CN108735247B - Driver circuit for charging a charging node - Google Patents

Abstract

A driver circuit is disclosed. The driver circuit includes a clamp transistor, a comparison voltage transistor, an amplifying transistor, a bias transistor, and a charging circuit. The comparison voltage transistor is configured to provide a comparison voltage. The amplifying transistor includes an amplifying gate connected to the first node of the clamping transistor, a first amplifying node configured to receive the comparison voltage, and a second amplifying node connected to the gate of the clamping transistor. The bias transistor is configured to supply a bias voltage. The charging circuit performs at least one of: is configured to draw current from the first node through the clamp transistor and is configured to supply current to the first node through the clamp transistor.

Description

Driver circuit for charging a charging node

Technical Field

Example embodiments of the inventive concepts described herein relate to a semiconductor circuit, and more particularly, to a driver circuit that charges a charging node.

Background

The memory device includes a plurality of memory cells. The plurality of memory cells are regularly arranged according to a specific pattern to reduce the area occupied by the memory cells. Memory cells arranged according to a regular pattern may be connected to conductive lines for accessing the memory cells.

As the number of memory cells connected to each conductive line increases and the distance between the conductive lines becomes shorter, the memory device is highly integrated. In this case, the resistive load and the capacitive load of each conductive line increase. When the resistive load and the capacitive load increase, much time is required to drive the voltage of the conductive line to a target level, and thus the operation speed of the memory device may be reduced. Accordingly, there is a need for an apparatus and method that can rapidly drive each conductive line with a target voltage even if the resistive load and capacitive load of each conductive line increase.

Disclosure of Invention

Example embodiments of the inventive concepts provide a driver circuit capable of reducing an occupied area and improving a driving speed.

According to an example embodiment of the inventive concepts, a driver circuit includes a clamp transistor, an amplifying transistor, a bias transistor, and a charging circuit. The clamp transistor includes a clamp gate, a first clamp node, and a second clamp node connected to the charging node. The comparison voltage transistor includes a comparison voltage gate configured to receive a reference voltage, a first comparison voltage node configured to receive a first voltage, and a second comparison voltage node configured to output a comparison voltage. The amplifying transistor includes an amplifying gate connected to the charging node, a first amplifying node connected to a second comparison voltage node of the comparison voltage transistor and configured to receive the comparison voltage, and a second amplifying node connected to a clamping gate of the clamping transistor. The bias transistor includes a bias gate configured to receive a bias voltage, a first bias node connected to a clamp gate of the clamp transistor, and a second bias node configured to receive a second voltage. The charging circuit performs one of the following: configured to draw current from the charging node through the clamp transistor and configured to supply current to the charging node through the clamp transistor.

In an example embodiment, the clamp transistor and the amplifying transistor may be PMOS transistors, and the comparison voltage transistor and the bias transistor may be NMOS transistors.

In an example embodiment, the first voltage may be a power supply voltage and the second voltage may be a ground voltage.

In an example embodiment, the clamp transistor and the amplifying transistor may be NMOS transistors, and the comparison voltage transistor and the bias transistor may be PMOS transistors.

In an example embodiment, the first voltage may be a ground voltage and the second voltage may be a power supply voltage.

In an example embodiment, the driver circuit may further include an enable transistor connected between the clamp gate of the clamp transistor and the second amplifying node of the amplifying transistor, and the enable transistor may be configured to receive the enable signal and to be activated or deactivated based on the enable signal.

In an example embodiment, the driver circuit may further include a voltage generator configured to supply a third voltage to the second clamping node of the clamping transistor.

In an example embodiment, the amplifying transistor may be configured to adjust the voltage of the clamp gate such that the voltage of the charging node reaches the target voltage.

In an example embodiment, the reference voltage may be based on a target voltage of the charging node, a threshold voltage of the comparison voltage transistor, and a threshold voltage of the amplifying transistor.

In an example embodiment, the charging node may be connected to one of a word line and a bit line connected to the memory cell.

According to example embodiments of the inventive concepts, a driver circuit includes a clamp switch, a charging circuit, a comparison voltage generator, a single stage amplifier, and a current bias circuit. The clamp switch includes a gate configured to receive a clamp voltage, a first node, and a second node connected to a charging node. The charging circuit is connected to a first node of the clamp switch. The charging circuit performs at least one of: configured to draw current from the charging node through the clamp switch and configured to supply current to the charging node through the clamp switch. The comparison voltage generator is configured to output a comparison voltage. The single stage amplifier is configured to amplify a difference between the comparison voltage and a voltage of the charging node. The single-stage amplifier is configured to output the clamp voltage as an amplification result. The current bias circuit is connected to the gate of the clamp switch. The current bias circuit is configured to adjust an amount of current flowing to a ground node to which the ground voltage is supplied through the comparison voltage generator, the single-stage amplifier, and the current bias circuit.

In an example embodiment, the single stage amplifier may include a transistor including a gate connected to the charging node, a first node connected to the comparison voltage generator, and a second node connected to the gate of the clamp switch.

In an example embodiment, the charging circuit may include a first transistor connected between a first node of the clamp switch and a first voltage node to which the first voltage is supplied, a second transistor connected to the first voltage node, and a current source connected between the second transistor and the first node of the clamp switch. The first transistor is configured to be activated in response to a discharge enable signal. The second transistor may be configured to be activated in response to a charge enable signal.

In an example embodiment, the comparison voltage generator may include a transistor including a gate configured to receive a reference voltage, a first comparison voltage node configured to receive a first voltage, and a second comparison voltage node configured to output a comparison voltage.

In an example embodiment, a current bias circuit may include a transistor having a gate configured to receive a bias voltage, a first bias node configured to receive a first voltage, and a second bias node connected to the gate of a clamp switch.

In an example embodiment, the driver circuit may further include a voltage generator configured to supply a set voltage to the charging node in response to the set enable signal.

In an example embodiment, the driver circuit may further include: the second clamp switch includes a second gate configured to receive a second clamp voltage and third and fourth nodes connected to the charging node, a second charging circuit connected to the third node of the second clamp switch, a second comparison voltage generator configured to output a second comparison voltage, a second single stage amplifier, and a second current bias circuit connected to the second gate of the second clamp switch. The second charging circuit may perform at least one of: configured to draw current from the charging node through the second clamp switch and configured to supply current to the charging node through the second clamp switch. The second single stage amplifier may be configured to amplify a difference between the second comparison voltage and the voltage of the charging node. The second single stage amplifier may be configured to output the second clamp voltage as an amplification result. The second current bias circuit may be configured to adjust an amount of current flowing through the second comparison voltage generator, the second single stage amplifier, and the second current bias circuit to a second ground node to which the ground voltage is supplied.

In an example embodiment, each of the clamp switch and the single stage amplifier may include a PMOS transistor, and each of the charging circuit and the current bias circuit may include an NMOS transistor.

In an example embodiment, each of the clamp switch and the single stage amplifier may include an NMOS transistor, and each of the charging circuit and the current bias circuit may include a PMOS transistor.

According to example embodiments of the inventive concepts, a driver circuit configured to charge conductive lines connected to a plurality of memory cells of a nonvolatile memory is provided. The driver circuit includes a clamp switch, a comparison voltage generator, a single stage amplifier, and a current bias circuit. The clamp switch includes a gate configured to receive a clamp voltage, a first node, and a second node connected to a charging node of the conductive line. The charging circuit is connected to the first node of the clamp switch and at least one of: configured to draw current from the charging node through the clamp switch and configured to supply current to the charging node through the clamp switch. The comparison voltage generator is configured to output a comparison voltage. The single stage amplifier is configured to amplify a difference between the comparison voltage and a voltage of the charging node. The single-stage amplifier is configured to output the clamp voltage as an amplification result. The current bias circuit is connected to the gate of the clamp switch and configured to adjust an amount of current flowing to a ground node to which the ground voltage is supplied through the comparison voltage generator, the single stage amplifier, and the current bias circuit.

According to an example embodiment, a driver circuit includes a clamp switch, a charging circuit, and a charging control circuit. The clamp switch includes a clamp gate configured to receive a clamp voltage, a first clamp node, and a second clamp node connected to the charging node. The charging circuit includes a charging circuit node connected to a first clamping node of the clamping switch. The charging circuit node may be connected to the set transistor and the discharge transistor. The charge control circuit includes an amplifier, a bias circuit, and an enable switch connected in series to each other. The amplifier includes a first amplifier node configured to receive the comparison voltage, an amplifier gate connected to the charging node, and a second amplifier node. The enabling switch includes: an enable gate configured to receive an enable signal for activating or deactivating the enable switch, a first enable node connected to the second amplifier node, and a second enable node connected to the bias circuit and the clamp gate. The bias circuit includes a first bias node and a second bias node connected to the gate of the clamp switch.

In an example embodiment, each of the clamp switch and the amplifier may include a PMOS transistor, and each of the charging circuit and the bias circuit may include an NMOS transistor.

In an example embodiment, each of the clamp switch and the amplifier may include an NMOS transistor, and each of the charging circuit and the bias circuit may include a PMOS transistor.

In an example embodiment, the charge control circuit may include a comparison voltage generator. The comparison voltage generator may include a first comparison node connected to the first voltage node, a comparison gate configured to receive the reference voltage, and a second comparison node configured to output the comparison voltage to the first amplifier node. The second bias node may be connected to a second voltage node. The first voltage may be one of a supply voltage and a ground voltage. The second voltage may be a different one of the supply voltage and the ground voltage.

In an example embodiment, the driver circuit may further include a bit line connected to the charging node. The driver circuit may be a precharge circuit of the memory device.

Drawings

The above and other features of the inventive concept will become apparent from the following description with reference to non-limiting embodiments as illustrated in the following drawings in which like reference numerals refer to like parts throughout the various drawings unless otherwise specified. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the inventive concepts. In the drawings:

Fig. 1 is a block diagram illustrating a driver circuit according to an example embodiment of the inventive concept;

fig. 2 is a block diagram illustrating an application of a driver circuit according to an example embodiment of the inventive concepts;

fig. 3 is a block diagram illustrating an application of a driver circuit according to an example embodiment of the inventive concepts;

fig. 4 is a circuit diagram illustrating an amplifier of a charge control circuit according to an example embodiment of the inventive concept;

fig. 5 is a diagram illustrating an application of a driver circuit according to an example embodiment of the inventive concept;

FIG. 6 is a block diagram illustrating an application of the driver circuit illustrated in FIG. 5;

FIG. 7 is a block diagram illustrating another application of the driver circuit illustrated in FIG. 5;

fig. 8 is a block diagram illustrating an application of the driver circuit illustrated in fig. 7;

fig. 9 is a block diagram illustrating a nonvolatile memory device to which a driver circuit is applied according to an example embodiment of the inventive concepts;

fig. 10 is a circuit diagram illustrating a memory block according to an example embodiment of the inventive concept;

fig. 11 is a block diagram illustrating a portion of a page buffer circuit to which a driver circuit is applied according to an example embodiment of the inventive concept;

Fig. 12 is a block diagram illustrating a portion of a row decoder circuit to which a driver circuit is applied according to an example embodiment of the inventive concepts;

fig. 13 is a block diagram illustrating another example of a nonvolatile memory device to which a driver circuit is applied according to an example embodiment of the inventive concept;

fig. 14 is a circuit diagram illustrating a memory tile according to an example embodiment of the inventive concept;

fig. 15 is a block diagram partially illustrating a row decoder circuit and sense amplifier and write driver circuits to each of which a driver circuit is applied according to an example embodiment of the inventive concept;

fig. 16 is a block diagram illustrating a storage device according to an example embodiment of the inventive concept;

fig. 17 is a block diagram illustrating a computing device according to an example embodiment of the inventive concepts; and

fig. 18 is a block diagram illustrating an application of a load circuit according to an example embodiment of the inventive concepts.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments of the inventive concepts to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like reference numerals and/or numerals in the drawings denote like elements, and thus their description may not be repeated.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. Other words used to describe relationships between elements or layers (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", "on …" versus "directly on …") should be interpreted in the same manner. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms "first," "second," and the like may be used herein to describe various elements, components, regions, layers and/or sections. These elements, components, regions, layers, and/or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.

Spatially relative terms, such as "below," "low," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" may include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including" and/or "including," if used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Expressions such as "at least one of … …" when following a list of elements, modify the entire list of elements without modifying individual elements of the list.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

While the corresponding plan view and/or perspective view of some cross-sectional view(s) may not be shown, the cross-sectional view(s) of the device structures illustrated herein provide support for multiple device structures that will expand in two different directions as illustrated in the plan view and/or in three different directions as illustrated in the perspective view. The two different directions may or may not be orthogonal to each other. The three different directions may include a third direction that may be orthogonal to the two different directions. Multiple device structures may be integrated in the same electronic device. For example, when one (a) device structure (e.g., a memory cell structure or a transistor structure) is illustrated in a cross-sectional view, an electronic device may include a plurality of device structures (e.g., memory cell structures or transistor structures) as illustrated by a plan view of the electronic device. The plurality of device structures may be arranged in an array and/or in a two-dimensional pattern.

Fig. 1 is a block diagram illustrating a driver circuit 10 according to an example embodiment of the inventive concept. Referring to fig. 1, a set voltage VSET may be supplied to one end of a load circuit LC. The set voltage VSET may be a target voltage to be charged to an internal conductive path of the load circuit LC. The driver circuit 10 may be connected to the load circuit LC through a conductive line including a charging node CN. The conductive line including the charging node CN may be electrically connected to an internal conductive path of the load circuit LC to be charged with the set voltage VSET. The driver circuit 10 may permit current to flow between the source of the set voltage VSET and the charging node CN through the internal conductive path of the load circuit LC. For example, the driver circuit 10 may draw current from the charging node CN or may supply current to the charging node CN. The load circuit LC may permit current to flow through an internal conductive path of the load circuit LC, thereby increasing the speed at which the voltage of the internal conductive path of the load circuit LC follows the set voltage VSET.

Referring to fig. 1, the driver circuit 10 may include a clamp switch CS, a charge control circuit CCC, and a charge circuit CC.

The clamp switch CS may adjust the amount of current supplied by the charging circuit CC to the charging node CN or the amount of current drawn by the charging circuit CC from the charging node CN under control of the charging control circuit CCC. For example, the clamp switch CS may include (or may be comprised of) a transistor having a gate configured to receive the clamp voltage VCLP from the charge control circuit CCC, a first node connected to the charge circuit CC, and a second node connected to the charge node CN. For example, the clamp switch CS may include (or may be composed of) a PMOS type transistor.

The charge control circuit CCC may adjust the clamp voltage VCLP to make it possible to adjust the amount of current drawn (or discharged) from the charge node CN or the load circuit LC through the clamp switch CS or the amount of current supplied (or flowing) to the charge node CN or the load circuit LC.

The charging circuit CC may include a discharge transistor DT, a set transistor ST, and a current source CUS. The discharge transistor DT may be connected between the clamp switch CS and a ground node to which a ground voltage is supplied. The discharge transistor DT may operate in response to the discharge enable signal en_d. The discharge enable signal en_d may be activated to discharge the internal conductive path or the charging node CN of the load circuit LC. When the discharge enable signal en_d is activated, the discharge transistor DT may be turned on, and thus the internal conductive path of the load circuit LC or the charge node CN may be connected with the ground node.

The set transistor ST and the current source CUS may be connected in series between the clamp switch CS and the ground node. The set transistor ST may operate in response to the charge enable signal en_ch. When the charge enable signal en_ch is activated, the set transistor ST may be turned on, and thus the internal conductive path of the load circuit LC or the charge node CN may be connected with a current source. In fig. 1, an example of an example embodiment according to the inventive concept is provided when a set transistor ST is disposed at a Clamp Switch (CS) side and a current source is disposed at a ground node side. However, the scope and spirit of the inventive concept may not be limited thereto. For example, the positions of the set transistor ST and the current source CUS may be changed.

In fig. 1, an example according to an example embodiment of the inventive concept is provided when a discharge transistor DT is connected to a ground node. However, the scope and spirit of the inventive concept may not be limited thereto. For example, the discharge transistor DT may be connected to a voltage node instead of the ground node. For example, the discharge transistor DT may be connected to a power supply node to which a power supply voltage is supplied.

As described above, the driver circuit 10 according to example embodiments of the inventive concept may draw current from or may supply current to the internal conductive path or the charging node CN of the load circuit LC, thereby increasing the speed at which the voltage of the internal conductive path or the charging node CN of the load circuit LC follows the set voltage VSET.

An example in which the clamp switch CS includes (or consists of) a PMOS type transistor is described with reference to fig. 1. However, the scope and spirit of the inventive concept may be applicable to the case where the clamp switch CS includes (or consists of) an NMOS type transistor.

Fig. 2 is a block diagram illustrating an application of the driver circuit 11 according to an example embodiment of the inventive concepts. The charge control circuit CCC1 of the driver circuit 11 is illustrated in more detail in fig. 2 compared to fig. 1. Referring to fig. 2, the charge control circuit CCC1 may be connected to a voltage source that outputs a clamp voltage VCMP having a fixed active level and a fixed inactive level. For example, when the charge enable signal en_ch is activated, the charge control circuit CCC1 may output a voltage having a fixed level sufficient to turn on the clamp switch CS as the clamp voltage VCLP. When the charge enable signal en_ch is deactivated, the charge control circuit CCC1 may output a voltage having a fixed level sufficient to turn off the clamp switch CS as the clamp voltage VCLP.

In the driver circuit 11 illustrated in fig. 2, the clamp voltage VCLP may have a fixed level when charging the internal conductive path or charging node CN of the load circuit LC. As the voltage of the internal conductive path of the load circuit LC or the voltage of the charging node CN approaches the set voltage VSET, the driving capability (capability), i.e., the amount of current supplied or drawn, of the driver circuit 11 may decrease. For this reason, it may take a lot of time to charge the internal conductive path or charging node CN of the load circuit LC up to the set voltage VSET.

Fig. 3 is a block diagram illustrating an application of the driver circuit 12 according to an exemplary embodiment of the inventive concept. The charge control circuit CCC2 of the driver circuit 12 is illustrated in more detail in fig. 3 compared to fig. 1. Referring to fig. 3, the charge control circuit CCC2 may include an amplifier AP. The positive input of the amplifier AP may be supplied with a reference voltage VREF. The charging node CN may be connected to the negative input of the amplifier AP. The output of the amplifier AP may be passed to the gate of the clamp switch CS as a clamp voltage VCLP.

In an initial state where charging starts, the voltage of the charging node CN or the voltage of the internal conductive path of the load circuit LC may be higher than the reference voltage VREF. The amplifier AP may apply a clamp voltage VCLP having a negative level to the gate of the clamp switch CS. If the voltage of the charging node CN or the voltage of the internal conductive path of the load circuit LC is higher than the reference voltage VREF, the amplifier AP may apply the clamping voltage VCLP having an amplified negative level to the gate of the clamping switch CS, and thus the clamping switch CS may permit a greater amount of current to flow through the internal conductive path of the load circuit LC and the charging node CN.

The difference between the voltage of the internal conductive path of the load circuit LC and the reference voltage VREF or the difference between the voltage of the charging node CN and the reference voltage VREF may be amplified according to the gain of the amplifier AP, and the amplification result may be applied to the clamp voltage VCLP. Accordingly, the amount of current passed through the clamp switch CS can be amplified by the gain of the amplifier AP, thereby improving the driving capability of the driver circuit 12.

When the voltage of the internal conductive path of the load circuit LC or the voltage of the charging node CN decreases and reaches the reference voltage VREF, the amplifier AP may pass the ground or positive output to the clamp switch CS, and thus the clamp switch CS may be turned on.

As described above, when the charge control circuit CCC2 includes the amplifier AP, the amount of current passed through the clamp switch CS can be amplified by the gain of the amplifier AP. This may mean that the driving capability of the driver circuit 12 is improved. In addition, when the amplifier AP is set up (established) together with the charging node CN and the clamp switch CS, the voltage of the charging node CN can be adjusted to the level of the reference voltage VREF by the amplifier AP. That is, when the level of the reference voltage VREF is set to be the same as or similar to the level of the set voltage VSET, the driver circuit 12 may allow the voltage of the internal conductive path of the load circuit LC or the voltage of the charging node CN to follow the same as or similar to the level of the set voltage VSET.

However, as illustrated in fig. 3, when the charge control circuit CCC2 includes the amplifier AP, the complexity, current consumption, and area of the charge control circuit CCC2 may increase.

Fig. 4 is a circuit diagram illustrating an amplifier AP of the charge control circuit CCC2 according to an example embodiment of the inventive concepts. Referring to fig. 4, the amplifier AP may include first to eighth transistors T1 to T8.

The first transistor T1 may have a gate configured to receive the inverting amplification enable signal/en_a, a first node connected to the clamp switch CS, and a second node connected to the ground node. The second transistor T2 may have a gate connected to the gate of the third transistor T3, a first node connected to the clamp switch CS, and a second node connected to the ground node. The first transistor T1 and the second transistor T2 may be connected in parallel.

The third transistor T3 may have a gate connected to the gate of the second transistor T2, a first node connected to the gate of the third transistor T3 to form a diode connection, and a second node connected to a ground node. The fourth transistor T4 may have a gate configured to receive the inverting amplification enable signal/en_a, a first node connected to the first node of the third transistor T3, and a second node connected to the ground node.

The fifth transistor T5 may have a gate to which the reference voltage VREF is supplied, a first node connected to the second node of the seventh transistor T7, and a second node connected to the clamp switch CS. The sixth transistor T6 may have a gate connected to the charging node CN, a first node connected to the second node of the seventh transistor T7, and a second node connected to the first node of the third transistor T3.

The seventh transistor T7 may have a gate to which the inverting amplification enable signal/en_a is supplied, a first node connected to the second node of the eighth transistor T8, and a second node connected to the first node of the fifth transistor T5. The eighth transistor T8 may have a gate to which the BIAS voltage BIAS is supplied, a first node connected to a power supply node to which the power supply voltage VCC is supplied, and a second node connected to the first node of the seventh transistor T7.

In an example embodiment, each of the first to fourth transistors T1 to T4 may be of an NMOS type, and each of the fifth to eighth transistors T5 to T8 may be of a PMOS type.

The first transistor T1, the fourth transistor T4, and the seventh transistor T7 may determine activation or deactivation of the amplifier AP. When the amplifier AP is activated, the inverting amplification enable signal/en_a may have a low level. In this case, the first transistor T1 and the fourth transistor T4 may be turned off, while the seventh transistor T7 may be turned on.

The second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 may constitute a differential amplifier. The eighth transistor T8 may function as a current controller that adjusts the amount of current flowing inside the amplifier AP based on the BIAS voltage BIAS.

When the amplifier AP is deactivated, the inverting amplification enable signal/en_a may have a high level. In this case, the seventh transistor T7 may be turned off, and thus the current path may be blocked. When the first transistor T1 is turned on by the high-level inverting amplification enable signal/en_a, the clamp switch CS may be connected to the ground node through the turned-on first transistor T1. Since the fourth transistor T4 is turned on by the high-level inverting amplification enable signal/en_a, the first node of the third transistor T3 may be connected to the ground node through the turned-on fourth transistor T4.

Referring to fig. 3 and 4, the amplifier AP included in the charge control circuit CCC2 may require at least 8 transistors, and thus the complexity and area of the driver circuit 12 may increase. In addition, the amplifier AP may include a first current path implemented with the fifth transistor T5 and a second current path implemented with the sixth transistor T6. Since current is consumed through two current paths, the current consumption of the driver circuit 12 may increase.

Fig. 5 is a diagram illustrating an application of the driver circuit 13 according to an example embodiment of the inventive concepts. The charge control circuit CCC3 of the driver circuit 13 is illustrated in more detail in fig. 5 compared to fig. 1. Referring to fig. 5, the charge control circuit CCC3 may include a bias circuit BC, an enable switch ES, a single stage amplifier SSA, and a comparison voltage generator CVG.

The bias circuit BC may be connected to the gate of the clamp switch CS. The BIAS circuit BC may be configured to adjust an amount of current flowing to the ground node to which the ground voltage is supplied through the comparison voltage generator CVG, the single stage amplifier SSA, and the BIAS circuit BC in response to the BIAS voltage BIAS. For example, the BIAS circuit BC may function as a current source that allows current to flow to the ground node in response to the BIAS voltage BIAS. The BIAS circuit BC may be connected between the gate of the clamp switch CS and the ground node and may comprise a transistor controlled by a BIAS voltage BIAS. For example, the bias circuit BC may comprise an NMOS transistor.

The enable switch ES may be connected between the bias circuit BC and the single stage amplifier SSA. The enable switch ES may determine activation or deactivation of the charge control circuit CCC3. The enable switch ES may be connected between the bias circuit BC and the single stage amplifier SSA and may include a transistor that operates in response to the amplified enable signal en_a. When the amplification enable signal en_a is activated, the transistor of the enable switch ES may be turned on, and thus the charge control circuit CCC3 may be activated. When the amplification enable signal en_a is deactivated, the transistor of the enable switch ES may be turned off, and thus the charge control circuit CCC3 may be deactivated. For example, the enable switch ES may include a PMOS transistor.

The single-stage amplifier SSA may be connected between the comparison voltage generator CVG and the enable switch ES. The single-stage amplifier SSA may amplify a difference between the comparison voltage VCOM from the comparison voltage generator CVG and the voltage of the charging node CN and may output the amplified voltage as the clamp voltage VCLP by enabling the switch ES. For example, the single-stage amplifier SSA may include a gate connected to the charging node CN, a first node configured to receive the comparison voltage VCOM from the comparison voltage generator CVG, and a second node outputting the clamping voltage VCLP through the enable switch ES. For example, the single stage amplifier may include PMOS transistors.

The comparison voltage generator CVG may output a comparison voltage VCOM determined according to the reference voltage VREF. The comparison voltage generator CVG may have a gate to which the reference voltage VREF is supplied, a first node connected to a power supply node to which the power supply voltage VCC is supplied, and a second node to which the comparison voltage VCOM is output. For example, the comparison voltage generator CVG may include an NMOS transistor.

The driver circuit 13 may drive the internal conductive path or charging node CN of the load circuit LC with a voltage lower than the present voltage (current voltage). Hereinafter, the operation of the driver circuit 13 will be described in more detail.

When the driver circuit 13 is activated, the enable switch ES may be turned on. For convenience of description, further description about the enable switch ES is omitted. The BIAS circuit BC may function as a current source through which a constant current determined by the BIAS voltage BIAS flows. The comparison voltage generator CVG may compare the reference voltage VREF with the power supply voltage VCC to output a comparison voltage VCOM lower than the power supply voltage VCC by a threshold voltage of a transistor of the comparison voltage generator CVG as a comparison result.

Because the bias circuit BC, which supplies the comparison voltage VCOM to the first node of the single-stage amplifier SSA and functions as a current source, is connected to the second node thereof, the single-stage amplifier SSA may function as a common source (common source) amplifier. The single stage amplifier SSA may have a negative gain. The single stage amplifier SSA may amplify a difference between the comparison voltage VCOM and the voltage of the charging node CN with a negative gain, and may output the amplified voltage as the clamp voltage VCLP.

In an initial state where charging starts, the voltage of the internal conductive path of the load circuit LC or the voltage of the charging node CN may be higher than the comparison voltage VCOM. Thus, the single-stage amplifier SSA may output a voltage having an absolute value (e.g., an amplified value) greater than a difference between the comparison voltage VCOM and the voltage of the charging node CN and a negative sign as the clamp voltage VCLP. The clamp switch CS may be turned on by the clamp voltage VCLP and thus the charging circuit CC may allow current to flow through the load circuit LC and the charging node CN. That is, the voltage of the internal conductive path of the load circuit LC and the charging node CN gradually decreases to the set voltage VSET.

As the voltage of the internal conductive path of the load circuit LC and the charging node CN decreases, the voltage difference between the comparison voltage VCOM and the charging node CN may also gradually decrease. When the voltage of the charging node CN reaches a voltage lower than the comparison voltage VCOM by the threshold voltage of the transistor of the single-stage amplifier SSA, the single-stage amplifier SSA may output the clamp voltage VCLP having the ground level or the positive level, and thus the clamp switch CS may be turned off. That is, the driver circuit 15 may allow the voltage of the charging node CN to follow a voltage lower than the reference voltage VREF by a voltage corresponding to the sum of the threshold voltage of the transistor of the comparative voltage generator CVG and the threshold voltage of the transistor of the single-stage amplifier SSA. When the reference voltage VREF is set to a voltage higher than the set voltage VSET by a voltage corresponding to the sum of the threshold voltage of the transistor of the comparison voltage generator CVG and the threshold voltage of the transistor of the single-stage amplifier SSA, the internal conductive path or the charging node CN of the load circuit LC may be driven with a voltage having the same or similar level as the set voltage VSET. In detail, the clamp switch CS can be driven by an amplifier, for example, a single-stage amplifier SSA, and thus the driving capability of the driver circuit 13 can be improved.

Even if the number of transistors constituting the charge control circuit CCC3 of fig. 5 is smaller than the number of transistors constituting the amplifier AP of fig. 4, the charge control circuit CCC2, the charge control circuit CCC3 can provide the same ability to set the target level of the output voltage using the reference voltage VREF and to improve the driving capability by amplifying the gain. In particular, the charge control circuit CCC3 of fig. 5 may use only one current path, and thus the charge control circuit CCC3 may consume one-fourth of the current compared to the amplifier AP of fig. 4. That is, when the charge control circuit CCC3 of fig. 5 is used, a function of setting a target level of an output voltage and improving driving capability with an amplification gain can be maintained, but power consumption and area of the driver circuit 13 can be reduced.

Fig. 6 is a block diagram illustrating an application of the driver circuit 14 similar to the driver circuit 13 illustrated in fig. 5. The driver circuit 14 of fig. 6 may be different from the driver circuit 13 of fig. 5 in that the set voltage VSET is not applied to the load circuit LC and the set voltage generator SVG is also included in the driver circuit 14. The set voltage generator SVG may include a voltage node to which the set voltage VSET is supplied and a transistor. The transistor may output the set voltage VSET in response to the charge enable signal en_ch. For example, when the transistor of the set voltage generator SVG is turned on by the activated set enable signal en_s, the internal conductive path of the charging node CN or the load circuit LC may be charged with the set voltage VSET.

In fig. 6, an example according to an example embodiment of the inventive concept is provided when the set voltage generator SVG supplies the set voltage VSET to the node between the clamp switch CS and the charging circuit CC. However, the scope and spirit of the inventive concept may not be limited thereto. For example, the set voltage generator SVG may be changed to supply the set voltage VSET to a node electrically connected to the charging node CN in the driver circuit 14. For example, the set voltage generator SVG may be configured to supply the set voltage VSET to a node between the charging node CN and the clamp switch CS, or directly supply the set voltage VSET to the charging node CN.

Fig. 7 is a block diagram illustrating another application of the driver circuit 13 illustrated in fig. 5. In an example embodiment, the driver circuit 13 of fig. 5 may be of PMOS type, while the driver circuit 15 of fig. 7 may be of NMOS type. The clamp switch CS of the driver circuit 13 of fig. 5 may be of PMOS type, while the clamp switch CS of the driver circuit 15 of fig. 7 may be of NMOS type. In addition, the charge control circuit CCC4 of the driver circuit 15 of fig. 7 may be different in structure from the charge control circuit CCC3 of the driver circuit 13 of fig. 5.

In comparison with the charging circuit CC of fig. 5, the charging circuit CC' of fig. 7 may include a discharging transistor DT, a setting transistor ST, and a current source CUS. The discharge transistor DT may be connected between a power supply node to which the power supply voltage VCC is supplied and the clamp switch CS. The discharge transistor DT may operate in response to the discharge enable signal en_d. Upon discharging the internal conductive path of the load circuit LC or the charging node CN, the discharge enable signal en_d may be activated. When the discharge enable signal en_d is activated, the discharge transistor DT may be turned on, and thus the internal conductive path of the load circuit LC or the charge node CN may be connected with the power supply node.

The set transistor ST and the current source CUS may be connected in series between the power supply node and the clamp switch CS. The set transistor ST may operate in response to the charge enable signal en_ch. When the charge enable signal en_ch is activated, the set transistor ST may be turned on, and thus the internal conductive path or charge node CN of the load circuit LC may be connected with the current source CUS. In fig. 7, an example of an example embodiment according to the inventive concept is provided when the set transistor ST is disposed at the power supply node side and the current source CUS is disposed at the Clamp Switch (CS) side. However, the scope and spirit of the inventive concept may not be limited thereto. For example, the positions of the set transistor ST and the current source CUS may be changed.

Further, an example of an example embodiment according to the inventive concept is provided in fig. 7 when the discharge transistor DT is connected to a power supply node. However, the scope and spirit of the inventive concept may not be limited thereto. For example, the discharge transistor DT may be connected to a voltage node instead of the ground node. For example, the discharge transistor DT may be connected to a ground node to which a ground voltage is supplied.

Referring to fig. 7, the charge control circuit CCC4 may include a bias circuit BC, an enable switch ES, a single stage amplifier SSA, and a comparison voltage generator CVG.

The bias circuit BC may be connected to the gate of the clamp switch CS. The BIAS circuit BC may be configured to adjust an amount of current flowing to the ground node to which the ground voltage is supplied through the comparison voltage generator CVG, the single stage amplifier SSA, and the BIAS circuit BC in response to the BIAS voltage BIAS. For example, the BIAS circuit BC may function as a current source that outputs a current in response to the BIAS voltage BIAS. The BIAS circuit BC may be connected between the gate of the clamp switch CS and the power supply node and may comprise a transistor controlled by a BIAS voltage BIAS. For example, the bias circuit BC may comprise a PMOS transistor.

The enable switch ES may be connected between the bias circuit BC and the single stage amplifier SSA. The enable switch ES may determine activation or deactivation of the charge control circuit CCC 4. The enable switch ES may be connected between the bias circuit BC and the single stage amplifier SSA and may include a transistor that operates in response to the amplified enable signal en_a. When the amplification enable signal en_a is activated, the transistor of the enable switch ES may be turned on, and thus the charge control circuit CCC4 may be activated. When the amplification enable signal en_a is deactivated, the transistor of the enable switch ES may be turned off, and thus the charge control circuit CCC4 may be deactivated. For example, the enable switch ES may include an NMOS transistor.

The single-stage amplifier SSA may be connected between the comparison voltage generator CVG and the enable switch ES. The single-stage amplifier SSA may amplify a difference between the comparison voltage VCOM from the comparison voltage generator CVG and the voltage of the charging node CN and may output the amplified voltage as the clamp voltage VCLP by enabling the switch ES. For example, the single-stage amplifier SSA may include a gate connected to the charging node CN, a first node configured to receive the comparison voltage VCOM from the comparison voltage generator CVG, and a second node outputting the clamping voltage VCLP through the enable switch ES. For example, the single-stage amplifier SSA may include an NMOS transistor.

The comparison voltage generator CVG may output a comparison voltage VCOM determined according to the reference voltage VREF. The comparison voltage generator CVG may have a gate to which the reference voltage VREF is supplied, a first node connected to a ground node to which the ground voltage is supplied, and a second node to output the comparison voltage VCOM. For example, the comparison voltage generator CVG may include a PMOS transistor.

The driver circuit 15 may drive the internal conductive path or charging node CN of the load circuit LC with a voltage higher than the present voltage. Hereinafter, the operation of the driver circuit 13 will be described in more detail.

The enable switch ES may be turned on when the driver circuit 15 is activated. For convenience of description, further description about the enable switch ES is omitted. The bias circuit BC may function as a current source through which a constant current flows. The comparison voltage generator CVG may compare the reference voltage VREF with the ground voltage to output a comparison voltage VCOM higher than the ground voltage by a threshold voltage of a transistor of the comparison voltage generator CVG as a comparison result.

Because the bias circuit BC, which supplies the comparison voltage VCOM to the first node of the single-stage amplifier SSA and functions as a current source, is connected to the second node thereof, the single-stage amplifier SSA can function as a common-source amplifier. The single stage amplifier SSA may have a negative gain. The single-stage amplifier SSA may amplify a difference between the comparison voltage VCOM and the voltage of the charging node CN with a negative gain and may output the amplified voltage as the clamp voltage VCLP.

In an initial state where charging starts, the voltage of the internal conductive path of the load circuit LC or the voltage of the charging node CN may be lower than the comparison VCOM. Thus, the single-stage amplifier SSA may output a voltage having an absolute value (e.g., an amplified value) greater than a difference between the comparison voltage VCOM and the voltage of the charging node CN and being positive as the clamp voltage VCLP. The clamp switch CS may be turned on by the clamp voltage VCLP and thus the charging circuit CC' may allow current to flow through the load circuit LC and the charging node CN. That is, the voltage of the internal conductive path of the load circuit LC and the charging node CN may gradually increase to the set voltage VSET.

As the voltage of the internal conductive path of the load circuit LC and the charging node CN increases, the voltage difference between the comparison voltage VCOM and the voltage of the charging node CN may also gradually decrease. When the voltage of the charging node CN reaches a voltage higher than the comparison voltage VCOM by the threshold voltage of the transistor of the single-stage amplifier SSA, the single-stage amplifier SSA may output the clamp voltage VCLP having the ground level or the negative level, and thus the clamp switch CS may be turned off. That is, the driver circuit 15 may allow the voltage of the charging node CN to follow a voltage higher than the reference voltage VREF by a voltage corresponding to the sum of the threshold voltage of the transistor of the comparative voltage generator CVG and the threshold voltage of the transistor of the single-stage amplifier SSA. When the reference voltage VREF is set to a voltage lower than the set voltage VSET by a voltage corresponding to the sum of the threshold voltage of the transistor of the comparison voltage generator CVG and the threshold voltage of the transistor of the single-stage amplifier SSA, the internal conductive path or the charging node CN of the load circuit LC may be driven with a voltage having the same or similar level as the set voltage VSET. In particular, the clamp switch CS can be driven by an amplifier, particularly a single-stage amplifier SSA, and thus the driving capability of the driver circuit 15 can be improved.

Even if the number of transistors constituting the charge control circuit CCC4 of fig. 7 is smaller than the number of transistors constituting the amplifier AP of fig. 4, the charge control circuit CCC4 can provide the same ability to set the target level of the output voltage using the reference voltage VREF and to improve the driving ability by amplifying the gain. Specifically, the charge control circuit CCC4 of fig. 7 may use only one current path, and thus the charge control circuit CCC4 may consume one-fourth of the current compared to the amplifier AP of fig. 4. That is, when the charge control circuit CCC4 of fig. 7 is used, a function of setting a target level of an output voltage and improving driving capability with an amplification gain can be maintained, but power consumption and area of the driver circuit 15 can be reduced.

Fig. 8 is a block diagram illustrating an application of the driver circuit 16. The driver circuit 16 of fig. 8 may be different from the driver circuit 15 of fig. 7 in that the set voltage VSET is not applied to the load circuit LC and the set voltage generator SVG is also included in the driver circuit 15. The set voltage generator SVG may include a voltage node to which the set voltage VSET is supplied and a transistor. The transistor may output the set voltage VSET in response to the set enable signal en_s. For example, when the transistor of the set voltage generator SVG is turned on by the activated set enable signal en_s, the internal conductive path of the charging node CN or the load circuit LC may be charged with the set voltage VSET.

In fig. 8, an example according to an example embodiment of the inventive concept is provided when the set voltage generator SVG supplies the set voltage VSET to the node between the clamp switch CS and the charging circuit CC'. However, the scope and spirit of the inventive concept may not be limited thereto. For example, the set voltage generator SVG may be changed to supply the set voltage VSET to a node electrically connected to the charging node CN in the driver circuit 16. For example, the set voltage generator SVG may be configured to supply the set voltage VSET to a node between the charging node CN and the clamp switch CS, or directly supply the set voltage VSET to the charging node CN.

Referring to fig. 5 to 8, various exemplary embodiments of the inventive concept are described. At least two of the driver circuits of fig. 5-8 may be embodied as a single load circuit. For example, one of the driver circuits of fig. 5 and 6 that decreases the voltage of the charging node, and one of the driver circuits of fig. 7 and 8 that increases the voltage of the charging node may be embodied to adjust the voltage associated with a single load circuit.

Fig. 9 is a block diagram illustrating a nonvolatile memory device to which a driver circuit is applied according to an example embodiment of the inventive concepts. In an example embodiment, a NAND flash memory device is illustrated in fig. 9.

Referring to fig. 9, the nonvolatile memory device 110 may include a memory cell array 111, a row decoder circuit 113, a page buffer circuit 115, a data input/output circuit 117, and a control logic circuit 119.

The memory cell array 111 may include a plurality of memory blocks BLK1 to BLKz. The memory blocks BLK1 to BLKz may be arranged along a column direction. Each memory block may have a three-dimensional structure that expands in a row direction, a column direction, and a height direction. Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. Each of the memory blocks BLK1 to BLKz may be connected to the row decoder circuit 113 through at least one string selection line SSL, a plurality of word lines WL, and at least one ground selection line GSL. Each of the memory blocks BLK1 to BLKz may be connected to the page buffer circuit 115 through a plurality of bit lines BL. The bit lines BL may extend in the column direction, and the memory blocks BLK1 to BLKz may be commonly connected to the bit lines BL. The memory cells in the memory blocks BLK1 to BLKz may have the same structure.

In an example embodiment, each of the memory blocks BLK1 to BLKz may be a unit of an erase operation. Memory cells in the memory cell array 111 may be erased in memory blocks. Memory cells in a memory block may be erased simultaneously. In other embodiments, each memory block may be divided into a plurality of sub-blocks. The erasure can be performed in sub-blocks.

In an example embodiment, each of the memory blocks BLK1 through BLKz may include physical memory spaces that are distinguished by block addresses. Each of the word lines WL may correspond to a physical memory space differentiated by row address. Each of the bit lines BL may correspond to a physical memory space distinguished by a column address.

The row decoder circuit 113 may be connected to the memory cell array 111 through a plurality of ground selection lines GSL, a plurality of word lines WL, and a plurality of string selection lines SSL. The row decoder circuit 113 may operate according to the control of the control logic circuit 119. The row decoder circuit 113 may decode an address received from the controller through an input/output channel, and may switch voltages to be applied to at least one string selection line SSL, word line WL, and at least one ground selection line GSL based on the decoded address.

For example, during a programming operation, the row decoder circuit 113 may apply a programming voltage to a selected word line in a memory block selected by address. The row decoder circuit 113 may also apply a pass voltage (pass voltage) to unselected word lines in the selected memory block. During a read operation, the row decoder circuit 113 may apply a select read voltage to a selected word line in a selected memory block. The row decoder circuit 113 may also apply non-selected read voltages to unselected word lines in the selected memory block. During an erase operation, the row decoder circuit 113 may apply an erase voltage (e.g., a ground voltage or a voltage having a level similar to that of the ground voltage) to the word lines in the selected memory block.

The page buffer circuit 115 may be connected to the memory cell array 111 through a bit line BL. The page buffer circuit 115 may be connected to the memory cell array 111 through a bit line BL. The page buffer circuit 115 may operate under the control of the control logic circuit 119.

During a program operation, the page buffer circuit 115 may store data to be programmed in the memory cells. The page buffer circuit 115 may apply a voltage to the bit line BL based on the stored data. For example, the page buffer circuit 115 may function as a write driver. During a read operation, the page buffer circuit 115 may read out the voltage on the bit line BL and may store the read out result. For example, the page buffer circuit 115 may function as a sense amplifier.

The data input/output circuit 117 may be connected to the page buffer circuit 115 through a data line DL. The data input/output circuit 117 may output data read by the page buffer circuit 115 to the controller through an input/output channel, and may transfer data received from the controller through the input/output channel to the page buffer circuit 115.

The control logic 119 may receive commands from the controller via an input/output channel and may receive control signals therefrom via a control channel. The control logic circuit 119 may receive a command through an input/output channel in response to a control signal, may route an address received through the input/output channel to the row decoder circuit 113, and may route data received through the input/output channel to the data input/output circuit 117. The control logic 119 may decode the received command and may control the nonvolatile memory device 110 based on the decoded command.

In an example embodiment, during a read operation, the control logic 119 may generate the data strobe signal DQS based on a read enable signal/RE received from the controller over a control channel. The data strobe signal DQS thus generated may be output to the controller through a control channel. During a programming operation, the control logic 119 may receive a data strobe signal DQS from the controller through a control channel.

Fig. 10 is a circuit diagram illustrating a memory block BLKa according to an example embodiment of the inventive concept. Referring to fig. 10, the memory block BLKa may include a plurality of cell strings CS11 to CS21 and CS12 to CS22. The plurality of cell strings CS11 to CS21 and CS12 to CS22 may be arranged along the row direction and the column direction to constitute rows and columns.

For example, the cell strings CS11 and CS12 arranged in the row direction may constitute a first row, and the cell strings CS21 and CS22 arranged in the row direction may constitute a second row. The cell strings CS11 and CS21 arranged along the column direction may constitute a first column, and the cell strings CS12 and CS22 arranged along the column direction may constitute a second column.

Each cell string may include a plurality of cell transistors. In each cell string, the cell transistors may include a ground selection transistor GST, memory cells MC1 to MC6, and string selection transistors SSTa and SSTb. The ground selection transistors GST, the memory cells MC1 to MC6, and the string selection transistors SSTa and SSTb in each cell string may be stacked in a height direction perpendicular to a plane (e.g., a plane on a substrate of the memory block BLKa) on which the cell strings CS11 to CS21 and CS12 to CS22 are arranged along rows and columns.

Each cell transistor may be a charge trapping type cell transistor whose threshold voltage varies according to the amount of charge trapped in its insulating layer.

The sources of the lowermost ground selection transistors GST may be commonly connected to the common source line CSL.

The control gates of the ground selection transistors GSTa of the cell strings CS11 and CS12 in the first row may be commonly connected to the ground selection line GSL1, and the control gates of the ground selection transistors GSTb of the cell strings CS21 and CS22 in the second row may be commonly connected to the ground selection line GSL2. That is, cell strings in different rows may be connected to different ground select lines.

In an example embodiment, the memory block BLKa may be modified or changed such that the ground selection lines connected to the ground selection transistors belonging to the same row and placed at different heights are connected to different ground selection lines. In an example embodiment, the memory block BLKa may be modified or changed such that the ground selection lines connected to the ground selection transistors belonging to different rows and placed at the same height are interconnected and commonly controlled. In an example embodiment, the memory block BLKa may be modified or changed such that the ground select lines connected to the ground select transistors are interconnected and commonly controlled.

Commonly connected to the word lines are control gates of memory cells placed at the same height (or order) relative to the substrate (or ground selection transistor GST). Connected to the different word lines WL1 to WL6 are control gates of memory cells placed at different heights (or orders). For example, the memory cells MC1 may be commonly connected to the word line WL1. The memory cells MC2 may be commonly connected to the word line WL2. The memory cells MC3 may be commonly connected to the word line WL3. Memory cell MC4 may be commonly connected to word line WL4. The memory cells MC5 may be commonly connected to the word line WL5. The memory cells MC6 may be commonly connected to the word line WL6.

Among the first string selection transistors SSTa of the cell strings CS11 to CS21 and CS12 to CS22 having the same height (or order), the control gates of the first string selection transistors SSTa in different rows may be connected to different string selection lines SSL1a and SSL2a. For example, the first string selection transistors SSTa of the cell strings CS11 and CS12 may be commonly connected to the string selection line SSL1a. The first string selection transistors SSTa of the cell strings CS21 and CS22 may be commonly connected to a string selection line SSL2a.

Among the second string selection transistors SSTb of the cell strings CS11 to CS21 and CS12 to CS22 having the same height (or order), the control gates of the second string selection transistors SSTb in different rows may be connected to different string selection lines SSL1b and SSL2b. For example, the second string selection transistors SSTb of the cell strings CS11 and CS12 may be commonly connected to the string selection line SSL1b. The second string selection transistors SSTb of the cell strings CS21 and CS22 may be commonly connected to a string selection line SSL2b.

That is, cell strings in different rows may be connected to different string select lines. String selection transistors having the same height (or order) and belonging to the same cell string of the row may be connected to the same string selection line. String selection transistors having different heights (or orders) and belonging to the same cell string of the row may be connected to different string selection lines.

In an exemplary embodiment, string selection transistors of cell strings in the same row may be commonly connected to a string selection line. For example, the string selection transistors SSTa and SSTb of the cell strings CS11 and CS12 in the first row may be commonly connected to a string selection line. The string selection transistors SSTa and SSTb of the cell strings CS21 and CS22 in the second row may be commonly connected to a string selection line.

The columns of cell strings CS11 to CS21 and CS12 to CS22 may be connected to different bit lines BL1 and BL2, respectively. For example, the string selection transistors SSTb of the cell strings CS11 and CS21 in the first column may be commonly connected to the bit line BL1. The string selection transistors SSTb of the cell strings CS12 and CS22 in the second column may be commonly connected to the bit line BL2.

The cell strings CS11 and CS12 may constitute a first plane. The cell strings CS21 and CS22 may constitute a second plane.

In the memory block BLKa, memory cells of each plane placed at the same height may constitute a physical page. The physical page may refer to a unit in which the memory cells MC1 to MC6 are written and read. For example, one plane of the memory block BLKa may be selected by the string selection lines SSL1a, SSL1b, SSL2a, and SSL2 b. When on voltages are supplied to the string selection lines SSL1a and SSL1b, respectively, and off voltages are supplied to the string selection lines SSL2a and SSL2b, respectively, the cell strings CS11 and CS12 in the first plane may be connected to the bit lines BL1 and BL2. That is, the first plane may be selected. When the on voltage is supplied to the string selection lines SSL2a and SSL2b, respectively, and the off voltage is supplied to the string selection lines SSL1a and SSL1b, respectively, the cell strings CS21 and CS22 in the second plane may be connected to the bit lines BL1 and BL2. That is, the second plane may be selected. In the selected plane, one row of memory cells MC may be selected by word lines WL1 to WL6. In the selected row, a selection voltage may be applied to the second word line WL2, and non-selection voltages may be applied to the remaining word lines WL1 and WL3 to WL6, respectively. The physical page of the second word line WL2 corresponding to the second plane may be selected by adjusting voltages of the string selection lines SSL1a, SSL1b, SSL2a and SSL2b and the word lines WL1 to WL6. A write or read operation may be performed with respect to the memory cell MC2 in the selected physical page.

For example, two or more bits may be written in each memory cell MC. Bits written to memory cells belonging to one physical page may be used to define a logical page. The first bit written to a memory cell belonging to one physical page may constitute a first logical page. The nth bit written to a memory location belonging to one physical page may constitute the nth logical page. A logical page may refer to a unit of data access. When a read operation is performed with respect to one physical page, data may be accessed in logical pages.

In the memory block BLKa, the memory cells MC1 to MC6 may be erased by memory block or by sub-block. When erasing is performed per memory block, all memory cells MC in the memory block BLKa may be simultaneously erased according to an erase request (e.g., an erase request from an external controller). When the erasure is performed in sub-blocks, a part of the memory cells MC in the memory block BLKa may be erased simultaneously according to an erasure request (e.g., an erasure request from an external controller), and other memory cells MC may be inhibited from being erased. A low voltage (e.g., a ground voltage or a low voltage having a level similar to that of the ground voltage) may be supplied to a word line connected to the memory cell MC to be erased, and the word line connected to the memory cell MC to be inhibited from erasing may be floated.

The memory block BLKa shown in fig. 10 is an example. However, the scope and spirit of the inventive concept may not be limited thereto. For example, the number of rows of cell strings may be increased or decreased. As the number of rows of cell strings changes, the number of string or ground select lines and the number of cell strings connected to bit lines may also change.

The number of columns of cell strings may be increased or decreased. As the number of columns of cell strings changes, the number of bit lines connected to the columns of cell strings and the number of cell strings connected to the string selection lines may also change.

The height of the cell strings may be increased or decreased. For example, the number of ground selection transistors, memory cells, or string selection transistors stacked in each cell string may be increased or decreased.

In an example embodiment, the memory cells MC in a physical page may correspond to at least three logical pages. For example, k bits (k is an integer of 2 or more) may be programmed in the memory cell MC. The memory cells MC of the physical page may store k logical pages, each of which is composed of the nth bit programmed in the memory cells MC, respectively.

As described above, the memory block BLKa may be embodied as a three-dimensional memory array. The 3D memory array may be formed monolithically (monolithics) on a substrate (e.g., a semiconductor substrate such as silicon or a semiconductor-on-insulator substrate). The 3D memory array may include two or more physical levels (physical levels) of memory cells having active areas disposed on a substrate and circuitry associated with the operation of those memory cells, whether such associated circuitry is on or within such a substrate. The layers of each level of the array are deposited directly on the layers of each underlying level of the array.

In example embodiments of the inventive concepts, a 3D memory array includes vertical NAND strings (or cell strings) oriented vertically such that at least one memory cell is located on another memory cell. The at least one memory cell MC may include a charge trapping layer. Each vertical NAND string may also include at least one select transistor placed on a memory cell MC. At least one selection transistor may have the same structure as the memory cell MC and may be uniformly formed using the memory cell MC.

The following patent documents, which are incorporated herein by reference in their entirety, describe suitable configurations for three-dimensional memory arrays configured into a plurality of levels, with word lines and/or bit lines shared between the levels: U.S. patent No. 7,679,133; 8,553,466; 8,654,587; 8,559,235; U.S. patent publication 2011/023648.

As described above, the memory blocks BLK1 to BLKz may share the bit line BL. Each bit line may be connected to a plurality of cell strings in each memory block. Because of the resistive and capacitive loading of each bit line, it may take a lot of time to drive each bit line up to the target voltage. The driver circuit 13, 14, 15 or 16 according to example embodiments of the inventive concepts may be used to reduce the time taken to drive each bit line up to a target voltage. As such, the driver circuit 13, 14, 15 or 16 according to example embodiments of the inventive concepts may be used to reduce the time taken to drive each word line up to the target voltage.

Fig. 11 is a block diagram illustrating a portion of a page buffer circuit 115 to which a driver circuit is applied according to an example embodiment of the inventive concept. In an example embodiment, components of the page buffer circuit 115 corresponding to one bit line BL are illustrated in fig. 11. Referring to fig. 11, the page buffer circuit 115_1 may include a precharge circuit PC connected to the bit line BL and a page buffer PB.

The page buffer PB may include a sense (sense) latch SL, a first dump circuit (dump circuit) DC1, first to kth data latches DL1 to DLk, a second dump circuit DC2, and a cache latch CL.

The Sense Latch (SL) may perform a bias operation in which a voltage (e.g., a set voltage VSET) is applied to the bit line BL based on the stored bit or a sense operation in which the bit is stored according to the voltage bit on the bit line BL. The sense latch LL may store bits that may be transferred through the first transfer circuit DC1 and may transfer bits stored therein to the first transfer circuit DC 1.

The first dumping circuit DC1 may store bits in the sense latch SL based on the bits stored in the data latches DL1 to DLk, or may perform a dumping operation to transfer the bits stored in the sense latch SL to one of the data latches DL1 to DLk.

Each of the data latches DL1 to DLk can store a bit transferred from the sense latch SL through the first transfer latch DC1, i.e., a bit read from a memory cell connected to the bit line BL. Alternatively, the data latches DL1 to DLk may store bits to be transferred to the sense latch SL through the first transfer latch DC1, i.e., bits to be written to memory cells connected to the bit line BL. The selected data latch from the first through kth data latches DL1 through DLk may transfer the bit stored therein to the second dump circuit DC 2. The selected data latch from the first to kth data latches DL1 to DLk may store the bit transferred from the second dump circuit DC 2. The number of data latches DL1 to DLk may be the same as or greater than the number of bits to be written to the memory cells connected to the bit line BL.

The second dump circuit DC2 may transfer data stored in a data latch selected from the data latches DL1 to DLk to the cache latch CL. The second dump circuit DC2 may transfer the bits stored in the cache latch CL to a data latch selected from the data latches DL1 to DLk.

The precharge circuit PC may include one or more of the driver circuits 13 to 16 described with reference to fig. 5 to 8. For example, the precharge circuit PC may be configured to charge the bit line BL with a set voltage VSET (e.g., a power supply voltage). At this time, the precharge circuit PC may control the bit line BL using one or more driver circuits so as to follow the same or similar level as the set voltage VSET. When the set voltage VSET (e.g., a power supply voltage or a ground voltage) is established on the bit line BL through the sense latch SL, the voltage of the bit line BL may be adjusted to follow the same or similar level as the set voltage VSET.

In an example embodiment, the sense latch SL may include one or more of the driver circuits 13 to 16 described with reference to fig. 5 to 8. For example, the sense latch SL may be configured to establish a ground voltage or a power supply voltage based on the bit line BL stored therein. The sense latch SL may use one or more driver circuits to perform the biasing operations described above.

Fig. 12 is a block diagram illustrating a portion of a row decoder circuit 113 to which a driver circuit is applied according to an example embodiment of the inventive concept. In an example embodiment, components of the row decoder circuit 113_1 corresponding to one memory block are illustrated in fig. 12. Referring to fig. 12, the row decoder circuit 113_1 may include transfer (pass) transistors connected to word lines WL1 to WLn, a block decoder BDEC, and a word line driver WLD of a memory block, respectively.

The word line driver WLD may be configured to drive a plurality of internal lines SI. In an example embodiment, the number of internal lines SI driven by the word line driver WLD may be the same as the number of word lines belonging to one memory block. The internal line SI may correspond to a word line of each memory block.

The block decoder BDEC may select one of the plurality of memory blocks BLK1 to BLKz based on the block address supplied to the row decoder circuit 113_1 (refer to fig. 9). The block decoder BDEC may turn on the transfer transistor PTR corresponding to the selected memory block. That is, the block decoder BDEC may electrically connect the word lines WL1 to WLn of the selected memory block to the internal line SI, respectively.

The word line driver WLD may include one or more of the driver circuits 13 to 16 described with reference to fig. 5 to 8. The word line driver WLD may drive the internal lines SI and the word lines WL1 to WLn using one or more driver circuits.

A ground selection line driver that drives the ground selection line GSL and a string selection line driver that drives the string selection line SSL may be included in the row decoder circuit 113_1. Each of the string select line driver and the ground select line driver may be configured to drive a corresponding select line using one or more driver circuits.

Fig. 13 is a block diagram illustrating another example of a nonvolatile memory device to which a driver circuit is applied according to an example embodiment of the inventive concept. In an example embodiment, a cross-point type memory device is illustrated in fig. 13. The cross point type memory device may have a structure in which memory cells connected to word lines and bit lines are disposed at intersections (cross points) of the word lines and the bit lines. In example embodiments, nonvolatile RAM such as Resistive Random Access Memory (RRAM), phase change RAM (PRAM), ferroelectric RAM (FeRAM), and Magnetic RAM (MRAM) may be implemented to have a cross point type.

Referring to fig. 13, the nonvolatile memory device 210 may include a memory cell array 211, a row decoder circuit 213, a sense amplifier and write driver circuit 215, a data input/output circuit 217, and a control logic circuit 219.

The memory cell array 111 may include a plurality of memory TILEs TILE1 through TILE z. The memory TILEs TILE1 to TILE z may be arranged in the height direction. Each memory tile may have a three-dimensional structure that extends along a row direction, a column direction, and a height direction. The memory TILEs TILE1 through TILEz may be commonly connected to the row decoder circuit 213 through a plurality of global word lines GWL. The memory TILEs TILE1 through TILEz may be commonly connected to the sense amplifier and write driver circuitry 215 through a plurality of global bit lines GBL.

Each memory tile may include a plurality of memory cells. The plurality of memory cells of each memory tile may be connected to a plurality of word lines respectively connected to global word lines GWL. The word lines belonging to each memory tile may be independent of the other memory tiles. The plurality of memory cells of each memory tile may be connected to a plurality of bit lines respectively connected to global bit lines GBL. The bit lines belonging to each memory tile may be independent of the other memory tiles.

The row decoder circuit 213 may be connected to the memory cell array 211 through a global bit line GBL. The row decoder circuit 213 may operate according to the control of the control logic circuit 219. The row decoder circuit 213 may decode an address received from the controller through the input/output channel and may control a voltage to be applied to the global word line GWL based on the decoded address.

The sense amplifier and write driver circuit 215 may be connected to the memory cell array 211 through a global bit line GBL. The sense amplifier and write driver circuit 215 may be connected to the data input output circuit 217 through a plurality of data lines DL. The sense amplifier and write driver circuit 215 may operate under the control of the control logic circuit 219.

The data input/output circuit 217 may be connected to the sense amplifier and write driver circuit 215 through a data line DL. The data input/output circuit 217 may output data read by the sense amplifier and write driver circuit 215 to the controller through an input/output channel, and may pass data received from the controller through the input/output channel to the sense amplifier and write driver circuit 215.

The control logic 219 may receive commands from the controller via an input/output channel and may receive control signals therefrom via a control channel. The control logic 219 may receive a command through an input/output channel in response to a control signal, may route an address received through the input/output channel to the row decoder circuit 213, and may route data received through the input/output channel to the data input/output circuit 217. The control logic 219 may decode the received command and may control the nonvolatile memory device 210 based on the decoded command.

Fig. 14 is a circuit diagram illustrating a memory tile TILEk according to an example embodiment of the inventive concepts. As illustrated in fig. 14, the memory tile TILEk may include word lines and bit lines sequentially stacked in a height direction. For example, in fig. 14, bit lines bl1_1 and bl1_2 may be disposed at a first plane. The bit lines bl1_1 and bl1_2 may extend along the column direction and may be spaced apart from each other along the row direction.

The word lines wl1_1 and wl1_2 may be disposed at a second plane on the first plane. The word lines wl1_1 and wl1_2 may extend along the row direction and may be spaced apart from each other along the column direction.

The memory cell may be formed between the first plane and the second plane and may be disposed at intersections of the bit lines bl1_1 and bl1_2 and the word lines wl1_1 and wl1_2, respectively. Each memory cell may be connected to a word line and a bit line.

Bit lines bl2_1 and bl2_2 may be disposed at a third plane on the second plane. The bit lines bl2_1 and bl2_2 may extend along the column direction and may be spaced apart from each other along the row direction.

The memory cell may be formed between the second plane and the third plane and may be disposed at intersections of the bit lines bl2_1 and bl2_2 and the word lines wl1_1 and wl1_2, respectively. Each memory cell may be connected to a word line and a bit line.

Word lines wl2_1 and wl2_2 may be disposed at a fourth plane on the third plane. The word lines wl2_1 and wl2_2 may extend along the row direction and may be spaced apart from each other along the column direction.

The memory cell may be formed between the third plane and the fourth plane and may be disposed at intersections of the bit lines bl2_1 and bl2_2 and the word lines wl2_1 and wl2_2, respectively. Each memory cell may be connected to a word line and a bit line.

Each memory cell may include a variable resistor element VR and a select element S. When the voltages of the word line and the bit line belong to the first condition, the resistance value of the variable resistor element VR may be increased (e.g., may be set or written). When the voltages of the word line and the bit line belong to the second condition, the resistance value of the variable resistor element VR may be reduced (e.g., may be reset or erased). The resistance value of the variable resistor element VR may be maintained when the word line and bit line voltages do not belong to the first condition and the second condition.

The selection element S may comprise a diode. The selection element S may provide a selection of the corresponding memory cell. For example, the selection element S may select a corresponding memory cell by passing a current based on voltages of the word line and the bit line. The selection element S may not select a corresponding memory cell by blocking current based on voltages of the word line and the bit line. In an example embodiment, the selection element S may be replaced by a transistor. In example embodiments, instead of using the selection element S, a method of controlling voltages of the word line and the bit line may be used to select each memory cell. For example, by setting the word line and the bit line connected to the unselected memory cell with the same voltage, no current can flow to the unselected memory cell. By setting the word line and the bit line connected to the unselected memory cell with different voltages, current can flow to the unselected memory cell. In the case of using a method of adjusting a voltage instead of the selection element S, each memory cell may not include the selection element S.

The variable resistor element VR may be of a resistive type, a phase change type, a magnetic type or a ferroelectric type.

As described above, memory TILEs TILE1 through TILEz may share global bit line GBL. Each global bit line may be connected to a plurality of bit lines in each memory tile. Because of the resistive and capacitive loading of each global bit line, it can take a lot of time to drive each global bit line up to the target voltage. The driver circuit 13, 14, 15 or 16 according to example embodiments of the inventive concepts may be used to reduce the time taken to drive each global bit line up to a target voltage. As such, the driver circuits 13, 14, 15, or 16 according to example embodiments of the inventive concepts may be used to reduce the time taken to drive each global word line up to a target voltage.

Fig. 15 is a block diagram partially illustrating a row decoder circuit 213_1 and a sense amplifier and write driver circuit 215_1 to each of which a driver circuit is applied according to an example embodiment of the inventive concept.

Referring to fig. 15, the row decoder circuit 213_1 may include a global word line driver corresponding to the global word line GWL. The global word line driver may be configured to drive the global word lines using one or more of the driver circuits 13 to 16 described with reference to fig. 5 to 8.

The 8 sense amplifier and write driver circuit 215_1 may include a global bit line driver that drives a global bit line. The global bit line driver 215_1 may be configured to drive the global bit line GBL using one or more of the driver circuits 13 to 16 described with reference to fig. 5 to 8.

Fig. 16 is a block diagram illustrating a storage device 100 according to an example embodiment of the inventive concepts. Referring to fig. 16, the storage device 100 may include a nonvolatile memory device 110, a controller 120, and a Random Access Memory (RAM) 130.

The nonvolatile memory device 110 may perform a write, read, or erase operation under the control of the controller 120. The nonvolatile memory device 110 may receive commands and addresses from the controller 120 through input/output channels. The nonvolatile memory device 110 may exchange data with the controller 120 through an input/output channel.

The non-volatile memory device 110 may include flash memory. However, the scope and spirit of the inventive concept may not be limited thereto. For example, the nonvolatile memory device 110 may include at least one of nonvolatile memory devices such as a phase change RAM (PRAM), a Magnetic RAM (MRAM), a Resistive RAM (RRAM), and a ferroelectric RAM (FeRAM).

The controller 120 may be a memory controller configured to access the nonvolatile memory device 110. For example, the controller 120 may control the nonvolatile memory device 110 through an input/output channel and a control channel in order to perform a write, read, or erase operation.

The controller 120 may control the nonvolatile memory device 110 under the control of an external host device (not shown). For example, the controller 120 may communicate with an external host device based on a format different from the format used for communication of the nonvolatile memory device 110. The unit of data that the controller 120 transfers to the nonvolatile memory device 110 may be different from the unit of data that the controller 120 transfers to the external host device.

The controller 120 may use the RAM 130 as a working memory, a buffer memory, or a cache memory. The controller 120 may store data or code required to manage the nonvolatile memory device 110 in the RAM 130. For example, the controller 120 may read data or code required to manage the nonvolatile memory device 110 from the nonvolatile memory device 110, and may load the read data or code on the RAM 130 for driving.

RAM 130 may include at least one of various random access memories such as, but not limited to, static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SRAM), PRAM, MRAM, RRAM, and FRAM.

The storage device 100 may include a Solid State Drive (SSD) or a Hard Disk Drive (HDD). The storage device 100 may include memory cards such as PC cards (personal computer memory card international association (PCMCIA)), compact Flash (CF) cards, smart media cards (e.g., SM, SMC), memory sticks, multimedia cards (e.g., MMC, RS-MMC, mmcmmicro), SD cards (e.g., SD, mini SD, micro SD, SDHC), universal Serial Bus (USB) memory cards, and Universal Flash Storage (UFS). The storage device 100 may include an embedded memory, such as an embedded multimedia card (eMMC), UFS, and PPN (ideal page NAND).

In fig. 16, an example according to an example embodiment of the inventive concept is provided when the RAM 130 is disposed outside the controller 120. However, the scope and spirit of the inventive concept may not be limited thereto. For example, the storage device 100 may not include the RAM 130 disposed outside the controller 120. The controller 120 may use the internal RAM as a buffer memory, a working memory, or a cache memory.

As described with reference to fig. 1 to 15, when one or more of the driver circuits 13 to 16 described with reference to fig. 5 to 8 is applied to the nonvolatile memory device 110, the operation speed of the nonvolatile memory device 110 may be increased, and the complexity and area thereof may be reduced. This may mean that the operating speed of the non-volatile memory device 110 increases and its complexity and area decreases. In addition, the nonvolatile memory device 110 and the manufacturing cost of the memory device 110 can be reduced.

Fig. 17 is a block diagram illustrating a computing device 1000 according to an example embodiment of the inventive concepts. With reference to fig. 17, a computing device 1000 may include a processor 1100, RAM 1200, a storage device 1300, a modem 1400, and a user interface 1500.

The processor 1100 may control the overall operation of the computing device 1000 and may perform logical operations. The processor 1100 may be based on a data processing device that includes hardware physically configured to perform operations represented by commands included in code or programs. For example, the processor 1100 may be a system on a chip (SoC). The processor 1100 may be a general purpose processor, a special purpose processor, or an application processor.

RAM 1200 may be in communication with processor 1100. RAM 1200 may be the main memory of processor 1100 or computing device 1000. The processor 1100 may temporarily store code or data in the RAM 1200. The processor 1100 may execute code and may process data using the RAM 1200. The processor 1100 may use the RAM 1200 to execute various software such as an operating system and applications. The processor 1100 may use the RAM 1200 to control the overall operation of the computing device 1000. The RAM 1200 may include volatile memory such as SRAM, DRAM, SDRAM, etc., or nonvolatile memory such as PRAM, MRAM, RRAM, FRAM, etc.

The storage device 1300 may be in communication with the processor 1100. The storage device 1300 may be used to store data for a long time. That is, the processor 110 may store data to be stored for a long time in the storage device 1300. Storage device 1300 may store a boot image for driving computing device 1000. The storage device 1300 may store source code for various software such as an operating system and applications. The storage device 1300 may store data processed by various software, such as an operating system and applications.

In an example embodiment, the processor 1100 may load source code stored on the storage device 1300 onto the RAM 1200 and may execute the code, thereby driving various software such as an operating system, applications, and the like. The processor 1100 may load data stored on the storage device 1300 onto the RAM 1200 and may process the data loaded on the RAM 1200. The processor 1100 may store long-term data among the data stored in the RAM 1200 in the storage device 1300.

The storage device 1300 may include non-volatile memory such as, but not limited to, flash memory, PRAM, MRAM, RRAM, or FRAM.

Modem 1400 may communicate with external devices under control of processor 1100. For example, the modem 1400 may communicate with external devices in a wired or wireless manner. The modem 1400 may communicate with an external device based on at least one of a wireless communication manner such as Long Term Evolution (LTE), wiMax, global system for mobile communications (GSM), code Division Multiple Access (CDMA), bluetooth, near Field Communication (NFC), wi-Fi, radio Frequency Identification (RFID), etc.; wired communication means such as Universal Serial Bus (USB), SATA, HSIC, SCSI, firewire, peripheral Component Interconnect (PCI), PCI express (PCIe), nonvolatile high-speed memory (NVMe), universal flash memory (UFS), secure Digital (SD), SDIO, universal Asynchronous Receiver Transmitter (UART), serial Peripheral Interface (SPI), high-speed SPI (HS-SPI), RS232, built-in integrated circuit (I2C), HS-I2C, integrated chip built-in sound (I2S), sony/philips digital interface (S/PDIF), multimedia card (MMC), embedded MMC (eMMC), and the like.

The user interface 1500 may be in communication with a user under the control of the processor 1100. For example, the user interface 1500 may include a user input interface such as a keyboard, keypad, buttons, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscopic sensor, and vibration sensor. The user interface 150 may additionally include user output interfaces such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display device, an Active Matrix OLED (AMOLED) display device, a Light Emitting Diode (LED), a speaker, and a motor.

As described with reference to fig. 1 to 15, when one or more of the driver circuits 13 to 16 described with reference to fig. 5 to 8 is applied to the memory device 1300, the operation speed of the memory device 1300 may be increased and the complexity and area thereof may be reduced. This may mean that the operating speed of the computing device 1000 is increased and its complexity and area is reduced. In addition, the manufacturing costs of the memory device 1300 and the computing device 1000 may be reduced.

According to example embodiments of the inventive concepts, the driver circuit may be configured to drive the clamp transistor using an amplifier. Therefore, the driving capability of the driver circuit can be improved. Further, the driver circuit may be composed of a single-stage amplifier. Accordingly, the number of transistors constituting the driver circuit can be reduced, and thus the area of the driver circuit can be reduced.

Even though a hardware implementation (e.g., a specific circuit) of a driver circuit according to an example embodiment has been described with reference to fig. 3 and 5-8 of the present application, one of ordinary skill in the art will appreciate that the driver module can alternatively implement the features of the driver circuit described above. For example, the drive module may include a drive memory (e.g., a memory device) and a controller (e.g., a microprocessor) configured to execute computer readable code (e.g., software) stored in the drive memory, wherein the computer readable code transforms the controller into a dedicated controller configured to perform some or all of the operations described herein, as performed by one or more of the driver circuits in accordance with the example embodiments in fig. 3 and 5-8 of the present application.

It should be understood that the exemplary embodiments described herein should be considered in descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each device or method according to example embodiments should typically be considered as available for use with other similar features or aspects in other devices or methods according to example embodiments. Although a few example embodiments have been particularly shown and described, it will be understood by those of ordinary skill in the art that changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims (24)

1. A driver circuit, comprising:

a clamp transistor including a clamp gate, a first clamp node, and a second clamp node connected to the charging node;

a comparison voltage transistor including a comparison voltage gate configured to receive a reference voltage, a first comparison voltage node configured to receive a first voltage, and a second comparison voltage node configured to output a comparison voltage;

an amplifying transistor including an amplifying gate connected to the charging node, a first amplifying node connected to a second comparison voltage node of the comparison voltage transistor and configured to receive the comparison voltage, and a second amplifying node connected to a clamping gate of the clamping transistor;

a bias transistor including a bias gate configured to receive a bias voltage, a first bias node connected to a clamp gate of the clamp transistor, and a second bias node configured to receive a second voltage; and

a charging circuit that performs one of: configured to draw current from the charging node through the clamp transistor and configured to supply current to the charging node through the clamp transistor.

2. The driver circuit of claim 1, wherein

The clamp transistor and the amplifying transistor are PMOS transistors, and

the comparison voltage transistor and the bias transistor are NMOS transistors.

3. The driver circuit of claim 1, wherein

The first voltage is a power supply voltage, and

the second voltage is a ground voltage.

4. The driver circuit of claim 1, wherein

The clamp transistor and the amplifying transistor are NMOS transistors

The comparison voltage transistor and the bias transistor are PMOS type transistors.

5. The driver circuit of claim 1, wherein

The first voltage is the ground voltage

The second voltage is a supply voltage.

6. The driver circuit of claim 1, further comprising:

an enable transistor connected between the clamp gate of the clamp transistor and the second amplifying node of the amplifying transistor, an

The enable transistor is configured to receive an enable signal and to be activated or deactivated based on the enable signal.

7. The driver circuit of claim 1, further comprising:

and a voltage generator configured to supply a third voltage to the second clamping node of the clamping transistor.

8. The driver circuit of claim 1, wherein the amplifying transistor is configured to adjust the voltage of the clamp gate such that the voltage of the charging node reaches the target voltage.

9. The driver circuit of claim 8, wherein the reference voltage is based on a target voltage of the charging node, a threshold voltage of the comparison voltage transistor, and a threshold voltage of the amplifying transistor.

10. The driver circuit of claim 1, wherein the charging node is connected to one of a word line and a bit line connected to the memory cell.

11. A driver circuit, comprising:

a clamp switch including a gate configured to receive a clamp voltage, a first node, and a second node connected to a charging node;

a charging circuit connected to the first node of the clamp switch,

the charging circuit performs at least one of: configured to draw current from the charging node through the clamp switch and configured to supply current to the charging node through the clamp switch;

a comparison voltage generator configured to output a comparison voltage;

a single-stage amplifier is provided which comprises a first amplifier,

the single stage amplifier is configured to amplify a difference between the comparison voltage and the voltage of the charging node, an

The single-stage amplifier is configured to output a clamp voltage as an amplification result; and

a current bias circuit connected to the gate of the clamp switch,

the current bias circuit is configured to adjust an amount of current flowing to a ground node to which a ground voltage is supplied through the comparison voltage generator, the single stage amplifier, and the current bias circuit.

12. The driver circuit of claim 11, wherein the single stage amplifier comprises:

including a transistor connected to the gate of the charging node,

a first node connected to the comparison voltage generator

A second node connected to the gate of the clamp switch.

13. The driver circuit of claim 11, wherein the charging circuit comprises:

a first transistor connected between a first node of the clamp switch and a first voltage node to which a first voltage is supplied,

the first transistor is configured to be activated in response to a discharge enable signal;

a second transistor connected to the first voltage node,

the second transistor is configured to be activated in response to a charge enable signal; and

a current source connected between the second transistor and the first node of the clamp switch.

14. The driver circuit of claim 11, wherein the comparison voltage generator comprises:

a transistor including a gate configured to receive a reference voltage, a first comparison voltage node configured to receive a first voltage, and a second comparison voltage node configured to output a comparison voltage.

15. The driver circuit of claim 11, wherein the current bias circuit comprises:

A transistor having a gate configured to receive a bias voltage,

a first bias node configured to receive a first voltage, an

A second bias node connected to the gate of the clamp switch.

16. The driver circuit of claim 11, further comprising:

and a voltage generator configured to supply a set voltage to the charging node in response to the set enable signal.

17. The driver circuit of claim 11, further comprising:

a second clamp switch including a second gate configured to receive a second clamp voltage, a third node, and a fourth node connected to the charging node;

a second charging circuit connected to a third node of the second clamp switch,

the second charging circuit performs at least one of: configured to draw current from the charging node through the second clamp switch and configured to supply current to the charging node through the second clamp switch; a second comparison voltage generator configured to output a second comparison voltage;

a second one-stage amplifier is provided,

the second single stage amplifier is configured to amplify a difference between the second comparison voltage and the voltage of the charging node,

the second single-stage amplifier is configured to output a second clamp voltage as an amplification result; and

A second current bias circuit connected to the second gate of the second clamp switch,

the second current bias circuit is configured to adjust an amount of current flowing through the second comparison voltage generator, the second single stage amplifier, and the second current bias circuit to a second ground node to which the ground voltage is supplied.

18. The driver circuit of claim 17, wherein,

each of the clamp switch and the single stage amplifier includes a PMOS transistor

Each of the charging circuit and the current bias circuit includes an NMOS transistor.

19. The driver circuit of claim 17, wherein,

each of the second clamp switch and the second single stage amplifier includes an NMOS transistor

Each of the second charging circuit and the second current bias circuit includes a PMOS transistor.

20. A driver circuit configured to charge conductive lines connected to a plurality of memory cells of a nonvolatile memory, the driver circuit comprising:

a clamp switch including a gate configured to receive a clamp voltage, a first node, and a second node connected to a charging node of the conductive line;

a charging circuit connected to the first node of the clamp switch,

the charging circuit performs at least one of: configured to draw current from the charging node through the clamp switch and configured to supply current to the charging node through the clamp switch;

A comparison voltage generator configured to output a comparison voltage;

a single-stage amplifier is provided which comprises a first amplifier,

the single stage amplifier is configured to amplify a difference between the comparison voltage and the voltage of the charging node, an

The single-stage amplifier is configured to output a clamp voltage as an amplification result; and

a current bias circuit connected to the gate of the clamp switch,

the current bias circuit is configured to adjust an amount of current flowing to a ground node to which a ground voltage is supplied through the comparison voltage generator, the single stage amplifier, and the current bias circuit.

21. A driver circuit, comprising:

a clamp switch including a clamp gate configured to receive a clamp voltage, a first clamp node, and a second clamp node connected to a charging node;

a charging circuit comprising a charging circuit node connected to a first clamping node of the clamping switch,

the charging circuit node is connected to the set transistor and the discharge transistor; and

the charging control circuit comprises a comparison voltage generator, an amplifier, an enabling switch and a biasing circuit which are sequentially connected in series,

the comparison voltage generator includes a first comparison node connected to a first voltage node to which a first voltage is supplied, a comparison gate configured to receive a reference voltage, and a second comparison node configured to output a comparison voltage to the amplifier,

The amplifier includes a first amplifier node configured to receive the comparison voltage output from the comparison voltage generator, an amplifier gate connected to the charging node and a second amplifier node,

the enable switch includes an enable gate configured to receive an enable signal for activating or deactivating the enable switch, a first enable node connected to the second amplifier node and a second enable node connected to the bias circuit and the clamp gate,

the bias circuit including a first bias node connected to a gate of the clamp switch and a second bias node connected to a second voltage node supplied with a second voltage, the bias circuit being configured to adjust an amount of current flowing to the first voltage node through the comparison voltage generator, the amplifier and the bias circuit in response to the bias voltage,

wherein the first voltage is one of a power supply voltage and a ground voltage, and the second voltage is a different one of the power supply voltage and the ground voltage.

22. The driver circuit of claim 21, wherein

Each of the clamp switch and the amplifier includes a PMOS transistor

Each of the charging circuit and the bias circuit includes an NMOS transistor.

23. The driver circuit of claim 21, wherein

Each of the clamp switch and the amplifier includes an NMOS transistor

Each of the charging circuit and the bias circuit includes a PMOS transistor.

24. The driver circuit of claim 21, further comprising:

bit line connected to the charging node, wherein

The driver circuit is a precharge circuit of the memory device.

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