CN108566180A - A kind of single delay chain circuit generating two-way delay - Google Patents

Abstract

The invention discloses a single delay chain circuit for generating two-way delays, comprising: a main chain of the delay chain, a first buffer circuit, a second buffer circuit, a first selector and a second selector; wherein: the delay The odd output ends of the chain main chain are all connected with the input ends of the first buffer circuit, and the even output ends of the delay chain main chain are connected with the input ends of the second buffer circuit; the output ends of the first buffer circuit are connected with the first selector The input terminal of the second buffer circuit is connected to the input terminal of the second selector; the first selector gates the output signal of the first buffer circuit, and the second selector controls the output signal of the second buffer circuit gating; the outputs of the first selector and the second selector are the two outputs of the delay chain circuit. The circuit replaces the traditional circuit of two identical delay chains by extracting two delayed signals with opposite phases in one delay chain, so that the relative delay of the two delayed signals is more accurate.

Description

A single delay chain circuit generating two delays

technical field

The invention relates to the technical field of digital circuits, in particular to a single-delay chain circuit generating two-way delays.

Background technique

At present, delay chain circuits are widely used in large-scale digital circuits. In structures such as delay-locked loops and time-to-digital converters, a delay chain circuit with uniform delay is very important.

The existing delay chain circuit mostly adopts the structure of two or more chains. The uniformity of the delay chain delay of this structure will inevitably be affected by factors such as technology, which will affect the accuracy and stability of the entire delay chain circuit. . The uniformity of delay chain delay is a technical problem to be solved urgently.

Contents of the invention

The purpose of the present invention is to provide a single-delay chain circuit for generating two-way delays, which can make the relative delay of the two-way delay signals more accurate.

The purpose of the present invention is achieved through the following technical solutions:

A single delay chain circuit generating two-way delay, characterized in that it includes: a delay chain main chain, a first buffer circuit, a second buffer circuit, a first selector and a second selector; wherein:

The odd output ends of the main chain of the delay chain are all connected to the input end of the first buffer circuit, and the even output ends of the main chain of the delay chain are connected to the input end of the second buffer circuit;

The output end of the first buffer circuit is connected to the input end of the first selector, and the output end of the second buffer circuit is connected to the input end of the second selector;

The first selector gates the output signal of the first buffer circuit, and the second selector gates the output signal of the second buffer circuit; The output of the second selector is the two outputs of the delay chain circuit.

As can be seen from the technical scheme provided by the present invention above, by extracting two-way phase-opposite time-delay signals on a time-delay chain, replacing traditional circuits of two identical time-delay chains, the problem of the time delay of the time-delay chain is solved The problem of uniformity, so that the relative delay of the two delayed signals is more accurate.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings on the premise of not paying creative work.

Fig. 1 is the schematic diagram of a kind of single delay chain circuit that produces two-way delay provided by the embodiment of the present invention;

FIG. 2 is a schematic diagram of an example of a single delay chain circuit generating two delays provided by an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The embodiment of the present invention provides a single delay chain circuit that generates two-way delay, as shown in Figure 1, it mainly includes: delay chain main chain, first buffer circuit, second buffer circuit, first selector and Second selector; where:

The odd output ends of the main chain of the delay chain are all connected to the input ends of the first buffer circuit, and the even output ends of the main chain of the delay chain are connected to the input ends of the second buffer circuit; The output terminal of the first buffer circuit is connected to the input terminal of the first selector, and the output terminal of the second buffer circuit is connected to the input terminal of the second selector; the first selector is connected to the input terminal of the second selector; The output signal of a buffer circuit is gated, and the second selector is gated on the output signal of the second buffer circuit; the output of the first selector and the second selector is a delay chain two outputs of the circuit.

In the embodiment of the present invention, the main chain of the delay chain includes a plurality of end-to-end delay units; the first delay unit is the input of the main chain of the delay chain; the output end of each delay unit is connected to the next The input terminal connection of a delay unit;

Exemplarily, the number of delay units in the main chain of the delay chain can be 2n+1, then the 2n+1th delay unit can be set as a redundant delay unit to ensure that the load of the 2nth delay unit is the same as The first 2n-1 delay units are the same, and the delay of each delay unit is guaranteed to be the same.

In the embodiment of the present invention, the first buffer circuit includes n first buffer units; the input end of each first buffer unit is independently connected to the output of the corresponding odd-numbered delay unit in the main chain of the delay chain end connection.

In the embodiment of the present invention, the second buffer circuit includes n second buffer units; the input end of each second buffer unit is independently connected to the output of the corresponding even-numbered delay unit in the main chain of the delay chain end connection.

In the embodiment of the present invention, the structure and quantity of the first buffer unit in the first buffer circuit and the second buffer unit in the second buffer circuit are the same.

In the embodiment of the present invention, when the first enable signal EN1 is 1, the first buffer circuit works, and the delay signal is input to the first selector; when the first enable signal EN1 is 0, the first buffer circuit does not work , input 0 into the first selector; the first selector is controlled by the control signal of the first selector to gate the output of the first buffer circuit, and the output of the first selector is the output DOUT1 of the delay chain; when the second When the enable signal EN2 is 1, the second buffer circuit works, and the delayed signal is input to the second selector; when the second enable signal EN2 is 0, the second buffer circuit does not work, and 0 is input to the second selector; The second selector is controlled by the control signal of the second selector to gate the output of the second buffer circuit, and the output of the second selector is the output DOUT2 of the delay chain.

Preferably, the delay unit includes an inverter, the first buffer unit includes an AND gate, and the second buffer unit includes an AND gate, and a related delay chain circuit is shown in FIG. 2 .

Referring to Figure 2, the input signal DIN is input from the input end of the first delay unit of the delay chain main chain, and the delay signal with uniformly increased delay is sequentially generated at the output end of each delay unit, and the step size of the delay increase is the delay time of one delay unit. The output terminals of the odd number of delay units produce inverted delayed signals, and the output terminals of even number of delay units produce non-inverted delayed signals. When the first enable signal EN1 is 1, the first buffer circuit works, and the delay signal is input to the first selector; when the first enable signal EN1 is 0, the first buffer circuit does not work, and 0 is input to the first selector. Selector; the first selector is controlled by the control signal S1 of the first selector to gate the output of the first buffer circuit, and the output of the first selector is the output DOUT1 of the delay chain; DOUT1 is an inverted delay signal .

When the second enable signal EN2 is 1, the second buffer circuit works, and the delay signal is input to the second selector; when the second enable signal EN2 is 0, the second buffer circuit does not work, and 0 is input to the second selector. A selector: the second selector is controlled by the control signal S2 of the second selector to gate the output of the second buffer circuit, the output of the second selector is the output DOUT2 of the delay chain, and DOUT2 is an in-phase delay signal.

The above-mentioned delay chain circuit provided by the embodiment of the present invention replaces the traditional circuits of two identical delay chains by extracting two delay signals with opposite phases on a delay chain, so as to solve the delay problem of the delay chain The problem of uniformity, so that the relative delay of the two delayed signals is more accurate.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person familiar with the technical field can easily conceive of changes or changes within the technical scope disclosed in the present invention. Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1. A single delay chain circuit producing two-way delay is characterized in that it comprises: delay chain main chain, the first buffer circuit, the second buffer circuit, the first selector and the second selector; wherein: The odd output ends of the main chain of the delay chain are all connected to the input end of the first buffer circuit, and the even output ends of the main chain of the delay chain are connected to the input end of the second buffer circuit; The output end of the first buffer circuit is connected to the input end of the first selector, and the output end of the second buffer circuit is connected to the input end of the second selector; The first selector gates the output signal of the first buffer circuit, and the second selector gates the output signal of the second buffer circuit; The output of the second selector is the two outputs of the delay chain circuit. 2. a kind of single delay chain circuit that produces two-way time-delay according to claim 1, is characterized in that, described time-delay chain main chain comprises the time-delay unit of a plurality of end-to-end connections; The first time-delay unit It is the input of the main chain of the delay chain; the output end of each delay unit is connected with the input end of the next delay unit. 3. a kind of single delay chain circuit that produces two-way time-delay according to claim 2, is characterized in that, the number of delay unit in the main chain of described delay chain is 2n+1, then the 2n+th One delay unit is a redundant delay unit, which is used to ensure that the load of the 2nth delay unit is the same as that of the previous 2n-1 delay units, and that the delay of each delay unit is the same. 4. A single delay chain circuit generating two delays according to claim 2 or 3, wherein the delay unit comprises an inverter. 5. A kind of single delay chain circuit that produces two-way time-delay according to claim 1 or 2 or 3, is characterized in that, described first buffer circuit comprises n first buffer units; The input terminals of the units are individually connected to the output terminals of the corresponding odd-numbered delay units in the main chain of the delay chain. 6 . A single delay chain circuit generating two delays according to claim 5 , wherein the first buffer unit comprises an AND gate. 7 . 7. A kind of single delay chain circuit that produces two-way delay according to claim 1 or 2 or 3, is characterized in that, described second buffer circuit comprises n second buffer units; The input ends of the units are individually connected to the output ends of the corresponding even-numbered delay units in the main chain of the delay chain. 8. A single delay chain circuit generating two delays according to claim 7, wherein the second buffer unit comprises an AND gate. 9. A kind of single delay chain circuit that produces two-way delay according to claim 1, is characterized in that, the first buffer unit in the first buffer circuit, and the second buffer unit in the second buffer circuit The structure and quantity are the same. 10. a kind of single delay chain circuit that produces two-way delay according to claim 1, is characterized in that, When the first enable signal EN1 is 1, the first buffer circuit works, and the delay signal is input to the first selector; when the first enable signal EN1 is 0, the first buffer circuit does not work, and 0 is input to the first selector. A selector; the first selector is controlled by the control signal of the first selector to gate the output of the first buffer circuit, which is the output DOUT1 of the delay chain; When the second enable signal EN2 is 1, the second buffer circuit works, and the delay signal is input to the second selector; when the second enable signal EN2 is 0, the second buffer circuit does not work, and 0 is input to the second selector. A selector: the second selector is controlled by the control signal of the second selector to gate the output of the second buffer circuit, which is the output DOUT2 of the delay chain.