[go: up one dir, main page]

CN107516673A - GaN semiconductor device and its preparation method and application - Google Patents

GaN semiconductor device and its preparation method and application Download PDF

Info

Publication number
CN107516673A
CN107516673A CN201710702142.6A CN201710702142A CN107516673A CN 107516673 A CN107516673 A CN 107516673A CN 201710702142 A CN201710702142 A CN 201710702142A CN 107516673 A CN107516673 A CN 107516673A
Authority
CN
China
Prior art keywords
gallium nitride
layer
nitride layer
aluminum
gan semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710702142.6A
Other languages
Chinese (zh)
Inventor
金荣善
金峻渊
李尚俊
骆薇薇
孙在亨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Innovo Secco (zhuhai) Technology Co Ltd
Original Assignee
Innovo Secco (zhuhai) Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innovo Secco (zhuhai) Technology Co Ltd filed Critical Innovo Secco (zhuhai) Technology Co Ltd
Priority to CN201710702142.6A priority Critical patent/CN107516673A/en
Publication of CN107516673A publication Critical patent/CN107516673A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/015Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

本发明公开了一种GaN半导体器件,包括:基板;设置于所述基板上的晶种层;设置于所述晶种层上的缓冲层;设置于所述缓冲层上的所述氮化镓层;设置于所述氮化镓层上的AlxGaN1‑xN层;所述AlxGaN1‑xN层包括依次层叠于所述氮化镓层上的第一氮化镓铝层、氮化铝层以及第二氮化镓铝层。上述GaN半导体器件的结构,生长二维电子气(2DEG)用氮化铝镓薄膜时,有效利用作为插入薄膜结构的氮化铝镓/氮化铝/氮化铝镓复合膜;能有效控制在后续为栅极接触而进行的蚀刻工艺中剩下的氮化铝镓的厚度,改善晶体管(MISFET Transistor)特性中散布问题。

The invention discloses a GaN semiconductor device, comprising: a substrate; a seed layer arranged on the substrate; a buffer layer arranged on the seed layer; and the gallium nitride arranged on the buffer layer layer; an AlxGaN1-xN layer disposed on the gallium nitride layer; the AlxGaN1-xN layer includes a first aluminum gallium nitride layer, an aluminum nitride layer and a second layer stacked on the gallium nitride layer in sequence AlGaN layer. The structure of the above-mentioned GaN semiconductor device, when growing a two-dimensional electron gas (2DEG) aluminum gallium nitride thin film, effectively utilizes the aluminum gallium nitride/aluminum nitride/aluminum gallium nitride composite film as an inserted thin film structure; it can be effectively controlled at The remaining thickness of AlGaN in the subsequent etching process for the gate contact improves the dispersion problem in the characteristics of the transistor (MISFET Transistor).

Description

GaN半导体器件及其制备方法和应用GaN semiconductor device and its preparation method and application

技术领域technical field

本发明涉及半导体技术领域,特别是涉及一种GaN半导体器件及其制备方法和应用。The invention relates to the technical field of semiconductors, in particular to a GaN semiconductor device and its preparation method and application.

背景技术Background technique

电力半导体市场占有整个半导体市场的10%的庞大市场,但之前的电力半导体市场以利用硅的功率器件为主。在过去20年,每隔10年间,硅功率器件提高5~6倍的电力密度,很难期待性能上更进一步的提高。The power semiconductor market occupies a huge market of 10% of the entire semiconductor market, but the previous power semiconductor market was dominated by power devices using silicon. In the past 20 years, every 10 years, the power density of silicon power devices has increased by 5 to 6 times, and it is difficult to expect further improvements in performance.

与硅和砷化镓相比,氮化镓具有带隙宽(Eg=3.4eV),在高温下稳定(700℃)等特征。相比硅电力半导体,氮化镓电力半导体具有低温抵抗特性,不仅可以减少随着电力半导体而引起的-电闸的损失,还也可以做到系统消费电力最少化等优点。依靠氮化镓半导体器件小型化,高电压,高速电闸,可以实现低损失,高效率的下一代电力器件,可以满足产业用,电力网,信息通信部门的需求。Compared with silicon and gallium arsenide, gallium nitride has the characteristics of wide band gap (Eg=3.4eV) and stability at high temperature (700°C). Compared with silicon power semiconductors, gallium nitride power semiconductors have low-temperature resistance characteristics, which can not only reduce the loss of gates caused by power semiconductors, but also minimize system power consumption. Relying on the miniaturization of GaN semiconductor devices, high voltage, and high-speed gates, low-loss, high-efficiency next-generation power devices can be realized, which can meet the needs of industries, power grids, and information and communication departments.

但是,因为氮化镓电力半导体有着常关问题,期间不能单独使用氮化镓电力半导体,要与硅功率器件一同使用。如此,使用与常开动作有着同样功能的正极结构。However, because gallium nitride power semiconductors have a constant shutdown problem, gallium nitride power semiconductors cannot be used alone during the period, and must be used together with silicon power devices. In this way, use a positive electrode structure that has the same function as the normally open operation.

常开氮化镓半导体正在开发中,其中氮化镓磊晶层结构包含的氮化镓高电子迁移率晶体管的活用度也逐步提高。Normally-on gallium nitride semiconductors are under development, and the activity of gallium nitride high electron mobility transistors contained in the gallium nitride epitaxial layer structure is also gradually increasing.

为体现利用氮化镓电力器件中的崩溃电压,并且为生长出高品质的氮化镓层;在硅基板上生长出,如,氮化铝等籽晶层后,改善缓冲层的品质起着重要作用。即,活用以硅为基板的氮化铝籽晶层/氮化铝镓缓冲层上形成的未掺杂氮化镓磊晶层/氮化铝镓的二维电子气(2DEG)结构的品质及管理很重要。In order to reflect the breakdown voltage in GaN power devices and to grow high-quality GaN layers; after growing seed layers such as aluminum nitride on silicon substrates, improving the quality of the buffer layer plays an important role. important role. That is, the quality and Management is important.

发明内容Contents of the invention

基于此,本发明的目的是提供一种GaN半导体器件的结构。Based on this, the object of the present invention is to provide a structure of a GaN semiconductor device.

具体的技术方案如下:The specific technical scheme is as follows:

一种GaN半导体器件,包括:A GaN semiconductor device, comprising:

基板;Substrate;

设置于所述基板上的晶种层;a seed layer disposed on the substrate;

设置于所述晶种层上的缓冲层;a buffer layer disposed on the seed layer;

设置于所述缓冲层上的所述氮化镓层;the gallium nitride layer disposed on the buffer layer;

设置于所述氮化镓层上的AlxGaN1-xN层;an AlxGaN1-xN layer disposed on the gallium nitride layer;

所述AlxGaN1-xN层包括依次层叠于所述氮化镓层上的第一氮化镓铝层、氮化铝层以及第二氮化镓铝层。The AlxGaN1-xN layer includes a first aluminum gallium nitride layer, an aluminum nitride layer and a second aluminum gallium nitride layer stacked on the gallium nitride layer in sequence.

在其中一些实施例中,所述第二氮化镓铝层中的铝含量小于等于所述第一氮化镓铝层中的铝含量。In some embodiments, the aluminum content in the second AlGaN layer is less than or equal to the aluminum content in the first AlGaN layer.

在其中一些实施例中,其中0<x<1。In some of these embodiments, where 0<x<1.

在其中一些实施例中,所述AlxGa1-xN层的厚度为3nm~50nm。In some of the embodiments, the thickness of the AlxGa1-xN layer is 3nm-50nm.

在其中一些实施例中,所述晶种层的材质为氮化铝、氮化镓或氮化铝镓。In some of these embodiments, the material of the seed layer is aluminum nitride, gallium nitride or aluminum gallium nitride.

在其中一些实施例中,所述缓冲层的材质为氮化铝、氮化镓或氮化铝镓。In some of the embodiments, the material of the buffer layer is aluminum nitride, gallium nitride or aluminum gallium nitride.

在其中一些实施例中,所述氮化镓层为碳沉积氮化镓层、非掺杂氮化镓层或复合层,所述复合层为多层交互层叠的碳沉积氮化镓层和非掺杂氮化镓层。In some of these embodiments, the gallium nitride layer is a carbon-deposited gallium nitride layer, a non-doped gallium nitride layer or a composite layer, and the composite layer is a multi-layered carbon-deposited gallium nitride layer and a non-doped gallium nitride layer. Doped gallium nitride layer.

在其中一些实施例中,所述晶种层的厚度为100nm~200nm;所述缓冲层的厚度为0.5um~10um;所述氮化镓层的厚度为0.1um~1um。In some of the embodiments, the thickness of the seed crystal layer is 100nm-200nm; the thickness of the buffer layer is 0.5um-10um; the thickness of the gallium nitride layer is 0.1um-1um.

本发明的另一目的是提供上述GaN半导体器件的制备方法。Another object of the present invention is to provide a method for fabricating the above-mentioned GaN semiconductor device.

上述GaN半导体器件的制备方法,包括如下步骤:The preparation method of the above-mentioned GaN semiconductor device includes the following steps:

获取基板;Get the substrate;

在所述基板上形成晶种层;forming a seed layer on the substrate;

在所述晶种层上形成缓冲层;forming a buffer layer on the seed layer;

在所述缓冲层上形成氮化镓层;forming a gallium nitride layer on the buffer layer;

在所述氮化镓层上形成AlxGaN1-xN层;forming an AlxGaN1-xN layer on the gallium nitride layer;

所述AlxGaN1-xN层包括依次层叠于所述氮化镓层上的第一氮化镓铝层、氮化铝层以及第二氮化镓铝层。The AlxGaN1-xN layer includes a first aluminum gallium nitride layer, an aluminum nitride layer and a second aluminum gallium nitride layer stacked on the gallium nitride layer in sequence.

本发明的另一目的是提供一种半导体装置,包括上述GaN半导体器件。Another object of the present invention is to provide a semiconductor device including the above-mentioned GaN semiconductor device.

为体现利用氮化镓电力器件中的崩溃电压,并且为生长出高品质的氮化镓层。为形成二维电子气(2DEG)结构,使用非掺杂氮化镓/氮化铝镓(u-GaN/AlGaN layer);为形成晶体管(MISFET Transistor)结构,在后续工艺中,尤其在为栅极接触的蚀刻工艺中,氮化铝镓的蚀刻程度会引发蚀刻后氮化铝镓的厚度差异。由此,导致晶体管(MISFETTransistor)散布不良的问题。In order to reflect the breakdown voltage in GaN power devices and to grow high-quality GaN layers. In order to form a two-dimensional electron gas (2DEG) structure, use undoped gallium nitride/aluminum gallium nitride (u-GaN/AlGaN layer); in order to form a transistor (MISFET Transistor) structure, in the subsequent process, especially for the gate In the etching process of electrode contacts, the etching degree of AlGaN will cause the thickness difference of AlGaN after etching. This causes a problem of poor distribution of transistors (MISFET Transistors).

上述GaN半导体器件的结构,生长二维电子气(2DEG)用氮化铝镓薄膜时,氮化铝薄膜结构,即,第一氮化铝镓/氮化铝/第二氮化铝镓的复合膜。在后续栅极接触蚀刻工艺中,由于氮化铝镓薄膜结合氮化铝薄膜蚀刻量差,去除第二个氮化铝镓时,使氮化铝薄膜起到蚀刻终止功能,可一定程度上控制第一个氮化铝镓层的厚度,改善MISFET晶体管特性的散布。The structure of the above-mentioned GaN semiconductor device, when growing a two-dimensional electron gas (2DEG) aluminum gallium nitride thin film, the aluminum nitride thin film structure, that is, the composite of the first aluminum gallium nitride/aluminum nitride/second aluminum gallium nitride membrane. In the subsequent gate contact etching process, due to the poor etching amount of the aluminum gallium nitride film combined with the aluminum nitride film, when the second aluminum gallium nitride film is removed, the aluminum nitride film can perform the etching termination function, which can be controlled to a certain extent. The thickness of the first AlGaN layer improves the spread of MISFET transistor characteristics.

附图说明Description of drawings

图1为现有的GaN半导体器件的结构;Fig. 1 is the structure of existing GaN semiconductor device;

图2为现有的GaN半导体器件中氮化铝镓层全部蚀刻的情况;Fig. 2 is the situation that the aluminum gallium nitride layer is all etched in the existing GaN semiconductor device;

图3为现有的GaN半导体器件中氮化铝镓层部分蚀刻的情况;Fig. 3 is the situation that the AlGaN layer is partially etched in the existing GaN semiconductor device;

图4为一实施例GaN半导体器件的结构示意图(101、基板;102、晶种层;103、缓冲层;104、氮化镓层;105、第一氮化镓铝层;106、氮化铝层;107、第二氮化镓铝层);4 is a schematic structural view of a GaN semiconductor device according to an embodiment (101, substrate; 102, seed layer; 103, buffer layer; 104, gallium nitride layer; 105, first aluminum gallium nitride layer; 106, aluminum nitride layer; 107, the second aluminum gallium nitride layer);

图5为一实施例GaN半导体器件的结构蚀刻后的情况;Fig. 5 is the situation after the structure etching of GaN semiconductor device of an embodiment;

图6为GaN,AlGaN,AlN的蚀刻速率曲线。Figure 6 shows the etch rate curves of GaN, AlGaN, and AlN.

具体实施方式detailed description

为了便于理解本发明,下面将对本发明进行更全面的描述。但是,本发明可以以许多不同的形式来实现,并不限于本文所描述的实施例。相反地,提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。In order to facilitate the understanding of the present invention, the following will describe the present invention more fully. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present invention more thorough and comprehensive.

除非另有定义,本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的,不是旨在于限制本发明。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

一种GaN半导体器件,包括:A GaN semiconductor device, comprising:

基板101;Substrate 101;

设置于所述基板上的晶种层102;a seed layer 102 disposed on the substrate;

可以理解的,所述晶种层102的材质可为氮化铝、氮化镓或氮化铝镓;It can be understood that the material of the seed layer 102 can be aluminum nitride, gallium nitride or aluminum gallium nitride;

设置于所述晶种层102上的缓冲层103;a buffer layer 103 disposed on the seed layer 102;

可以理解的,所述缓冲层103的材质可为氮化铝、氮化镓或氮化铝镓;It can be understood that the material of the buffer layer 103 can be aluminum nitride, gallium nitride or aluminum gallium nitride;

设置于所述缓冲层103上的所述氮化镓层104;the gallium nitride layer 104 disposed on the buffer layer 103;

可以理解的,所述氮化镓层104为碳沉积氮化镓层、非掺杂氮化镓层或复合层,所述复合层为多层交互层叠的碳沉积氮化镓层和非掺杂氮化镓层;It can be understood that the gallium nitride layer 104 is a carbon-deposited gallium nitride layer, a non-doped gallium nitride layer or a composite layer, and the composite layer is a multi-layered carbon-deposited gallium nitride layer and a non-doped gallium nitride layer. gallium nitride layer;

设置于所述氮化镓层上的AlxGaN1-xN层;其中0<x<1;an AlxGaN1-xN layer disposed on the gallium nitride layer; wherein 0<x<1;

所述AlxGaN1-xN层包括依次层叠于所述氮化镓层上的第一氮化镓铝层105、氮化铝层106以及第二氮化镓铝层107(如图4所示)。The AlxGaN1-xN layer includes a first aluminum gallium nitride layer 105 , an aluminum nitride layer 106 and a second aluminum gallium nitride layer 107 sequentially stacked on the gallium nitride layer (as shown in FIG. 4 ).

与氮化镓接触的第一氮化铝镓层是为形成2DEG,与源极/漏极接触的第二氮化铝镓层是为改善源极对氮化铝镓、漏极对氮化铝镓的接触能力。The first AlGaN layer in contact with GaN is to form the 2DEG, and the second AlGaN layer in contact with the source/drain is to improve the source to AlGaN, drain to AlN Gallium contact capability.

所述第二氮化镓铝层中的铝含量小于等于所述第一氮化镓铝层中的铝含量。The aluminum content in the second aluminum gallium nitride layer is less than or equal to the aluminum content in the first aluminum gallium nitride layer.

上述GaN半导体器件的制备方法,包括如下步骤:The preparation method of the above-mentioned GaN semiconductor device includes the following steps:

获取基板;Get the substrate;

在所述基板上形成晶种层(seed layer);所述晶种层的材质可选自氮化铝AlN、氮化镓GaN或氮化铝镓AlGaN;forming a seed layer on the substrate; the material of the seed layer can be selected from aluminum nitride AlN, gallium nitride GaN or aluminum gallium nitride AlGaN;

工艺参数控制在:温度在1000~1150℃,厚度在100nm~200nm。Process parameters are controlled at: temperature at 1000-1150°C, thickness at 100nm-200nm.

在所述氮化铝晶种层上形成缓冲层(buffer layer);所述缓冲层的材质可选自AlN、氮化镓GaN或氮化铝镓AlGaN,也可以由氮化镓单一膜或氮化铝镓/氮化镓超晶格组成。工艺参数控制在温度1000~1150℃,厚度0.5um~10um下形成。A buffer layer (buffer layer) is formed on the aluminum nitride seed layer; the material of the buffer layer can be selected from AlN, gallium nitride GaN or aluminum gallium nitride AlGaN, or a single film of gallium nitride or nitrogen AlGaN/GaN superlattice composition. Process parameters are controlled at a temperature of 1000-1150°C and a thickness of 0.5um-10um.

在所述缓冲层上形成氮化镓层(GaN layer);工艺参数控制在温度1000~1150℃,厚度0.1um~1um下形成。A gallium nitride layer (GaN layer) is formed on the buffer layer; the process parameters are controlled at a temperature of 1000-1150°C and a thickness of 0.1um-1um.

在所述氮化镓层上形成AlxGaN1-xN层;工艺参数控制在温度1000~1150℃,厚度3nm~50nm下形成,Al含量为0<x<1。An AlxGaN1-xN layer is formed on the gallium nitride layer; the process parameters are controlled at a temperature of 1000-1150°C and a thickness of 3nm-50nm, and the Al content is 0<x<1.

所述AlxGaN1-xN层包括依次层叠于所述氮化镓层上的第一氮化镓铝层、氮化铝层以及第二氮化镓铝层,其中所述第二氮化镓铝层中的铝含量小于等于所述第一氮化镓铝层中的铝含量。The AlxGaN1-xN layer includes a first aluminum gallium nitride layer, an aluminum nitride layer and a second aluminum gallium nitride layer stacked on the gallium nitride layer in sequence, wherein the second aluminum gallium nitride layer The aluminum content is less than or equal to the aluminum content in the first aluminum gallium nitride layer.

上述GaN半导体器件的结构,生长二维电子气(2DEG)用氮化铝镓薄膜时,有效利用作为插入薄膜结构的氮化铝镓/氮化铝/氮化铝镓复合膜;能有效控制在后续为栅极接触而进行的蚀刻工艺中剩下的氮化铝镓的厚度(如图5、图6所示),改善晶体管(MISFETTransistor)特性中散布问题。The structure of the above-mentioned GaN semiconductor device, when growing a two-dimensional electron gas (2DEG) aluminum gallium nitride thin film, effectively utilizes the aluminum gallium nitride/aluminum nitride/aluminum gallium nitride composite film as an inserted thin film structure; it can be effectively controlled at The remaining AlGaN thickness (as shown in FIG. 5 and FIG. 6 ) in the subsequent etching process for the gate contact improves the dispersion problem in the characteristics of the transistor (MISFET Transistor).

以上所述实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例中的各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

以上所述实施例仅表达了本发明的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

  1. A kind of 1. GaN semiconductor devices, it is characterised in that including:
    Substrate;
    The crystal seed layer being arranged on the substrate;
    The cushion being arranged on the crystal seed layer;
    The gallium nitride layer being arranged on the cushion;
    The AlxGaN1-xN layers being arranged on the gallium nitride layer;
    The AlxGa1-xN layers include stack gradually in the first aluminum gallium nitride layer on the gallium nitride layer, aln layer and Second aluminum gallium nitride layer.
  2. 2. GaN semiconductor devices according to claim 1, it is characterised in that the aluminium in second aluminum gallium nitride layer contains The aluminium content that amount is less than or equal in first aluminum gallium nitride layer.
  3. 3. GaN semiconductor devices according to claim 1 or 2, it is characterised in that wherein 0<x<1.
  4. 4. GaN semiconductor devices according to claim 1 or 2, it is characterised in that the thickness of the AlxGa1-xN layers is 3nm~50nm.
  5. 5. GaN semiconductor devices according to claim 1 or 2, it is characterised in that the material of the crystal seed layer is nitridation Aluminium, gallium nitride or aluminium gallium nitride alloy.
  6. 6. GaN semiconductor devices according to claim 1 or 2, it is characterised in that the material of the cushion is nitridation Aluminium, gallium nitride or aluminium gallium nitride alloy.
  7. 7. GaN semiconductor devices according to claim 1 or 2, it is characterised in that the gallium nitride layer nitrogenizes for Carbon deposition Gallium layer, undoped gallium nitride layer or composite bed, the composite bed are the Carbon deposition gallium nitride layer of multilayer interaction cascading and undoped Gallium nitride layer.
  8. 8. GaN semiconductor devices according to claim 1 or 2, it is characterised in that the thickness of the crystal seed layer is 100nm ~200nm;The thickness of the cushion is 0.5um~10um;The thickness of the gallium nitride layer is 0.1um~1um.
  9. 9. the preparation method of the GaN semiconductor devices described in claim any one of 1-8, it is characterised in that comprise the following steps:
    Obtain substrate;
    Crystal seed layer is formed on the substrate;
    Cushion is formed on the crystal seed layer;
    Gallium nitride layer is formed on the cushion;
    AlxGaN1-xN layers are formed on the gallium nitride layer;
    The AlxGaN1-xN layers include stack gradually in the first aluminum gallium nitride layer on the gallium nitride layer, aln layer and Second aluminum gallium nitride layer.
  10. 10. a kind of semiconductor device, it is characterised in that including the GaN semiconductor devices described in claim any one of 1-8.
CN201710702142.6A 2017-08-16 2017-08-16 GaN semiconductor device and its preparation method and application Pending CN107516673A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710702142.6A CN107516673A (en) 2017-08-16 2017-08-16 GaN semiconductor device and its preparation method and application

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710702142.6A CN107516673A (en) 2017-08-16 2017-08-16 GaN semiconductor device and its preparation method and application

Publications (1)

Publication Number Publication Date
CN107516673A true CN107516673A (en) 2017-12-26

Family

ID=60721899

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710702142.6A Pending CN107516673A (en) 2017-08-16 2017-08-16 GaN semiconductor device and its preparation method and application

Country Status (1)

Country Link
CN (1) CN107516673A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112310210A (en) * 2019-08-02 2021-02-02 联华电子股份有限公司 High electron mobility transistor

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101002332A (en) * 2004-06-24 2007-07-18 日本电气株式会社 Semiconductor device
CN101009325A (en) * 2006-01-27 2007-08-01 松下电器产业株式会社 Transistor
JP2008244324A (en) * 2007-03-28 2008-10-09 Furukawa Electric Co Ltd:The Etching method of nitride compound semiconductor layer, and semiconductor device manufactured using the method
US20100270559A1 (en) * 2007-11-19 2010-10-28 Nec Corporation Field effect transistor and process for manufacturing same
US20120280244A1 (en) * 2011-05-06 2012-11-08 Samsung Electronics Co., Ltd. High Electron Mobility Transistors And Methods Of Manufacturing The Same
US20130112986A1 (en) * 2011-11-09 2013-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Gallium Nitride Semiconductor Devices and Method Making Thereof
CN207503986U (en) * 2017-08-16 2018-06-15 英诺赛科(珠海)科技有限公司 GaN semiconductor devices

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101002332A (en) * 2004-06-24 2007-07-18 日本电气株式会社 Semiconductor device
CN101009325A (en) * 2006-01-27 2007-08-01 松下电器产业株式会社 Transistor
JP2008244324A (en) * 2007-03-28 2008-10-09 Furukawa Electric Co Ltd:The Etching method of nitride compound semiconductor layer, and semiconductor device manufactured using the method
US20100270559A1 (en) * 2007-11-19 2010-10-28 Nec Corporation Field effect transistor and process for manufacturing same
US20120280244A1 (en) * 2011-05-06 2012-11-08 Samsung Electronics Co., Ltd. High Electron Mobility Transistors And Methods Of Manufacturing The Same
US20130112986A1 (en) * 2011-11-09 2013-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Gallium Nitride Semiconductor Devices and Method Making Thereof
CN207503986U (en) * 2017-08-16 2018-06-15 英诺赛科(珠海)科技有限公司 GaN semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112310210A (en) * 2019-08-02 2021-02-02 联华电子股份有限公司 High electron mobility transistor

Similar Documents

Publication Publication Date Title
US10096683B2 (en) Group III-N transistor on nanoscale template structures
US8895993B2 (en) Low gate-leakage structure and method for gallium nitride enhancement mode transistor
JP5224311B2 (en) Semiconductor electronic device
JP5634681B2 (en) Semiconductor element
JP5503487B2 (en) III-V semiconductor device having strain buffering interlayer
CN102683394B (en) Enhanced device and manufacturing method thereof
US8754419B2 (en) Semiconductor device
CN113314590B (en) Nitride high electron mobility transistor and manufacturing method thereof
US11955542B2 (en) Semiconductor device
US9679762B2 (en) Access conductivity enhanced high electron mobility transistor
CN105609552A (en) High electron mobility transistor and fabrication method thereof
CN111584628B (en) Enhanced GaN HEMT device and preparation method thereof
CN116387246A (en) p-GaN enhanced MIS-HEMT device and preparation method thereof
CN107331699A (en) GaN semiconductor devices and its preparation method and application
CN109962100B (en) P-channel GaN-based structure and electronic device
CN107516673A (en) GaN semiconductor device and its preparation method and application
CN207503986U (en) GaN semiconductor devices
TWI546958B (en) Gold and oxygen semi - high electron mobility transistor
CN117497414A (en) Preparation method of gallium oxide field effect transistor with high electron mobility and transistor
CN103681831B (en) High electron mobility transistor and method for manufacturing the same
JP6707837B2 (en) Semiconductor crystal substrate, semiconductor device, method of manufacturing semiconductor crystal substrate, and method of manufacturing semiconductor device
US11222968B2 (en) HEMT device structure and manufacturing method thereof
TW201911570A (en) Group III nitride semiconductor structure
CN116072722A (en) Enhanced semiconductor structure and manufacturing method thereof
CN207381406U (en) GaN semiconductor devices

Legal Events

Date Code Title Description
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20171226

RJ01 Rejection of invention patent application after publication