CN107345997B - A Test Method for IP Core Based on Test Shell - Google Patents

Abstract

The present application provides an IP core testing method based on a test shell, extracting a scan chain scan input SI and a primary input PI from an IP core test pattern, and loading the SI test data into the IP core through the test shell input port loading according to a test instruction The scan chain, applies the PI test data to the input port of the IP core through the WBR unit of the test shell, and unloads the SO test data and PO test data converted from the SI test data after passing through the internal logic circuit of the IP core. The data is measured and compared with the SO pattern in the IP core test pattern, and the PO test data is measured and compared with the PO pattern in the IP core test pattern. Therefore, it is possible to use the test pattern of the IP core to obtain the test data of the IP core based on the test case, and compare it with the corresponding pattern in the test pattern.

Description

A Test Method for IP Core Based on Test Shell

technical field

The present application relates to the field of System-on-Chip (SoC), and in particular, to an IP core testing method based on a test case.

Background technique

With the advancement of integrated circuit technology and the continuous improvement of people's requirements for integrated circuit performance and time-to-market, system-on-chip technology has become the development trend and mainstream technology of today's integrated circuits. The test development of the entire SoC chip requires the test information of each intellectual property (Intellectual Property, IP) core, which requires the IP provider to provide the SoC integrator with the internal design for test (Design For Test, DFT) strategy and test mode of the IP And the corresponding test protocol, fault coverage and test patterns. In the scan chain-based test pattern, the test data completes corresponding test establishment, test data loading, unloading, capturing and other operations according to the prescribed test protocol.

As shown in Figure 1, the IP core test pattern includes test clock CLK, test reset RSTN, IP core internal scan chain scan enable (Scan Enable, SE), IP core internal scan chain scan input (Scan Input, SI), IP core Internal scan chain scan output (Scan Output, SO), IP core primary input (Primary Input, PI), IP core primary output (Primary Output, PO) and other test data. Stage (1) scan input is to load the scan chain test data of the test pattern, and stage (5) scan output is to unload the scan chain test data of the test pattern. At this time, the scan enable signal is valid. For the first test pattern, it is not. There is scan chain test data unloading. For the second to the last test pattern, the test result output and measurement process captured by the last scan chain are performed at the same time as the scan chain test data is shifted in. For the last test pattern, only scan is performed. Unloading of chain test data; Phase (2) Parallel measurement refers to applying test pattern input to all primary inputs, and simultaneously performing test pattern output and test data measurement comparison at all primary outputs; Phase (3) Parallel capture refers to internal The logical test results are captured into the scan chain, so that the captured test data can be unloaded in the next shift operation. At this time, the scan enable signal is invalid. For the first test pattern, there is no internal register pair. Logic output capture process; stage (4) chain head output is to measure and compare the first test data scanned by the test shell scan chain (all measurement operations in Figure 1 occur after the test clock pulse, so in the next test pattern The first-of-chain output should be done before the scan input starts).

After the IP core is surrounded by a test case based on the IEEE1500 standard, all primary inputs and primary outputs correspond to a WBR cell (cell), and the IP core cannot be directly controlled and observed at the primary input and primary output. Therefore, the primary input of the IP core is originally The test data applied by the port will be applied by the test case serial port (Wrapper Serial Port, WSP) or the test case parallel port (Wrapper Parallel Port, WPP) in the test case. Similarly, the test originally output by the primary output port of the IP core The data is also output by WSP or WPP, and measured and compared. Therefore, the test protocol and the order of the test data shown in FIG. 1 will change. It can be seen that how to use the test pattern of the IP core to test the IP core provided with the test shell has become an urgent problem to be solved at present.

SUMMARY OF THE INVENTION

The present application provides an IP core testing method based on a test case, which aims to solve the problem of how to use the test pattern of the IP core to test the IP core provided with the test case.

In order to achieve the above purpose, the application provides the following technical solutions:

A test shell-based IP core testing method, comprising:

Extract the scan chain scan input SI test data and primary input PI from the IP core test pattern;

According to the test instruction, the SI test data and the PI test data are loaded through the input port of the test shell, wherein the SI test data enters the scan chain of the IP core after passing through the input port, and the PI test data passes through After the input port, it is applied to the input port of the IP core by the WBR unit of the test shell;

According to the test instruction, the SO test data and PO test data are unloaded through the output port of the test case, and the SO test data is converted from the SI test data after passing through the internal logic circuit of the IP core. The PO test data is obtained by converting the PI test data through the internal logic circuit of the IP core;

The SO test data is measured and compared with the SO pattern in the IP core test pattern, and the PO test data is measured and compared with the PO pattern in the IP core test pattern, wherein the SO Test data is output to the output port by the scan chain of the IP core, and the PO test data is captured by the WBR unit from the output port of the IP core to the output port of the test shell.

Optionally, before loading the SI test data and the PI test data through the input port of the test case, the method further includes:

moving test instructions into the test shell;

The test instruction is serial test access, and the loading of the SI test data and the PI test data through the input port of the test case includes:

The SI test data and the PI test data are input through the test case serial input WSI in the test case.

Optionally, the inputting of the SI test data and the PI test data by serially inputting the WSI through the test case in the test case includes:

In the case that the scan enable SE signal of the scan chain in the IP core and the shift control signal ShiftWR of the test shell register are valid, and the serial control signals of other test shells are invalid, the SI test data and the PI test are loaded according to the data path of the WBR. Data, the test data of the WBR unit close to the test shell serial output WSO is loaded first, and the test data of the WBR unit close to the test shell serial input WSI is loaded last, and the loaded test data includes: N _output irrelevant values, N _ff Described SI test data and N _input described PI test data, wherein, N _output is the number of IP core function output ports, N _ff is the number of scan chain scan units in the IP core, and N _input is the number of IP core function input ports. number.

Optionally, the inputting of the SI test data and the PI test data by serially inputting the WSI through the test case in the test case includes:

为所述IP核最长输入扫描链的长度。In the case that the scan enable SE signal of the scan chain in the IP core and the shift control signal ShiftWR of the test shell register are valid, and the serial control signals of other test shells are invalid, the SI test data and the PI test are loaded according to the data path of the WBR. Data, the test data of the WBR unit close to the test shell serial output WSO is loaded first, and the test data of the WBR unit close to the test shell serial input WSI is loaded last. The loaded test data includes: (N _max -N _imax ) irrelevant value, _Nff of the SI test data and _Ninput of the PI test data, wherein, _Nmax is the length of the longest scan chain of the IP core,

Enter the length of the longest scan chain for the IP core.

Optionally, the unloading of SO test data and PO test data through the output port of the test shell includes:

If the test command is a serial test access, the SO test data and the PO test data are unloaded through the WSO serially output from the test shell in the test shell.

Optionally, the serially outputting the WSO unloading the SO test data and the PO test data through the test shell in the test shell includes:

Under the circumstance that the scan enable SE signal of the scan chain in the IP core and the shift control signal ShiftWR of the test shell register are valid, and the serial control signals of other test shells are invalid, the SO test data and the PO test are unloaded according to the data path of the WBR. Data, the test data of the WBR unit close to the test shell serial output WSO is unloaded first, and the test data of the WBR unit close to the test shell serial input WSI is unloaded last, and the unloaded test data includes: (N _output -1) PO test data, _Nff of the SO test data, and N _input irrelevant values.

Optionally, the serially outputting the WSO unloading the SO test data and the PO test data through the test shell in the test shell includes:

个无关值，其中，

为所述IP核最长输出扫描链的长度。Under the circumstance that the scan enable SE signal of the scan chain in the IP core and the shift control signal ShiftWR of the test shell register are valid, and the serial control signals of other test shells are invalid, the SO test data and the PO test are unloaded according to the data path of the WBR. Data, the test data of the WBR unit close to the test shell serial output WSO is unloaded first, and the test data of the WBR unit close to the test shell serial input WSI is unloaded last, and the unloaded test data includes: (N _output -1) PO test data, _Nff of the SO test data and

an irrelevant value, where,

is the length of the longest output scan chain of the IP core.

Optionally, before loading the SI test data and the PI test data through the input port of the test case, the method further includes:

moving test instructions into the test shell;

The test instruction is parallel test access, and the loading of the SI test data and the PI test data through the input port of the test case includes:

The SI test data and the PI test data are input through WPI in parallel through the test case in the test case.

Optionally, the inputting of the SI test data and the PI test data by inputting the WPI in parallel through the test case in the test case includes:

个无关值和

个所述PI测试数据/所述SI测试数据，其中，N_wpp-max为最长并行扫描链的长度，

为第n条并行扫描链输入扫描链的长度。Under the condition that the scan chain scan enable SE signal and the test shell parallel scan enable signal WPSE in the IP core are valid, the SI test data and the PI test data are loaded according to the data path of the WBR, and the parallel output of the WPO near the test shell The test data of the WBR unit is loaded first, and the test data of the WBR unit input to the WPI in parallel near the test shell is loaded last. The test data loaded by the nth parallel scan chain includes:

irrelevant values and

the PI test data/the SI test data, where N _wpp-max is the length of the longest parallel scan chain,

Enter the length of the scan chain for the nth parallel scan chain.

Optionally, the inputting of the SI test data and the PI test data by inputting the WPI in parallel through the test case in the test case includes:

个无关值和

个所述PI测试数据和所述SI测试数据。Under the condition that the scan chain scan enable SE signal and the test shell parallel scan enable signal WPSE in the IP core are valid, the SI test data and the PI test data are loaded according to the data path of the WBR, and the parallel output of the WPO near the test shell The test data of the WBR unit is loaded first, and the test data of the WBR unit input to the WPI in parallel near the test shell is loaded last. The test data loaded by the nth parallel scan chain includes:

irrelevant values and

the PI test data and the SI test data.

Optionally, the unloading of SO test data and PO test data through the output port of the test shell includes:

If the test command is a parallel test access, the SO test data and the PO test data are unloaded through the WPO in parallel output from the test shell in the test shell.

Optionally, the parallel output of WPO unloading the SO test data and the PO test data through the test shell in the test shell includes:

个所述PI测试数据、所述SI测试数据和

个无关值，其中，

为第n条并行扫描链输出扫描链的长度。Under the condition that the scan chain scan enable SE signal and the test shell parallel scan enable signal WPSE in the IP core are valid, the SO test data and the PO test data are unloaded according to the data path of the WBR, and the WPO test data is output in parallel near the test shell. The test data of the WBR unit is unloaded first, and the test data of the WBR unit input to the WPI in parallel near the test shell is unloaded last. The test data unloaded by the nth parallel scan chain includes:

the PI test data, the SI test data and

an irrelevant value, where,

Output the length of the scan chain for the nth parallel scan chain.

Optionally, the parallel output of WPO unloading the SO test data and the PO test data through the test shell in the test shell includes:

个所述PO测试数据和所述SO测试数据和

个无关值。When the internal scan chain scan enable SE signal of the IP core and the parallel scan enable WPSE signal of the test shell are valid, the SO test data and the PO test data are unloaded according to the data path of the WBR, and the WPO test data is output in parallel near the test shell. The test data of the WBR unit is unloaded first, and the test data of the WBR unit input to the WPI in parallel near the test shell is unloaded last. The test data unloaded by the nth parallel scan chain includes:

the PO test data and the SO test data and

an irrelevant value.

In the IP core testing method based on the test shell described in this application, the scan chain scan input SI and the primary input PI are extracted from the IP core test pattern, and the SI test data is loaded into the IP through the test shell input port loading according to the test instruction. The scan chain of the core applies the PI test data to the input port of the IP core through the WBR unit of the test shell, and unloads the internal logic circuit of the IP core through the SI test data according to the test instruction After converting the obtained SO test data and PO test data, measure and compare the SO test data with the SO pattern in the IP core test pattern, and compare the PO test data with the SO pattern in the IP core test pattern. The PO graph is measured and compared, wherein the SO test data is output to the output port by the scan chain of the IP core, and the PO test data is captured by the WBR unit from the output port of the IP core to the output port. Test case output port. It can be seen that the method described in this application can use the test pattern of the IP core to obtain the IP core test data based on the test case, and compare it with the corresponding pattern in the test pattern.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

Fig. 1 is the schematic diagram of IP core test pattern;

2 is a flowchart of an IP core testing method based on a test shell disclosed in an embodiment of the application;

Fig. 3 is a kind of schematic diagram of IP core test shell;

4 is a flowchart of another IP core testing method based on a test shell disclosed by an embodiment of the application;

5 is a diagram of a test protocol for moving a test instruction into a WIR through a WSP disclosed in an embodiment of the present application;

Fig. 6 a) the schematic diagram of the IP core test pattern after the installation of the test shell obtained according to the IP core test pattern conversion disclosed by the embodiment of the application;

6b) is a schematic diagram of an IP core test pattern disclosed in an embodiment of the application;

Fig. 7 is the schematic diagram of another kind of IP core test case;

8 is a flowchart of another IP core test based on a test shell disclosed by an embodiment of the application;

Fig. 9 is the schematic diagram that is converted into the test pattern of test shell from IP core test pattern;

10 is a schematic diagram of a circuit for generating an enable signal disclosed in an embodiment of the present application;

11 is a schematic diagram of a signal reflected by a method disclosed in an embodiment of the present application;

FIG. 12 is a schematic diagram of a signal reflected by a method disclosed in an embodiment of the present application.

Detailed ways

The IP core test shell structure specified by the IEEE Std 1500 standard consists of a test shell boundary register (WrapperBoundary Register, WBR), a test shell bypass register (Wrapper Bypass Register, WBY), a test shell instruction register (Wrapper Instruction Register, WIR), a test shell Serial port (Wrapper SerialPort, WSP) and optional test shell parallel port (Wrapper Parallel Port, WPP) composition.

Among them, WBR is the data register, which is used to provide test stimulus and receive test response. The WBR consists of serially connected test case boundary register units (WBR Cell), which can realize the application of test excitation and the capture of test response, so as to realize the control and observation of the embedded IP core. Each input and output port of the embedded IP core has a WBR Cell, but the test access mechanism (Test Access Mechanism, TAM) port and the analog port can be set without WBRCell. IEEE Std 1500 defines only two types of WBR Cells: Input WBR Cell and Output WBR Cell. WBRCell provides 4 input and output ports: Cell Test Input (CTI), Test Output (CTO), Cell Functional Input (CFI), and CellFunctional Output (CFO) CTI and CTO form a shift path (CTI→CTO), and CFI and CFO form a functional path (CFI→CFO). Each WBR Cell includes at least one storage unit. The shift paths of all WBR Cells are connected end to end to form a test case scan chain, which is connected between the test case serial input (Wrapper Serial Input, WSI) and the test case serial output (Wrapper Serial Output, WSO). For the input cell, the CFI is connected to the test case function input, the CFO is connected to the IP core input, and for the output cell, the CFI is connected to the IP core output, and the CFO is connected to the test case function output. As long as the WBR Cell reaches the mode and behavior specified by IEEE1500, there is no fixed structure.

WBY is the data register and provides a branch between the test case serial input WSI and the test case serial output WSO. When no other data register is available, it can be selected by the current test shell instruction as the default data register, providing a fast path for test data to pass through the test of other IP cores.

The WIR is used to control the operation of the test case, and the WIR sends instructions serially into the test case circuit through the test case serial input WSI and the test case serial control (Wrapper Serial Control, WSC). And according to the loaded instructions, it determines whether the current test mode is out-of-core test or internal test, determines whether the access mode is serial access or parallel access, and determines whether it is connected between the test shell serial input WSI and the test shell serial output WSO. Whether the register is WIR, WBR or WBY, finally, the instruction register is responsible for generating the test shell control signal according to the loaded instruction to control the shift of WBY, the shift of WBR Cell, capture, update, transfer operations, and the selection of strobes.

WSP is the basic port of the test shell, which is used for the input and output of instructions and data in the test shell registers. In addition to the test shell serial input and output (WSI, WSO), it also contains the test shell serial control (WSC) that controls all the test shell registers. ), WSC consists of 6 mandatory signal lines and 2 optional signal lines, including: reset signal (WRSTN), clock signal (WRCK), instruction register selection signal (SelectWIR), register shift control signal (ShiftWR), register Capture signal (CaptureWR), register update signal (UpdateWR), register conversion signal (TransferDR, optional), auxiliary clock signal (AUXCK, optional). When SelectWIR is active, WIR is connected between WSI and WSO. When SelectWIR is inactive, WBR or WBY is connected between WSI and WSO.

The optional WPP provides parallel access to the test shell, which consists of the test shell parallel input (Wrapper Parallel Input, WPI), the test shell parallel output (Wrapper Parallel Output, WPO) and the test shell parallel control (Wrapper Parallel Control, WPC). It can split the serial test case scan chain into multiple parallel scan chains, saving test time. The larger the WPP width, the shorter the test time, but the more test pin resources are required, so it should be considered as a trade-off between test time and test resources.

The purpose of the test pattern conversion method described in this embodiment is to convert the test pattern at the IP core level into the test pattern at the test shell level, so as to test the IP core embedded in the test shell.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

A test shell-based IP core testing method disclosed in the embodiment of the present application, as shown in FIG. 2 , includes the following steps:

S201: Extract SI and PI test data from the IP core test graph;

As shown in Figure 1, the IP core test pattern includes test clock CLK, test reset RSTN, IP core internal scan chain scan enable (Scan Enable, SE), IP core internal scan chain scan input (Scan Input, SI), IP core Internal scan chain scan output (Scan Output, SO), primary input (Primary Input, PI), primary output (Primary Output, PO) and other test data. After the test case is installed, the ports originally used to access the SI, SO, PI, and PO signals are embedded in the test case and cannot be accessed, and only the input terminals for CLK, RSTN, and SE can be accessed. In addition, the IEEE1500 test case mandates serial port (WSP) access and optional parallel port (WPP) access. Therefore, the IP core test based on the test shell should first extract the SI and PI test data from the IP core test pattern, and then convert the IP core test pattern into a test pattern including CLK, RSTN, SE, WSP and WPP according to the test protocol.

S202: load the SI test data and the PI test data into the test shell according to the test instruction;

The SI test data enters the scan chain of the IP core after passing through the input port, and the PI test data is applied to the input of the IP core by the WBR unit of the test shell after passing through the input port port.

S203: unload SO test data and PO test data through the output port of the test shell according to the test instruction;

The SO test data is converted from the SI test data after passing through the internal logic circuit of the IP core, and the PO test data is converted from the PI test data after passing through the internal logic circuit of the IP core.

S204: after the SO test data is obtained by unloading, measure and compare the SO test data with the SO pattern in the IP core test pattern;

Wherein, the SO test data is output to the output port by the scan chain of the IP core. It should be noted that, in practical applications, when the SO test data is captured from the output port, the comparison with the SO pattern in the IP core test pattern is performed.

S205: After the PO test data is acquired by uninstalling, measure and compare the PO test data with the PO pattern in the IP core test pattern.

Wherein, the PO test data is captured by the WBR unit from the output port of the IP core to the output port of the test shell. It should be noted that, in practical applications, when the PO test data is captured from the output port, the comparison with the PO pattern in the IP core test pattern is performed.

Specifically, different test instructions will lead to different ports for loading and unloading test data in the test shell. The above steps will be described in detail below from the serial and parallel test instructions respectively.

扫描链1上扫描寄存器的数目为

因此，IP核内部扫描链扫描单元的数目为N_ff＝8。IP核内部扫描链和测试壳扫描链串联后的长度为N_wsp-max＝N_output+N_ff+N_input。(图3中粗线代表串行内部测试的数据通路，图3中未画出并行外部测试的数据通路。)Another IP core testing method based on a test shell disclosed in the embodiment of the present application is described. In this embodiment, serial test instructions and the IP core test shell shown in FIG. The number of IP core function input ports is N _input = 4 (excluding clock CLK, reset RSTN, scan input SI, scan enable SE), and the number of IP core function output ports is N _output = 4 (excluding scan output SO) , there are 2 scan chains inside the IP core, among which, the number of scan registers on scan chain 0 is

The number of scan registers on scan chain 1 is

Therefore, the number of scan chain scan units in the IP core is N _ff =8. The length of the concatenated scan chain of the IP core and the scan chain of the test shell is N _wsp-max =N _output +N _ff +N _input . (The thick line in Figure 3 represents the data path for the serial internal test, and the data path for the parallel external test is not shown in Figure 3.)

As shown in Figure 4, the method described in this embodiment includes the following steps:

S401: Extract SI, PI test data, SO and PO test data to be compared from the IP core test graph;

Among them, the SO and PO test data to be compared are the SO and PO test patterns in the IP core test pattern, which can be extracted here for subsequent comparison use. In order to avoid confusion, the SO test data extracted here is referred to as the SO test data to be compared, and the PO test data is referred to as the PO test data to be compared.

S402: Move the test command into the test shell;

In this embodiment, a test command is moved into the WIR through a wrapper serial port (Wrapper Serial Port, WSP). Figure 5 shows the test protocol for moving test instructions into the WIR through the WSP. In Figure 5, the IP core signals include: clock signal (CLK), reset signal (RSTN), scan enable signal (SE), and the test shell signals include: reset signal (WRSTN), clock signal (WRCK), instruction register selection signal (SelectWIR), register shift control signal (ShiftWR), register capture control signal (CaptureWR), register update control signal (UpdateWR), test shell serial input signal (WSI). During the shift into the test command to the WIR, the IP core signals are invalid. At the first falling edge of WRCK, SelectWIR is valid, indicating that the selected WIR is connected between WSI and WSO; at the second falling edge of WRCK, ShiftWR is valid, indicating that the next rising edge of WRCK can start the WIR shift operation; at the third From the rising edge of WRCK to the sixth rising edge of WRCK, the test command is shifted from WSI to WSO. During the WIR shift operation, SelectWIR and ShiftWR remain at 1, and the test command width is user-defined. In this embodiment, the test command width It is 4; at the 7th WRCK rising edge, UpdateWR is valid, indicating that the next WRCK falling edge starts the WIR update operation, and the updated test command can determine the current test access mechanism; at the 8th WRCK falling edge, SelectWIR is invalid, indicating that Select WBR or WBY to connect between WSI and WSO, and the test command shift-in process ends.

S403: Determine that the test instruction is a serial test access;

S404: Load the SI test data and the PI test data into the test shell through the test shell serial input (Wrapper Serial Input, WSI) in the test shell;

Specifically, in the scan input stage, SE and ShiftWR are valid, SelectWIR, CaptureWR, and UpdateWR are invalid, and at each rising edge of WRCK, the SI test data and the PI test data are loaded according to the data path of WBR, close to the test shell serial The test data of the WBR unit of the output WSO is loaded first, and the test data of the WBR unit of the serial input WSI close to the test shell is loaded last. The loaded test data includes: N _output irrelevant values (can be 0 or 1, the same below), N _ff scan input test data and N _input primary input test data, where N _output is the IP core function output The number of ports, N _ff is the number of scan chain scan units in the IP core, and N _input is the number of IP core function input ports. This stage completes the scan input test data of the test pattern and the loading of the preliminary input test data.

个SI0测试数据

个SI1测试数据→N_input个PI测试数据。其中，SI0为IP核内部扫描链0的扫描输入，SI1为IP核内部扫描链1的扫描输入，PI为初级输入。In this embodiment, the scan input stage is the third cycle to the eighteenth cycle in Fig. 6b). The test data of the device include: N _output irrelevant values

SI0 test data

SI1 test data → N _input PI test data. Among them, SI0 is the scan input of the internal scan chain 0 of the IP core, SI1 is the scan input of the internal scan chain 1 of the IP core, and PI is the primary input.

S405: Capture the primary output of the IP core to the test shell scan chain;

Specifically, in the parallel measurement stage, SelectWIR, ShiftWR, SE and UpdateWR are invalid, and the CaptureWR signal is valid, indicating that the capture operation can be started at the rising edge of WRCK, and the primary output of the IP core is captured to the test shell scan chain output WBR unit, so that the next time In the shift operation, the captured primary output test data is shifted out along the scan chain, but the CLK has no clock pulse, thereby ensuring that the primary output value remains unchanged during the capture process.

In this embodiment, the parallel measurement stage is the 19th cycle in Fig. 6b).

S406: Capture the internal logic output of the IP core to the internal scan chain of the IP core;

Specifically, in the parallel capture stage, SelectWIR, ShiftWR, SE, CaptureWR and UpdateWR are invalid. On the rising edge of CLK, the internal logic output of the IP core is captured into the scan chain, so that the captured test data edge will be captured in the next shift operation. Scan chain moved out.

In this embodiment, the parallel capture stage is the 20th cycle in Fig. 6b).

S407: output and measure the test shell scan chain head;

Specifically, in the test shell scan chain chain head output stage, SelectWIR, CaptureWR, UpdateWR are invalid, SE and ShiftWR are valid, and CLK and WRCK have no clock pulses to ensure that no shift operation is performed during the chain head output process. The first test data of the scan chain is output, and the test data is measured. The measurement operation should take place after the test data is stable.

In this embodiment, the first output stage of the scan chain of the test shell is the second cycle in Fig. 6b).

S408: Unload and measure SO test data and PO test data in the test case through the WSO in the test case.

S409: After measuring the SO test data and the PO test data, measure and compare the SO test data and the SO pattern in the IP core test pattern, that is, the SO test data to be compared, and compare the PO test data with the SO pattern to be compared. The PO pattern in the IP core test pattern, that is, the PO test data to be compared, is measured and compared to obtain the measurement result for the IP core.

Specifically, in the scan output stage, that is, the third cycle to the eighteenth cycle in Fig. 6b), the state of the control signal is consistent with that of S407, and at each WRCK falling edge, the SO test data and the PO are unloaded according to the data path of the WBR For the test data, the test data of the WBR unit close to the test shell serially outputting the WSO is unloaded first, and the test data of the WBR unit close to the test shell serially inputting the WSI is unloaded last. The unloaded test data includes: (N _output -1) primary output test data, N _ff scan output test data, and N _input irrelevant values. The test data is measured during the removal process (irrelevant values are not measured), and the measurement operation should take place after the test data is stabilized. This stage completes the scan output test data of the test pattern and the unloading of the primary output test data.

个SO0测试数据

个SO1测试数据→N_input个无关值。其中，SO0为IP核内部扫描链0的扫描输出，SO1为IP核内部扫描链1的扫描输出，PO为初级输出。In this embodiment, the scan output stage is the third cycle to the eighteenth cycle in Fig. 6b), and the unloaded test data includes: (N _output -1) PO test data

SO0 test data

SO1 test data → N _input irrelevant values. Among them, SO0 is the scan output of the internal scan chain 0 of the IP core, SO1 is the scan output of the internal scan chain 1 of the IP core, and PO is the primary output.

其中，

代表IP核内部每条扫描链的长度，n代表IP核内部扫描链数目。加装测试壳后，串行测试存取机制下，该阶段花费的测试时钟周期等于连接在WSI和WSO之间的扫描链长度，即N_wsp-max，图6中N_wsp-max＝16。It should be noted that the test shell-level test pattern is consistent with the IP core-level test pattern. During the application process of the second to the last test pattern, the output and measurement of the last scan chain capture test result are simultaneously performed, that is, the current test. The scan-in phase of the pattern and the scan-out phase of the last test pattern are performed simultaneously. For the application process of the first test pattern, there is no output of the previous test result, and similarly, for the output and measurement process of the last test result, there is no application process of the next test pattern. In the IP core test graph shown in Figure 6a), the test clock cycle spent in the scan input and output stage is equal to the length of the longest scan chain inside the IP core, namely

in,

Represents the length of each scan chain in the IP core, and n represents the number of scan chains in the IP core. After the test case is installed, under the serial test access mechanism, the test clock cycle spent in this stage is equal to the length of the scan chain connected between the WSI and the WSO, that is, N _wsp-max , N _wsp-max =16 in FIG. 6 .

Under the serial test access mechanism, the converted test pattern is shown in Figure 6 (all measurement operations in Figure 6 take place after the test data is stable). Figure 6a) is the IP core test pattern, its various stages are in one-to-one correspondence with Figure 1, the only difference is that Figure 1 shows two consecutive scan stages, the first scan stage includes the N-1th test pattern scan output and the first scan N test pattern scan input, the second scan stage includes the Nth test pattern scan output and N+1 test pattern scan input, while Figure 6a) only shows one scan stage, which includes the N-1th test pattern scan output and the Nth test pattern scan input. In order to maintain the coherence between the chain head output and the scan output, Figure 6a) places the chain head output stage before the scanning stage. Figure 6b) is the IP core test pattern after the test case is installed, which is converted according to the IP core test pattern. Note that the test reset ports (RSTN and WRSTN) and the test case parallel port WPP are not shown in the figure because the test reset does not require switching, and WPP is ineffective under this mechanism. It can be seen that under the serial test access mechanism, the key point of the IP core test method based on the test shell is to convert the parallel PI and PO test data into serial, and move them in or out serially according to the connection method of the test shell scan chain. , specifically, in Figure 6b), PI[3], PI[2], PI[1], and PI[0] of the Nth test pattern are serially shifted in from the 15th cycle to the 18th cycle, and the N-1 PO[0], PO[1], PO[2], and PO[3] of the test pattern are sequentially shifted out from the second cycle to the sixth cycle.

扫描链1上扫描寄存器的数目为

因此，IP核内部扫描链扫描单元的数目为N_ff＝8。测试壳并行端口的宽度为W_wpp＝3。(图7中粗线代表并行内部测试的数据通路，图7中未画出并行外部测试的数据通路。可以看出，并行内部测试时，3条并行扫描链的长度分别为IP核内部2条扫描链长度

以及输入端口链长度和输出端口链长度之和(N_input+N_output)。)Another test pattern conversion method disclosed in the embodiment of the present application, in this embodiment, the parallel test command and the IP core test shell shown in FIG. 7 are used as an example for description. In FIG. 7, the IP core function input port The number is N _input = 4 (excluding clock CLK, reset RSTN, scan input SI, scan enable SE), the number of IP core function output ports is N _output = 4 (excluding scan output SO), there are 2 scan chains, where the number of scan registers on scan chain 0 is

The number of scan registers on scan chain 1 is

Therefore, the number of scan chain scan units in the IP core is N _ff =8. The width of the test case parallel port is W _wpp =3. (the thick line in Fig. 7 represents the data path of the parallel internal test, and the data path of the parallel external test is not drawn in Fig. 7. It can be seen that during the parallel internal test, the lengths of 3 parallel scan chains are respectively 2 inside the IP core scan chain length

And the sum of the input port chain length and the output port chain length (N _input +N _output ). )

代表IP核内部扫描链的长度，n代表IP核内部扫描链数目。如图8所示，本实施例所述方法包括以下步骤：The longest scan chain connected between the parallel input of the test case and the parallel output of the test case is characterized by N _wpp-max (N _wpp-max =8 in Fig. 7), where,

Represents the length of the scan chain in the IP core, and n represents the number of scan chains in the IP core. As shown in Figure 8, the method described in this embodiment includes the following steps:

S801: Extract SI, PI test data, SO and PO test data to be compared from the IP core test graph;

S802: Move the test command into the test shell;

S803: Determine that the test instruction is a parallel test access;

S804: load the SI test data and the PI test data into the test case through parallel input of the test case in the test case;

个无关值和

个初级输入测试数据、扫描输入测试数据。其中，N_wpp-max为最长并行扫描链的长度，

为第n条并行扫描链输入扫描链的长度。该阶段完成测试图形的扫描输入测试数据和初级输入测试数据装载。Specifically, in the scan input stage, WPSE and SE are valid, and at each rising edge of WRCK, the SI test data and the PI test data are loaded according to the data path of the WBR, and the test data of the WBR unit of the WPO is output in parallel near the test shell. Loaded first, the test data of the WBR unit input to the WPI in parallel near the test shell is loaded last. The test data loaded by the nth parallel scan chain includes:

irrelevant values and

A primary input test data, scan input test data. where N _wpp-max is the length of the longest parallel scan chain,

Enter the length of the scan chain for the nth parallel scan chain. This stage completes the scan input test data of the test pattern and the loading of the preliminary input test data.

In this embodiment, in the scan input stage, that is, the third cycle to the tenth cycle in FIG. 9 , the test data loaded by each parallel scan chain is:

个无关值

个SI0测试数据；a) WPI[2]:

irrelevant value

SI0 test data;

个无关值

个SI1测试数据；b) WPI[1]:

irrelevant value

SI1 test data;

c) WPI[0]: (N _wpp-max -N _input ) irrelevant values→N _input PI test data.

S805: Capture the primary output of the IP core to the test shell scan chain;

Specifically, in the parallel measurement stage, WPSE and SE are invalid, indicating that the capture operation can be started at the rising edge of WRCK, and the primary output of the IP core is captured to the test shell scan chain output WBR unit, so that the captured primary output will be captured in the next shift operation. The output test data is shifted out along the scan chain, but the CLK is not clocked, ensuring that the primary output value remains unchanged during capture.

In this embodiment, the parallel measurement stage is the 11th cycle in FIG. 9 .

S806: Capture the internal logic output of the IP core to the internal scan chain of the IP core;

Specifically, in the parallel capture stage, WPSE and SE are invalid. On the rising edge of CLK, the internal logic output of the IP core is captured into the scan chain, so that the captured test data is shifted out along the scan chain in the next shift operation.

In this embodiment, the parallel capture stage is the twelfth cycle in FIG. 9 .

S807: Output and measure the test shell scan chain head;

Specifically, in the first output stage of the scan chain of the test shell, WPSE and SE are valid, and CLK and WRCK have no pulses, ensuring that no shift operation is performed during the output process of the chain head, and only the first test data of the parallel scan chain is output through WPO , and measure after the test data is stable.

In this embodiment, the first output stage of the test shell scan chain chain is the second cycle in FIG. 9 .

S808: Unload and measure SO test data and PO test data through the WPO in the test case.

S809: after measuring the SO test data and the PO test data, measure and compare the SO test data and the SO test data to be compared respectively, and measure and compare the PO test data and the PO test data to be compared, to get the measurement results for the IP core.

个初级输出测试数据、扫描输出测试数据和

个无关值。移出过程中对输出测试数据进行测量(无关值不用测量)，测量操作应发生在测试数据稳定之后。该阶段完成测试图形的扫描输出测试数据和初级输出测试数据卸载。Specifically, in the scan output stage, that is, from the 3rd cycle to the 10th cycle in FIG. 9 , the state of the control signal is consistent with that of S807, and at each falling edge of WRCK, the SO test data and the PO are unloaded according to the data path of WBR For test data, the test data of the WBR unit that is close to the test shell and output in parallel to the WPO is unloaded first, and the test data of the WBR unit that is close to the test shell and input in parallel to the WPI is unloaded last. The test data offloaded by the nth parallel scan chain includes:

primary output test data, scan output test data and

an irrelevant value. During the removal process, the output test data is measured (the irrelevant value is not measured), and the measurement operation should take place after the test data is stable. This stage completes the scan output test data of the test pattern and the unloading of the primary output test data.

In this embodiment, in the scan output stage, that is, the third cycle to the tenth cycle in FIG. 9 , the test data unloaded by each parallel scan chain is:

个SO0测试数据

个无关值；a) WPO[2]:

SO0 test data

an irrelevant value;

个SO1测试数据

个无关值；b) WPO[1]:

SO1 test data

an irrelevant value;

c) WPO[0]: (N _output -1) PO test data → (N _wpp-max -N _output ) irrelevant values.

It should be noted that the test shell-level test pattern is consistent with the IP core-level test pattern. During the application process of the second to the last test pattern, the output and measurement of the last scan chain capture test result are simultaneously performed, that is, the current test. The scan-in phase of the pattern and the scan-out phase of the last test pattern are performed simultaneously. For the application process of the first test pattern, there is no output of the previous test result, and similarly, for the output and measurement process of the last test result, there is no application process of the next test pattern. In the IP core test pattern, the test clock cycle spent in the scan input and output stage is equal to the length of the longest scan chain inside the IP core, that is, N _ip-max (=4). After the test shell is installed, the test clock cycle spent in this stage is Equal to the longest scan chain length connected between WPI and WPO, N _wpp-max . N _wpp-max =8 in FIG. 7 .

Under the parallel test access mechanism, the converted test pattern is shown in Figure 9 (note: all measurement operations in the figure take place after the test data is stable). In order to maintain the continuity between the chain head output and the scan output, Figure 9 places the chain head output stage before the scan input and output stage. Note that the test reset ports (RSTN and WRSTN) and the test shell serial port WSP are not shown in the figure, because the test reset does not require conversion, and the WSP is invalid under this mechanism. It can be seen that under the parallel test access mechanism, the key point of the test graph translation is to convert the test data of PI and PO into parallel, and move them in or out serially according to the connection mode of the test shell scan chain. Specifically, in Figure 9 , PI[3], PI[2], PI[1], PI[0] of the Nth test pattern are serially shifted in from the 7th cycle to the 10th cycle, PO[0], PI[0], PI[0] of the N-1th test pattern PO[1], PO[2], PO[3] are serially shifted out sequentially from the 2nd cycle to the 6th cycle.

It should be noted that, compared with WSP, WPP does not have a special capture operation enable signal CaptureWR. Therefore, this solution uses the circuit in Figure 10 to generate the capture operation enable of the WBR unit under the parallel test access mechanism inside the test shell device. Signal WP_CaptureWR. The circuit shown in Figure 10 includes a register and a 2-input NAND gate. The process of generating the circuit capture operation enable signal WP_CaptureWR is as follows: first register the WPSE signal for one shot and then output it, then invert the WPSE and combine it with the register The outputs are ANDed to get WP_CaptureWR.

It can be seen from Figure 6b) and Figure 9 that the scan chain takes a lot of cycles to scan in and out irrelevant values, resulting in scan input of valid test data of the Nth test pattern and valid test of the N-1th test pattern The scan output of the data cannot be performed exactly at the same time. In order to save testing time, in the embodiments of the present application, the methods described in the above embodiments are optimized, and an optimized IP core testing method based on a test shell is proposed. This optimization method can minimize the number of cycles for the scan chain to sweep in and out irrelevant values, thereby reducing the test time. The specific scheme is described as follows.

定义IP核最长输入扫描链长度为

串行测试存取机制下

并行测试存取机制下

Define the IP core input scan chain as the test shell input port chain plus the IP core internal scan chain, assuming that the input scan chain set is

Define the longest input scan chain length of the IP core as

Under serial test access mechanism

Under the parallel test access mechanism

定义IP核最长输出扫描链长度为

串行测试存取机制下

并行测试存取机制下

The IP core output scan chain is defined as the test shell output port chain plus the IP core internal scan chain, assuming that the output scan chain set is

Define the longest output scan chain length of the IP core as

Under serial test access mechanism

Under the parallel test access mechanism

扫描输入输出阶段所花费的测试周期数为N_max，则：Therefore, define the longest scan chain length of the IP core

The number of test cycles spent in the scan input and output stage is N _max , then:

IP核输出扫描链扫出无关值的周期数为

扫描输入输出阶段节约的测试周期数为N_wsp-max-N_max；Under the serial test access mechanism, the number of cycles for the IP core input scan chain to scan irrelevant values is

The number of cycles in which the IP core output scan chain sweeps out irrelevant values is

The number of test cycles saved in the scan input and output stage is N _wsp-max -N _max ;

…；各条IP核输出扫描链扫出无关值的周期数为

…；扫描输入输出阶段节约的测试周期数为N_wpp-max-N_max。Under the parallel test access mechanism, the number of cycles for each IP core input scan chain to scan irrelevant values is:

...; The number of cycles for each IP core output scan chain to scan out irrelevant values is

...; the number of test cycles saved in the scan input and output stage is N _wpp-max -N _max .

扫描链1上扫描寄存器的数目为

IP核最长输入扫描链长度为

IP核最长输出扫描链的长度为

IP核最长扫描链的长度为

优化的基于测试壳的IP核测试方法如图11所示(图11中所有测量操作发生在测试数据稳定之后)，它在扫描输入输出阶段与图6所述的方法不同，其他阶段的处理与图6所示的方法相同，不同之处具体描述如下：Taking a certain IP core test shell shown in FIG. 3 as an example to illustrate the IP core test method based on the test shell under the optimized serial test access mechanism, the number of input ports of the IP core function is N _input = 4 (excluding clock CLK, Reset RSTN, scan input SI, scan enable SE), the number of output ports of the IP core function is N _output = 4 (excluding scan output SO), there are 2 scan chains inside the IP core, among which, the number of scan registers on scan chain 0 is N output = 4 (excluding scan output SO). The number is

The number of scan registers on scan chain 1 is

The longest input scan chain length of the IP core is

The length of the longest output scan chain of the IP core is

The length of the longest scan chain of the IP core is

The optimized test shell-based IP core testing method is shown in Figure 11 (all measurement operations in Figure 11 take place after the test data has stabilized). It is different from the method described in Figure 6 in the scan input and output stage, and the processing in other stages is the same as that in Figure 6. The method shown in Figure 6 is the same, and the differences are described as follows:

个无关值、N_ff个扫描输入测试数据和N_input个初级输入测试数据。本实施例中，扫描输入阶段即图11中的第3周期到第14周期，装载的测试数据为：

个无关值

个SI0测试数据

个SI1测试数据→N_input个PI测试数据；1) In the scan input stage, the loaded test data includes:

irrelevant values, N _ff scan input test data, and N _input primary input test data. In this embodiment, in the scan input stage, that is, the third cycle to the 14th cycle in FIG. 11 , the loaded test data are:

irrelevant value

SI0 test data

SI1 test data → N _input PI test data;

个无关值。本实施例中，扫描输出阶段即图11中的第3周期到第14周期，卸载的测试数据为：(N_output-1)个PO测试数据

个SO0测试数据

个SO1测试数据

个无关值；2) In the scan output stage, the unloaded test data includes: (N _output -1) primary output test data, N _ff scan output test data and

an irrelevant value. In this embodiment, in the scan output stage, that is, the third cycle to the 14th cycle in FIG. 11 , the unloaded test data are: (N _output -1) PO test data

SO0 test data

SO1 test data

an irrelevant value;

According to the above input and output method, the number of test cycles saved is N _wsp-max -N _max =16-12=4.

扫描链1上扫描寄存器的数目为

测试壳并行端口宽度为W_wpp＝3。3条IP核输入扫描链的长度分别为：

IP核最长输入扫描链的长度为

3条IP核输出扫描链长度分别为：

IP核最长输出扫描链长度为

IP核最长扫描链长度为N_max＝4。优化的基于测试壳的IP核测试方法如图12所示(图12中所有测量操作发生在测试数据稳定之后)，它在扫描输入输出阶段的处理与图9所示的方法不同，其他阶段的处理与图9所示的方法相同，不同之处具体描述如下：Taking a certain IP core test shell shown in FIG. 7 as an example to illustrate the IP core test method based on the test shell under the parallel test access mechanism after optimization, the number of input ports of the IP core function is N _input = 4 (excluding clock CLK, reset RSTN, scan input SI, scan enable SE), the number of IP core function output ports is N _output = 4 (excluding scan output SO), there are 2 scan chains inside the IP core, among which, the number of scan registers on scan chain 0 for

The number of scan registers on scan chain 1 is

The width of the parallel port of the test case is W _wpp =3. The lengths of the input scan chains of the three IP cores are:

The length of the longest input scan chain of the IP core is

The lengths of the three IP core output scan chains are:

The longest output scan chain length of the IP core is

The longest scan chain length of the IP core is N _max =4. The optimized test shell-based IP core testing method is shown in Figure 12 (all measurement operations in Figure 12 take place after the test data is stable). The processing is the same as the method shown in Figure 9, and the differences are described in detail as follows:

个无关值和

个初级输入测试数据、扫描输入测试数据。本实施例中，扫描输入阶段即图12中的第3周期到第6周期，各条并行扫描链装载的测试数据为：1) In the scan input stage, the parallel input port of the test shell performs test data loading at the same time, and the test data loaded by the nth parallel scan chain includes:

irrelevant values and

A primary input test data, scan input test data. In this embodiment, in the scan input stage, that is, the third cycle to the sixth cycle in FIG. 12 , the test data loaded by each parallel scan chain is:

个无关值

个SI0测试数据；a) WPI[2]:

irrelevant value

SI0 test data;

个无关值

个SI1测试数据；b) WPI[1]:

irrelevant value

SI1 test data;

个无关值→N_input个PI测试数据；c) WPI[0]:

irrelevant values → N _input PI test data;

个初级输出测试数据、扫描输出测试数据和

个无关值。本实施例中，扫描输出阶段即图12中的第3周期到第6周期，各条并行扫描链卸载的测试数据为：2) In the scan output stage, the parallel output port of the test shell performs test data unloading at the same time, and the test data unloaded by the nth parallel scan chain includes:

primary output test data, scan output test data and

an irrelevant value. In this embodiment, in the scan output stage, that is, the third cycle to the sixth cycle in FIG. 12 , the test data unloaded by each parallel scan chain is:

个SO0测试数据

个无关值；a) WPO[2]:

SO0 test data

an irrelevant value;

个SO1测试数据

个无关值；b) WPO[1]:

SO1 test data

an irrelevant value;

个无关值；c) WPO[0]: (N _output -1) PO test data

an irrelevant value;

According to the above input and output method, the number of test cycles saved is N _wpp-max -N _max =8-4=4.

The optimized IP core test method based on the test shell reduces the number of cycles for the input scan chain to sweep in irrelevant values and the number of cycles for the output scan chain to scan out irrelevant values, so as to save the test cycle and optimize the test method.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments may be referred to each other.

The above description of the disclosed embodiments enables any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, this application is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (13)

1. An IP core testing method based on a testing shell is characterized by comprising the following steps:

extracting scan chain scan input SI test data and a primary input PI from an IP core test pattern;

loading the SI test data and the PI test data through an input port of a test shell according to a test instruction, wherein the SI test data enters a scan chain of the IP core after passing through the input port, and the PI test data is applied to the input port of the IP core by a WBR unit of the test shell after passing through the input port;

according to the test instruction, unloading SO test data and PO test data through an output port of the test shell, wherein the SO test data is obtained by converting the SI test data after passing through an internal logic circuit of the IP core, and the PO test data is obtained by converting the PI test data after passing through the internal logic circuit of the IP core;

measuring and comparing the SO test data with an SO pattern in the IP core test pattern, and measuring and comparing the PO test data with a PO pattern in the IP core test pattern, wherein the SO test data is output to the output port by the scan chain of the IP core, and the PO test data is captured to the output port of the test shell from the output port of the IP core by the WBR unit;

wherein the IP is intellectual property, the SI is scan input, the SO is scan output, the PI is primary input, the PO is primary output, and the WBR is test shell boundary register.

2. The method of claim 1, further comprising, prior to said loading said SI test data and said PI test data through a test shell input port:

moving a test instruction into the test shell;

the test instruction is serial test access, and loading the SI test data and the PI test data through the test shell input port includes:

and inputting the SI test data and the PI test data through a test shell serial input WSI in the test shell, wherein the WSI is the test shell serial input.

3. The method of claim 2, wherein the inputting the SI test data and the PI test data by a test shell serial input WSI in a test shell comprises:

loading the SI test data and the PI test data according to a data path of the WBR when a scan enable SE signal and a test shell register shift control signal ShiftWR in the IP core are effective and other test shell serial control signals are not effective, wherein the test data of a WBR unit close to a test shell serial output WSO is loaded first, the test data of a WBR unit close to a test shell serial input WSI is loaded last, and the loaded test data comprises: n is a radical of_outputAn independent value, N_ffThe SI test data and N_inputThe PI test data, wherein N_outputNumber of output ports for IP core function, N_ffFor the number of scan cells, N, in the internal scan chain of the IP core_inputIs the number of IP core function input ports, wherein the WSO is a test shell serial inputAnd (6) discharging.

4. The method of claim 2, wherein the inputting the SI test data and the PI test data by a test shell serial input WSI in a test shell comprises:

loading the SI test data and the PI test data according to a data path of the WBR when a scan enable SE signal and a test shell register shift control signal ShiftWR in the IP core are effective and other test shell serial control signals are not effective, wherein the test data of a WBR unit close to a test shell serial output WSO is loaded first, the test data of a WBR unit close to a test shell serial input WSI is loaded last, and the loaded test data comprises:

an independent value, N_ffThe SI test data and N_inputThe PI test data, wherein N_maxIs the length of the longest scan chain of the IP core,

and the length of the longest input scan chain is the IP core, wherein the SE is scan enable.

5. The method of claim 2, wherein offloading SO test data and PO test data through an output port of the test shell comprises:

and if the test instruction is serial test access, unloading the SO test data and the PO test data through a test shell serial output WSO in the test shell.

6. The method of claim 5, wherein the offloading the SO test data and the PO test data by a test shell serial output (WSO) in a test shell comprises:

scan enable SE signal and test case register shift control signal ShiftWR are asserted in scan chain within IP core, other test case stringsAnd in the case that the row control signal is invalid, unloading the SO test data and the PO test data according to the data path of the WBR, wherein the test data of the WBR unit close to the test shell serial output WSO is unloaded firstly, and the test data of the WBR unit close to the test shell serial input WSI is unloaded finally, and the unloaded test data comprises: (N)_output-1) said PO test data, N_ffThe SO test data and N_inputAn independent value.

7. The method of claim 5, wherein the offloading the SO test data and the PO test data by a test shell serial output (WSO) in a test shell comprises:

and in the case that the scan enable SE signal and the test shell register shift control signal ShiftWR in the IP core are effective and other test shell serial control signals are not effective, unloading the SO test data and the PO test data according to the data path of the WBR, wherein the test data of the WBR unit close to the test shell serial output WSO is unloaded firstly, the test data of the WBR unit close to the test shell serial input WSI is unloaded finally, and the unloaded test data comprises: (N)_output-1) said PO test data, N_ffThe SO test data and

an independent value, wherein,

the length of the longest output scan chain of the IP core is used.

8. The method of claim 1, further comprising, prior to said loading said SI test data and said PI test data through a test shell input port:

moving a test instruction into the test shell;

the test instruction is a parallel test access, and the loading the SI test data and the PI test data through the test shell input port includes:

and inputting the SI test data and the PI test data through a test shell in the test shells in parallel by inputting WPI, wherein the WPI is input in parallel by the test shells.

9. The method of claim 8, wherein the inputting the SI test data and the PI test data by parallel input of WPI through ones of the test shells comprises:

when the scan enable SE signal and the test shell parallel scan enable signal WPSE in the IP core are effective, the SI test data and the PI test data are loaded according to the data path of the WBR, the test data of the WBR unit close to the test shell parallel output WPO is loaded first, the test data of the WBR unit close to the test shell parallel input WPI is loaded last, and the test data loaded by the nth parallel scan chain comprises:

an independent value and

the PI test data and the SI test data, where N_wpp-maxIs the length of the longest parallel scan chain,

inputting the length of the scan chain for the nth parallel scan chain, wherein the WPO is the parallel output of the test shell.

10. The method of claim 8, wherein the inputting the SI test data and the PI test data by parallel input of WPI through ones of the test shells comprises:

loading the SI test data and the PI test data according to the data path of the WBR under the condition that the scan enable SE signal and the test shell parallel scan enable signal WPSE in the IP core are effective, wherein the test data of the WBR unit close to the test shell parallel output WPO is loaded first, and the test data close to the test shell parallel output WPO is output in parallelTest data of WBR units entering WPI are loaded finally, and the test data loaded by the nth parallel scan chain comprises:

an independent value and

the PI test data and the SI test data.

11. The method of claim 8, wherein offloading SO test data and PO test data through an output port of the test shell comprises:

and if the test instruction is parallel test access, unloading the SO test data and the PO test data through a test shell in the test shell in parallel output WPO.

12. The method of claim 11, wherein the offloading the SO test data and the PO test data through a test shell parallel output WPO of the test shells comprises:

in a case where the scan enable SE signal and the test case parallel scan enable WPSE signal within the IP core are valid, the SO test data and the PO test data are unloaded according to the data path of the WBR, the test data of the WBR cell close to the test case parallel output WPO is unloaded first, the test data of the WBR cell close to the test case parallel input WPI is unloaded last, and the unloaded test data of the nth parallel scan chain includes:

the PO test data/the SO test data and

an independent value, wherein,

for the nth parallelThe scan chain outputs the length of the scan chain.

13. The method of claim 11, wherein the offloading the SO test data and the PO test data through a test shell parallel output WPO of the test shells comprises:

in a case where the scan enable SE signal and the test shell parallel scan enable WPSE signal in the IP core are valid, the SO test data and the PO test data are unloaded according to the data path of the WBR, the test data of the WBR cell close to the test shell parallel output WPO is unloaded first, the test data of the WBR cell close to the test shell parallel input WPI is unloaded last, and the unloaded test data of the nth parallel scan chain includes:

the PO test data/the SO test data and

an independent value.

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