CN105990240B - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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- CN105990240B CN105990240B CN201510095432.XA CN201510095432A CN105990240B CN 105990240 B CN105990240 B CN 105990240B CN 201510095432 A CN201510095432 A CN 201510095432A CN 105990240 B CN105990240 B CN 105990240B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 137
- 238000000034 method Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000011248 coating agent Substances 0.000 claims abstract description 24
- 238000000576 coating method Methods 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 23
- 230000000694 effects Effects 0.000 claims abstract description 16
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 229910008482 TiSiN Inorganic materials 0.000 claims abstract description 8
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 238000011049 filling Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 29
- 230000008021 deposition Effects 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000004151 rapid thermal annealing Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 description 22
- 238000005530 etching Methods 0.000 description 9
- 239000007789 gas Substances 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910010038 TiAl Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 1
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to a kind of semiconductor devices and preparation method thereof, electronic device.The method includes the steps S1: providing semiconductor substrate, it is formed with several fins and the dummy gate around the fin on the semiconductor substrate, is also formed with the interlayer dielectric layer for filling gap between the adjacent dummy gate on the semiconductor substrate；Step S2: removing the dummy gate, to expose the fin；Step S3: gate dielectric and coating are sequentially formed on the fin；Step S4: executing Si ion implantation step, contains silicon covering layer to be formed.The present invention executes the Si ion implantation step to the TiN layer before depositing the workfunction layers, to form TiSiN layers, for controlling coating for the diffusion of the conductive layer Al formed in subsequent step, simultaneously will solve the problems, such as multi-Vt (multi-Vt), in addition, the method can also be effectively reduced ion implanting screen effect (IMP shadowing effect).
Description
Technical field
The present invention relates to semiconductor fields, in particular it relates to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technique
With the continuous development of semiconductor technology, the raising of performance of integrated circuits mainly passes through constantly diminution integrated circuit
The size of device is realized with improving its speed.Currently, due in pursuing high device density, high-performance and low cost half
Conductor industry has advanced to nanotechnology process node, and the preparation of semiconductor devices is limited by various physics limits.
With the continuous diminution of cmos device size, the challenge from manufacture and design aspect has promoted three dimensional design such as fin
The development of gate fin-fet (FinFET).Relative to existing planar transistor, FinFET is for 20nm and following work
The advanced semiconductor device of skill node, can effectively control device it is scaled caused by be difficult to the short channel overcome effect
It answers, the density of transistor array formed on a substrate can also be effectively improved, meanwhile, the grid in FinFET is around fin
(fin-shaped channel) setting, therefore electrostatic can be controlled from three faces, the performance in terms of Electrostatic Control is also more prominent.
Multi-Vt (multi-Vt) is a very big challenge, threshold voltage for 3D FINFET at present
Ion implanting and the ion implanting of workfunction layers can be used for solving the problems, such as multi-Vt (multi-Vt), but threshold
Threshold voltage ion implanting will reduce the mobility and mismatch performance of MOS, while to the ion implanting face of workfunction layers
The challenge for facing ion implanting shadowing effect (shadowing effect), in particular for the workfunction metal in NMOS device
Layer TiAl, since it is further exacerbated by with biggish thickness the shadowing effect of ion implanting.
In order to improve the performance and yield of semiconductor devices, need to be improved further the preparation method of device, with
Just the above problem is eliminated.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention is in order to overcome the problems, such as that presently, there are provide a kind of preparation method of semiconductor devices, comprising:
Step S1: providing semiconductor substrate, is formed with several fins on the semiconductor substrate and around the fin
The dummy gate of piece is also formed with the interlayer dielectric for filling gap between the adjacent dummy gate on the semiconductor substrate
Layer；
Step S2: removing the dummy gate, to expose the fin；
Step S3: gate dielectric and coating are sequentially formed on the fin；
Step S4: executing Si ion implantation step, contains silicon covering layer to be formed.
Optionally, in the step S3, the coating includes the TiN layer being sequentially depositing and TaN layers, in the TiN
The Si ion implantation step is executed in layer, to form TiSiN.
Optionally, after the step S4 the method also includes:
Step S5: workfunction layers are formed on the coating；
Optionally, the semiconductor substrate includes NMOS area and PMOS area, wherein the step S5 includes:
Step S51: PMOS workfunction layers are deposited in the NMOS area and the PMOS area；
Step S52: the PMOS workfunction layers in the NMOS area are removed；
Step S53: NMOS workfunction layers are deposited in the NMOS area.
Optionally, the method still further comprises to form barrier layer and metallic aluminum material layer after the step S4
Step, to form metal gates.
Optionally, the step S1 includes:
Step S11: semiconductor substrate is provided and executes ion implanting, to form trap；
Step S12: patterning the semiconductor substrate, forms the fin；
Step S13: deposition dummy gate dielectric layer and dummy gate material layer simultaneously pattern, to form the virtual grid
Pole.
Optionally, the step S1 may further comprise:
Step S14: source and drain LDD injection, and epitaxial growth half in the semiconductor substrate of dummy gate two sides are executed
Conductor material layer, to form lifting source and drain；
Step S15: ion implanting is executed again, and carries out rapid thermal annealing；
Step S16: depositing the interlayer dielectric layer and planarize, to fill the gap between the dummy gate.
Optionally, in the step S3, boundary layer and high k dielectric layer are sequentially depositing on the fin.
The present invention also provides a kind of semiconductor devices that above-mentioned method is prepared.
The present invention also provides a kind of electronic devices, including above-mentioned semiconductor devices.
In the present invention in order to solve the problems in the existing technology, a kind of semiconductor devices and its preparation side are provided
Method deposits high k dielectric layer, then depositing TiN layer in the method after removing the dummy gate on the fin
It is used as coating with TaN layers, the Si ion implantation is executed to the TiN layer before depositing the workfunction layers and is walked
Suddenly, to form TiSiN layers, for controlling coating for the diffusion of the conductive layer Al formed in subsequent step, simultaneously will
Multi-Vt (multi-Vt) is solved the problems, such as, in addition, the method can also be effectively reduced ion implanting screen effect
(IMP shadowing effect)。
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 is the preparation process schematic diagram of semiconductor devices described in the prior art；
Fig. 2 is the preparation process schematic diagram of heretofore described semiconductor devices；
Fig. 3 is the process flow chart for preparing semiconductor devices of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
The preparation method of semiconductor devices described in the prior art as shown in Figure 1, provide substrate 101, on substrate first
Form hard mask layer；Then, pattern the hard mask layer, formed for etching substrate be formed on fin it is multiple that
The exposure mask of this isolation；Then, substrate is etched to be formed on multiple fins 103；Then, deposition formed between multiple fins every
From structure；Finally, etching removes the hard mask layer.
Then dummy gate, and dielectric layer (not shown) are formed on the fin, it is described virtual to cover
Grid then removes the dummy gate, exposes the fin, and interlayer dielectric layer 104, height are sequentially depositing on the fin
K dielectric layer 105, coating 106,107 and workfunction layers 108, then execute ion implanting, due to workfunction layers
108 have biggish thickness, and the ion implanting gap very little between the fin, due to ion implanting screen effect for
The ion implanting of workfunction layers side wall is a very big challenge.
Embodiment 1
Semiconductor devices of the present invention and preparation method are described further below with reference to Fig. 2.
Step 201 is executed, semiconductor substrate 201 is provided and executes ion implanting, to form trap.
The semiconductor substrate 201 can be following at least one of the material being previously mentioned: silicon, insulation in this step
Silicon (SOI) on body is laminated silicon (SSOI), SiGe (S-SiGeOI), germanium on insulator SiClx is laminated on insulator on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..
Wherein the semiconductor substrate includes NMOS area and PMOS area, to form NMOS device in subsequent steps
And PMOS device.
Then pad oxide skin(coating) (Pad oxide) is formed in the semiconductor substrate 201, wherein the pad oxide skin(coating)
The forming method of (Pad oxide) can be formed by the method for deposition, such as the side such as chemical vapor deposition, atomic layer deposition
Method can also be formed by the surface of semiconductor substrate described in thermal oxide, and details are not described herein.
Further, the step of executing ion implanting can also be further included, in this step to serve as a contrast in the semiconductor
Trap is formed in bottom, wherein the ionic species and method for implanting that inject can be method commonly used in the art, herein not one by one
It repeats.
Then step 202 is executed, forms multiple fins 203 in semiconductor substrate 201, the width of fin is all identical,
Or fin is divided into multiple fins groups with different in width.
Specific forming method includes: that hard mask layer (not shown) is formed in semiconductor substrate 201, described in formation
The various suitable techniques that hard mask layer can be familiar with using those skilled in the art, such as chemical vapor deposition process, institute
Stating hard mask layer can be the oxide skin(coating) and silicon nitride layer being laminated from bottom to top；The hard mask layer is patterned, formation is used for
Etching semiconductor substrate 201 is to be formed on multiple exposure masks being isolated from each other of fin, in one embodiment, using from right
Patterning process described in quasi- double patterning (SADP) process implementing；Semiconductor substrate 201 is etched to be formed on fin structure.
Execute step 203, depositing isolation material layer 202, to cover the fin structure.
Specifically, as shown in Fig. 2, depositing isolation material layer 202, to be filled up completely the gap between fin structure.One
In a embodiment, the deposition is implemented using the chemical vapor deposition process with flowability.The material of spacer material layer 202
It can choose oxide, such as HARP.
Then spacer material layer 202 described in etch-back, until the object height of the fin.
Specifically, as shown in Fig. 2, spacer material layer 102 described in etch-back, with fin described in exposed portion, and then form
Fin with certain height.As an example, implement high annealing, so that spacer material layer 102 densifies, the high annealing
Temperature can be 700 DEG C -1000 DEG C；Chemical mechanical grinding is executed, until exposing the top of the hard mask layer；Described in removal
Silicon nitride layer in hard mask layer removes silicon nitride layer, the corruption of the wet etching using wet etching in one embodiment
Erosion liquid is diluted hydrofluoric acid；The oxide skin(coating) and part spacer material layer 102 in the hard mask layer are removed, to expose fin
The part of structure, and then the fin structure with certain height is formed, in one embodiment, being implemented using SiCoNi etching should
The etching gas of removal, the SiCoNi etching mainly has NH3And NF3。
Step 204 is executed, dummy gate is formed on the spacer material layer, to cover the fin.
Specifically, as shown in Fig. 2, depositing dummy gate material layer in this step, the dummy gate material layer can be with
Select semiconductor material commonly used in the art, such as polysilicon can be selected etc., it is not limited to it is a certain, herein no longer one by one
Enumerate,
The deposition method of the gate material layers can select the methods of chemical vapor deposition or atomic layer deposition.
Then the gate material layers are patterned, to form the dummy gate around the fin.
The dummy gate material layer is patterned, in this step to be formed around dummy gate, specifically, in the void
Photoresist layer is formed in quasi- gate material layers, then exposure development, to form opening, is then lost by exposure mask of the photoresist layer
The dummy gate material layer is carved, to be formed around dummy gate.
Optionally, dummy gate dielectric layer can also be further formed between the fin and the dummy gate.
Step 205 is executed, executes source and drain LDD injection, and in the two sides epitaxial growth of semiconductor material of the dummy gate
Layer, to form lifting source and drain.
Specifically, the common method of ability can be used in this step and execute source and drain LDD injection, details are not described herein.
Then in the two sides epitaxial growth SiC layer of the dummy gate in NMOS area, SiC source and drain is lifted to be formed
Pole.The SiC layer is formed using selective epitaxial growth (SEG) in the present invention, specifically, selects silicon-containing gas as raw material
Gas selects gas containing C as doping, reaction chamber is entered under the conveying of carrier gas, and then extension obtains the SiC layer.It is optional
Ground, SiC layer described in epitaxial growth while, can carry out doping (in-situ doped) in situ, can adulterate phosphorus or arsenic etc.,
Such as the gas containing phosphorus or arsenic is passed through while extension.
Likewise, in the two sides epitaxial growth SiGe of the dummy gate in the PMOS area, to form PMOS's
It is lifted source and drain.
Step 206 is executed, execute ion implanting step again and carries out rapid thermal annealing.
It can inhibit the depth and horizontal proliferation of impurity in the present invention in order to demonstrate,prove activator impurity again, execute the ion note
Rapid thermal annealing is carried out after entering, optionally, the rapid thermal annealing temperature is 1000-1050 DEG C.
Step 207 is executed, the interlayer dielectric layer is deposited and planarizes, to fill the gap between the dummy gate.
Specifically, it interlevel dielectric deposition and planarizes, planarizes described to interlayer dielectric layer to the dummy gate
Top.The non-limiting example of the planarization process includes mechanical planarization method and chemically mechanical polishing flattening method.
Step 208 is executed, the dummy gate is removed.
Specifically, the dummy gate is removed, groove is formed.The method of the removal can be photoetching and etching.It is losing
Gas used in the process of quarter includes HBr, is used as main etch gas；It further include the 02 or Ar as etching make-up gas,
Its quality that etching can be improved.
Step 209 is executed, gate interface layer 204, high k dielectric layer 205 are deposited.
Specifically, wherein the material of the high k dielectric layer 205 includes hafnium oxide, hafnium silicon oxide, nitrogen oxidation hafnium silicon, oxidation
Lanthanum, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc., it is especially excellent
Choosing is hafnium oxide, zirconium oxide or aluminium oxide.
It should be noted that can also form boundary layer 204 in the lower section of high k dielectric layer, constituent material includes silicon oxygen
Compound (SiOx), the effect for forming boundary layer is the interfacial characteristics improved between high k dielectric layer and semiconductor substrate.
Execute step 210, depositing TiN layer 206 and TaN layer 207 on the high k dielectric layer, as coating, and in institute
It states and executes the Si ion implantation step in TiN layer 206, to form TiSiN layers.
Specifically, coating is formed on the high k dielectric layer, constituent material includes titanium nitride and tantalum nitride, is formed
The effect of coating is diffusion of the metal material Al to high k dielectric layer prevented in metal gate structure, described is partly led with adjusting
The threshold voltage of body device.
In order to improve the regulation performance to threshold voltage, the Si ion implantation step is executed in the TiN layer 206,
To form TiSiN layers, Si ion implantation is executed before forming workfunction layers in the present invention, to increase ion implanting
Gap avoids ion implanting screen effect, further improves threshold so that being more easier to the ion implanting of the coating
Threshold voltage performance.
Step 211 is executed, forms workfunction layers, barrier layer and metallic aluminum material layer, on the coating with shape
At metal gates.
Specifically, PMOS workfunction layers, such as TiN are deposited first in this step；Then it removes in NMOS area
The PMOS workfunction layers, then the NMOS area deposit NMOS workfunction layers, such as TiAl etc..
So far, the introduction of the preparation process of the semiconductor devices of the embodiment of the present invention is completed.After the above step, also
It may include other correlation steps, details are not described herein again.Also, in addition to the foregoing steps, the preparation method of the present embodiment is also
It can include other steps among above-mentioned each step or between different steps, these steps can pass through the prior art
In various techniques realize that details are not described herein again.
In the present invention in order to solve the problems in the existing technology, a kind of semiconductor devices and its preparation side are provided
Method deposits high k dielectric layer, then depositing TiN layer in the method after removing the dummy gate on the fin
It is used as coating with TaN layers, the Si ion implantation is executed to the TiN layer before depositing the workfunction layers and is walked
Suddenly, to form TiSiN layers, for controlling coating for the diffusion of the conductive layer Al formed in subsequent step, simultaneously will
Multi-Vt (multi-Vt) is solved the problems, such as, in addition, the method can also be effectively reduced ion implanting screen effect
(IMP shadowing effect)。
Fig. 3 is the specifically semiconductor devices preparation flow figure described in embodiment of the present invention one, specifically includes:
Step S1: providing semiconductor substrate, is formed with several fins on the semiconductor substrate and around the fin
The dummy gate of piece is also formed with the interlayer dielectric for filling gap between the adjacent dummy gate on the semiconductor substrate
Layer；
Step S2: removing the dummy gate, to expose the fin；
Step S3: gate dielectric and coating are sequentially formed on the fin；
Step S4: executing Si ion implantation step, contains silicon covering layer to be formed.
Embodiment 2
The present invention also provides a kind of semiconductor devices, the semiconductor devices selects method preparation described in embodiment 1.
In the semiconductor devices to executing the Si ion implantation step in the TiN before depositing the workfunction layers,
To form TiSiN, therefore it can be very good the diffusion of control coating conductive layer Al, while multi-Vt will be solved
(multi-Vt) the problem of, can also effectively discharge ion implanting screen effect.
Embodiment 3
The present invention also provides a kind of electronic devices, including semiconductor devices as described in example 2.Wherein, semiconductor device
Part is semiconductor devices as described in example 2, or the semiconductor devices obtained according to preparation method described in embodiment 1.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the semiconductor devices.The electronic device of the embodiment of the present invention above-mentioned is partly led due to having used
Body device, thus there is better performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (9)
1. a kind of preparation method of semiconductor devices, comprising:
Step S1: providing semiconductor substrate, is formed with several fins on the semiconductor substrate and around the fin
Dummy gate is also formed with the interlayer dielectric layer for filling gap between the adjacent dummy gate on the semiconductor substrate；
Step S2: removing the dummy gate, to expose the fin；
Step S3: gate dielectric and coating are sequentially formed on the fin；
Step S4: executing Si ion implantation step, contains silicon covering layer to be formed；
Step S5: workfunction layers are formed on the coating；
Wherein, the shadowing effect that can reduce the workfunction layers ion implanting containing silicon covering layer.
2. the method according to claim 1, wherein in the step S3, the coating includes successively sinking
Long-pending TiN layer and TaN layer executes the Si ion implantation step, in the TiN layer to form TiSiN.
3. according to the method described in claim 2, it is characterized in that, the semiconductor substrate includes NMOS area and the area PMOS
Domain, wherein the step S5 includes:
Step S51: PMOS workfunction layers are deposited in the NMOS area and the PMOS area；
Step S52: the PMOS workfunction layers in the NMOS area are removed；
Step S53: NMOS workfunction layers are deposited in the NMOS area.
4. according to the method described in claim 2, it is characterized in that, the method still further comprises after the step S4
The step of forming barrier layer and metallic aluminum material layer, to form metal gates.
5. the method according to claim 1, wherein the step S1 includes:
Step S11: semiconductor substrate is provided and executes ion implanting, to form trap；
Step S12: patterning the semiconductor substrate, forms the fin；
Step S13: deposition dummy gate dielectric layer and dummy gate material layer simultaneously pattern, to form the dummy gate.
6. according to the method described in claim 5, it is characterized in that, the step S1 may further comprise:
Step S14: source and drain LDD injection, and the epitaxial semiconductor in the semiconductor substrate of dummy gate two sides are executed
Material layer, to form lifting source and drain；
Step S15: ion implanting is executed again, and carries out rapid thermal annealing；
Step S16: depositing the interlayer dielectric layer and planarize, to fill the gap between the dummy gate.
7. the method according to claim 1, wherein in the step S3, being sequentially depositing on the fin
Boundary layer and high k dielectric layer.
8. the semiconductor devices that method described in a kind of one of claim 1 to 7 is prepared.
9. a kind of electronic device, including semiconductor devices according to any one of claims 8.
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| US5899740A (en) * | 1997-03-04 | 1999-05-04 | Samsung Electronics Co., Ltd. | Methods of fabricating copper interconnects for integrated circuits |
| CN101189730A (en) * | 2004-03-31 | 2008-05-28 | 英特尔公司 | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
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| US8765588B2 (en) * | 2011-09-28 | 2014-07-01 | United Microelectronics Corp. | Semiconductor process |
| US8803254B2 (en) * | 2012-11-28 | 2014-08-12 | Globalfoundries Inc. | Methods of forming replacement gate structures for NFET semiconductor devices and devices having such gate structures |
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| US5899740A (en) * | 1997-03-04 | 1999-05-04 | Samsung Electronics Co., Ltd. | Methods of fabricating copper interconnects for integrated circuits |
| CN101189730A (en) * | 2004-03-31 | 2008-05-28 | 英特尔公司 | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
| CN104241142A (en) * | 2013-06-13 | 2014-12-24 | 三星电子株式会社 | Method of fabricating semiconductor device |
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