CN105680847B - An FPGA circuit and its design method - Google Patents
An FPGA circuit and its design method Download PDFInfo
- Publication number
- CN105680847B CN105680847B CN201610120404.3A CN201610120404A CN105680847B CN 105680847 B CN105680847 B CN 105680847B CN 201610120404 A CN201610120404 A CN 201610120404A CN 105680847 B CN105680847 B CN 105680847B
- Authority
- CN
- China
- Prior art keywords
- register
- output signal
- output
- multiple selector
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
The invention discloses a kind of FPGA circuitry and its design method, the circuit includes input-output unit, routing cell and configurable logic cell, and institute's routing cell includes the first multiple selector, and the configurable logic cell includes combinational logic circuit；The input terminal of first multiple selector is connect with the output end of the input-output unit, it is directly connected between the output end of first multiple selector and the input terminal of the combinational logic circuit by register circuit, by increasing by one register circuit of setting between the combinational logic circuit in the input-output unit and configurable logic cell, shorten the critical path between the register in input-output unit in register and configurable logic cell, reduce the delay between two registers, solves the technical issues of being unable to reach the design requirement for high-speed signal circuit design, realize the function that the timing of FPGA can be adjusted according to different design requirements, improve the maximum frequency of FPGA circuitry design.
Description
Technical field
The present invention relates to programmable integrated circuit design field, especially a kind of FPGA circuitry and its design method.
Background technique
FPGA (Field-Programmable Gate Array), i.e. field programmable gate array, it be PAL, GAL,
The product further developed on the basis of the programming devices such as CPLD.It is as one in the field specific integrated circuit (ASIC)
It plants semi-custom circuit and occurs, not only solved the deficiency of custom circuit, but also overcome original programming device gate circuit number to have
The shortcomings that limit.
In general, FPGA by partially forming as follows: input-output unit, configurable logic cell, internal storage unit,
Other resources such as global clock network unit, multiplier, interconnection resource (Routing Resource).Pass through above unit mould
Block, user can freely program functional circuit required for realization oneself.Meanwhile when being designed using FPGA, not only need
Meet the needs of function, many times needs to meet the design requirement of timing, such as: need to design a circuit design, and
And have strict requirements to the maximum frequency of design, but during being designed, in some places or on path
Different design close this minimum delay requirement, this when, generally require using the adjustment of flip_flop (trigger) resource come
Change the whole timing of the design.
For current FPGA resource, flip_flop only in input-output unit, the modules such as configurable logic cell,
Corresponding flip_flop resource is not present in routing resource.So shortest path is from a flip_flop when design
Other flip_flop is then arrived by routing.In this case, its delay be comprising from first flip_flop to
Between routing combinational logic delay t1 and routing delay t2 and routing to second flip_flop it
Between combinational logic postpone t3, these three parts.The path of introducing is relatively long, under normal circumstances, can satisfy needs, but
It is when encountering high speed signal, this structure may be unable to satisfy the demand of design.
Summary of the invention
The technical problem underlying that the present invention solves is: the present invention provides a kind of FPGA circuitry and design methods, solve
It is for design key path delay longer in existing FPGA design, it is unable to reach the design for high-speed signal circuit design
It is required that the technical issues of.
In order to solve the above technical problems, the invention adopts the following technical scheme:
The present invention provides a kind of FPGA circuitries, comprising: input-output unit, routing cell and configurable logic cell,
The routing cell includes the first multiple selector；The configurable logic cell includes combinational logic circuit；
The input terminal of first multiple selector is connect with the output end of the input-output unit, first multichannel
It is directly connected between the output end of selector and the input terminal of the combinational logic circuit by register circuit.
In another embodiment of the invention, the register circuit is set in the routing cell, the register
The input terminal of circuit is connect with the output end of first multiple selector, the output end of the register circuit and the combination
The input terminal of logic circuit connects.
In another embodiment of the invention, the routing cell further include: buffer unit and the second multiple selector；
The buffer cell for receiving the output signal of the first multiple selector output, and the output is believed
Number second multiple selector is sent to as the second output signal；
The register, for being sent to second multi-path choice for the output signal as the first output signal
Device；
Second multiple selector, for receiving selection signal, and when the selection signal is that instruction chooses described the
When the first selection signal of one output signal, described first is chosen from first output signal and second output signal
Output signal is sent to the combinational logic circuit；
It is defeated from described first when the selection signal is the second selection signal that second output signal is chosen in instruction
Second output signal, which is chosen, in signal and second output signal out is sent to the combinational logic circuit.
In another embodiment of the invention, the register is set in the configurable logic cell, and described first
The output signal of output is sent directly to the register in the configurable logic cell, the deposit by multiple selector
The output signal received is sent to the combinational logic circuit by device.
In another embodiment of the invention, the register is made of at least one trigger.
In order to solve the above-mentioned technical problem, the present invention also provides a kind of FPGA circuitry design method, the FPGA circuitries
Including input-output unit, routing cell and configurable logic cell, which comprises
First multiple selector is set on the routing cell, combinational logic is set on the configurable logic cell
Circuit；
Register circuit is set between first multiple selector and the combinational logic circuit, and by the deposit
The input terminal of device circuit is connect with the output end of the input-output unit, the output end of the register circuit and the combination
The input terminal of logic circuit connects.
In another embodiment of the invention, described by first multiple selector and the combinational logic circuit
Between setting register circuit include: that the register circuit is set in the routing cell, pass through register electricity
The output signal that first multiple selector exports is sent to the combinational logic circuit by road.
FPGA circuitry design method as claimed in claim 6, which is characterized in that described by being selected in first multichannel
It selects and register circuit is set between device and the combinational logic circuit further include: the register is set to described can configure and is patrolled
It collects in unit, the output signal of output is sent directly in the configurable logic cell by first multiple selector
Register, the output signal received is sent to the combinational logic circuit by the register.
In another embodiment of the invention, when the register to be set in the routing cell, further includes:
Buffer cell and the second multiple selector are set in the routing cell；
Receive the output signal of first multiple selector output by the buffer cell, and by the output signal
The second multiple selector is sent to as the second output signal；
The output signal is sent to second multiple selector by the register；
Second multiple selector receives selection signal selection for first output signal or the second output signal
It is sent to the combinational logic circuit.
In another embodiment of the invention, it is defeated by described first to receive selection signal selection for second multiple selector
Signal or the second output signal are sent to the combinational logic circuit and specifically include out:
It is defeated from described first when the selection signal is the first selection signal that first output signal is chosen in instruction
First output signal, which is chosen, in signal and second output signal out is sent to the combinational logic circuit；
It is defeated from described first when the selection signal is the first selection signal that first output signal is chosen in instruction
First output signal, which is chosen, in signal and second output signal out is sent to the combinational logic circuit.
Beneficial effects of the present invention:
The present invention provides a kind of FPGA circuitry and its design method, by the first multiple selector by input-output unit
Output signal is sent to the register circuit, and the output signal is sent to combinational logic circuit by the register circuit,
The output signal is transmitted directly to combinational logic circuit from input-output unit output end by setting register circuit, is made
It obtains to replace with the critical path by original input/output register to configurable logic cell register and be posted by input and output
Critical path of the storage to register circuit.
Further, the register circuit is to be arranged in routing cell, and such setting is so that critical path changes
For the register circuit from input-output unit directly into routing cell, namely being comparable to will be in configurable logic cell
Register is advanced in routing cell, so that the critical path between two registers is effectively shortened, also to effectively subtract
In the minimum delay for having lacked the critical path when designing circuit, further improve the clock frequency entirely designed.
Detailed description of the invention
Fig. 1 is a kind of FPGA circuitry structure chart that the embodiment of the present invention one provides；
Fig. 2 is another FPGA circuitry structure chart that the embodiment of the present invention one provides；
The signal path structural schematic diagram that FPGA circuitry designs in the case of Fig. 3 is common routing；
Fig. 4 is a kind of structural schematic diagram of the critical path for FPGA circuitry that the embodiment of the present invention one provides；
Fig. 5 is the particular circuit configurations figure of the critical path of FPGA circuitry provided by Fig. 4；
Fig. 6 is a kind of flow chart of FPGA circuitry design method provided by Embodiment 2 of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiment is a part of the embodiment in the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Central scope of the invention is: the adjustment due to existing FPGA circuitry structure for realization timing, only logical
The register crossed in input-output unit and configurable logic cell is realized, and for existing FPGA, is also only had
There are registers for input-output unit and the two parts of configurable logic cell, and there is no there is deposit in routing cell
Device, therefore, if wanting to carry out circuit design by existing FPGA, and when having related high requirement to the clock frequency of design,
It can only be adjusted on input-output unit and configurable logic cell, and can not achieve timing in routing cell part
Adjustment, therefore, causing entire design still can also have biggish delay.
The present invention provides a kind of FPGA circuitry and its design method, the circuit includes: input-output unit, wiring list
Member and configurable logic cell, the routing cell include the first multiple selector；The configurable logic cell includes combination
Logic circuit；It is reduced by carrying out the design of register circuit between the input-output unit and configurable logic cell
The delay of critical path is deposited specifically by increasing setting one between the input-output unit and combinational logic circuit
Further the register circuit is arranged in the routing cell for device circuit, and critical path is defeated by original input
Register replaces with input/output register to routing cell register to configurable logic cell register out, and the input is defeated
Unit sends a signal to the first multiple selector out, and first multiple selector receives the input-output unit output
Output signal, and the output signal is sent to from the output end of first multiple selector by the register circuit
The combinational logic circuit, when carrying out circuit design so as to shorten routing cell, input-output unit register and configurable
Critical path between logic unit register, effectively reduces path delay.
Below by specific embodiment combination attached drawing, invention is further described in detail.
Embodiment one:
In view of existing FPGA circuitry setting critical path delay is too long, set so as to cause high-speed signal circuit is not achieved
The technical issues of design requirement of meter, present embodiments provides the circuit of FPGA a kind of, the circuit include: input-output unit,
Routing cell and configurable logic cell, the routing cell include the first multiple selector, the configurable logic cell packet
Include combinational logic circuit；The input terminal of first multiple selector is connect with the output end of the input-output unit, described
It is directly connected between the output end of first multiple selector and the input terminal of the combinational logic circuit by register circuit.
Referring to FIG. 1, Fig. 1 illustrates a kind of FPGA circuitry, including input-output unit 11, routing cell 12 and configurable
Logic unit 13, the routing cell 12 include the first multiple selector 121 and register circuit 122, the configurable logic
Unit 13 includes combinational logic circuit 131, and first multiple selector 121 and the output end of the input-output unit 11 connect
It connects, and first multiple selector 121 receives the multiple signals exported from the input-output unit 11 as institute
Multiple input signals of the first multiple selector 121 are stated, first multiple selector 121 is selected from the multiple input signal
An input signal is taken to be sent to the register circuit 122 as the first output signal, further, in the present embodiment,
First multiple selector 121 can be believed by the register circuit 122 using the output signal as the first output again
Number it is directly transferred to the combinational logic circuit 131.
In the present embodiment, another FPGA circuitry structure is additionally provided, as shown in Figure 1, in the cloth of the FPGA circuitry
Line unit 12 is additionally provided with buffer cell 123 and the second multiple selector 124, the input terminal of the buffer cell 123 with it is described
The output end of first multiple selector 121 connects, the output end of the buffer cell 123 and second multiple selector 124
First input end connection, the buffer cell 123 forms second signal transmission path with second multiple selector 124；
The register circuit 122 forms the first signal transmission path with second multiple selector 124；
In the present embodiment, the buffer cell 123 can also be used to the intensity of the output signal of amendment input, guarantee letter
Number be capable of complete and accurate is output to other parts；The buffer cell 123 receives it from first multiple selector 121
The output signal of output, and second multiple selector 124 is sent to using the output signal as the second output signal；Institute
Register circuit 122 is stated to send out the output signal received from first multiple selector 121 as the first output signal
It send to the second input terminal of second multiple selector 124；Then second multiple selector is controlled by selection signal
What 124 selections were exported first multiple selector 121 using the first signal transmission path or second signal transmission path
First output signal is sent on the combinational logic circuit 131 in the configurable logic cell 13.
The present embodiment provides in FPGA circuitry, when the selection signal that second multiple selector 124 receives is to refer to
(the first signal transmission path has in other words been selected) when showing the first selection signal for choosing first output signal, from described
First output signal, which is chosen, in the first output signal and the second output signal received is sent to the configurable logic
On combinational logic circuit 131 in unit 13.
When the selection signal that second multiple selector 124 receives is the second choosing that the second output signal is chosen in instruction
(second signal transmission path has in other words been selected) when selecting signal, has been exported from first output signal received and second
It is chosen in signal on the combinational logic circuit 131 that second output signal is sent in the configurable logic cell 13.
Preferably, as shown in Figure 1, second multiple selector 124 is that two-way inputs No. two selectors exported all the way,
(it that is to say received selection signal for first choice letter when the enable end SC_BYPASS of No. two selector is not enabled
Number), first output signal passes through from first signal transmission path, that is to say and leads to from the register circuit 122
It crosses, to realize the improvement function of carrying out timing in routing cell 12, that is to say that realize can also by routing cell 12
To carry out the adjustment in path delay.
As shown in Fig. 2, the register circuit 122 can also be that setting exists in FPGA circuitry provided in this embodiment
In the configurable logic cell 13；It is described when the register circuit is arranged in the configurable logic cell 13
First multiple selector 121 receives the multiple input signals inputted by the input-output unit, and believes from the multiple input
An input signal is chosen in number, and the register in the configurable logic cell 13 is sent directly to as the first output signal
On circuit 122.
In the present embodiment, regardless of the register circuit is arranged in routing cell 12 or configurable logic cell
In 13, the effect for shortening signal path can be achieved；As shown in figure 3, the FPGA for common routing carries out circuit design
Signal path structural schematic diagram, critical path (critical path) are generally made of four parts, two register circuits 31 with
Routing cell 32 and combinational logic circuit 33 are clipped between 34.In order to guarantee that design can reach frequency big as far as possible, generally
It is time and T1 of the register circuit 31 to be reduced to the greatest extent with the delay of both register circuits 34.If utilizing general wiring
If unit, the minimum delay is T1=multiple selector+buffer cell+routing cell+combinational logic, produced by this four parts
Delay.
As shown in figure 4, for the present embodiment provides the structural schematic diagrams of the critical path of FPGA circuitry, including register circuit
41 and routing cell 42.Specific circuit structure as shown in figure 5, the routing cell 42 include: the first multiple selector 421,
Buffer cell 422, the second multiple selector 423 and register circuit 424, wherein first multiple selector 421, buffering
Unit 422 and the second multiple selector 423 are in turn connected to form second signal transmission path (Path2) respectively；More than described first
Road selector 421, the second multiple selector 423 and register circuit 424 are in turn connected to form the first signal transmission path respectively
(Path1).It can thus be seen that being added when critical path by the way that the enable end SC_BYPASS of the second multiple selector is arranged to control
Enter the register circuit 424 in routing cell 42, so as to obtain, the minimum delay T2=multiple selector of the FPGA circuitry
+ routing cell, the delay that this two parts generates.According to the comparison of T1 and T2 it is found that T2 is significantly less than T1.
In FPGA circuitry provided in this embodiment, the register circuit is made of at least one trigger, certainly
The DATA REG circuitry being also possible on FPGA.
Embodiment two:
Fig. 6 is a kind of flow chart of FPGA circuitry design method provided in this embodiment, please refers to Fig. 6:
The first multiple selector is arranged in S601 on the routing cell, the setting group on the configurable logic cell
Combinational logic circuit；
S602, is arranged register circuit between first multiple selector and the combinational logic circuit, and by institute
The input terminal for stating register circuit is connect with the output end of the input-output unit, the output end of the register circuit and institute
State the input terminal connection of combinational logic circuit.
In the present embodiment, the register circuit is specially and is made of at least one trigger, or directly uses
The DATA REG circuitry of FPGA.
In the present embodiment, the register circuit being arranged by the design method is specially that one is arranged on routing cell
A register circuit, the routing cell further include the first multiple selector, by the register circuit by more than described first
The output signal of road selector output is sent to the combinational logic circuit, and first multiple selector is received by the input
Multiple input signals of output unit input, and an input signal is chosen as output signal from the multiple output signal
Point is sent to the register circuit, and the register circuit is used to receive the first output of the first multiple selector output
Signal is sent to the configurable logic cell.
In the present embodiment, when the register circuit is arranged in the routing cell, further includes: in the wiring
Buffer cell and the second multiple selector are set in unit；
Receive the output signal of first multiple selector output by the buffer cell, and by the output signal
The second multiple selector is sent to as the second output signal；
The output signal is sent to second multiple selector by the register；
Second multiple selector receives selection signal selection for first output signal or the second output signal
It is sent to the combinational logic circuit.
Second multiple selector receives selection signal selection for first output signal or the second output signal
The combinational logic circuit is sent to specifically include:
It is defeated from described first when the selection signal is the first selection signal that first output signal is chosen in instruction
First output signal, which is chosen, in signal and second output signal out is sent to the combinational logic circuit；
It is defeated from described first when the selection signal is the first selection signal that first output signal is chosen in instruction
First output signal, which is chosen, in signal and second output signal out is sent to the combinational logic circuit.
In the present embodiment, the register can also be set to by the design method by the configurable logic list
In member, the output signal of output is sent directly to posting in the configurable logic cell by first multiple selector
The output signal received is sent to the combinational logic circuit by storage, the register.Preferably, the register
Circuit can pass through the first multi-path choice in the routing cell directly using the register in the configurable logic cell
The signal that the input-output unit exports is sent directly on the combinational logic circuit by device, to reach shortening circuit
The design requirement of routing path, reducing in circuit design is the delay time of critical path.
In conclusion implementation through the invention, at least exist it is following the utility model has the advantages that
The present invention provides a kind of FPGA circuitry and its design method, the circuit includes input-output unit, wiring list
Member and configurable logic cell, institute's routing cell include the first multiple selector, and the configurable logic cell includes that combination is patrolled
Collect circuit；The input terminal of first multiple selector is connect with the output end of the input-output unit, first multichannel
It is directly connected between the output end of selector and the input terminal of the combinational logic circuit by register circuit, by inputting
Increase by one register circuit of setting between the register in register and configurable logic cell in output unit, by posting
The first output signal that first multiple selector exports is sent directly in the combinational logic circuit by latch circuit, excellent
Choosing, the register circuit is to be arranged in routing cell, therefore, the critical path of the method setting provided through the invention
Input/output register is replaced with to configurable logic cell register by original input/output register to post to routing cell
Storage, critical path delay are reduced, and are realized the timing that can adjust FPGA according to different design requirements, are improved design
Maximum frequency, increase improvement of the entire FPGA to timing function.
The above content is specific embodiment is combined, further detailed description of the invention, and it cannot be said that this hair
Bright specific implementation is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, it is not taking off
Under the premise of from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to protection of the invention
Range.
Claims (10)
1. a kind of FPGA circuitry characterized by comprising input-output unit, routing cell and configurable logic cell, it is described
Routing cell includes the first multiple selector；The configurable logic cell includes combinational logic circuit；
The input terminal of first multiple selector is connect with the output end of the input-output unit, first multi-path choice
It is directly connected between the output end of device and the input terminal of the combinational logic circuit by register.
2. FPGA circuitry as described in claim 1, which is characterized in that the register is set in the routing cell, institute
The input terminal for stating register is connect with the output end of first multiple selector, the output end of the register and the combination
The input terminal of logic circuit connects.
3. FPGA circuitry as claimed in claim 2, which is characterized in that the routing cell further include: buffer cell and second
Multiple selector；
The buffer cell for receiving the output signal of the first multiple selector output, and the output signal is made
Second multiple selector is sent to for the second output signal；
The register, for being sent to second multiple selector for the output signal as the first output signal；
Second multiple selector, for receiving selection signal, and when the selection signal is that instruction selection described first is defeated
Out when the first selection signal of signal, first output is chosen from first output signal and second output signal
Signal is sent to the combinational logic circuit；
When the selection signal is the second selection signal that second output signal is chosen in instruction, from the first output letter
Number and second output signal in choose second output signal and be sent to the combinational logic circuit.
4. FPGA circuitry as described in claim 1, which is characterized in that the register is set to the configurable logic cell
In, the output signal of output is sent directly to the register in the configurable logic cell by first multiple selector,
The output signal received is sent to the combinational logic circuit by the register.
5. FPGA circuitry according to any one of claims 1-4, which is characterized in that the register is by least one trigger
Composition.
6. a kind of FPGA circuitry design method, the FPGA circuitry includes input-output unit, routing cell and configurable logic
Unit, which is characterized in that the described method includes:
First multiple selector is set on the routing cell, combinational logic electricity is set on the configurable logic cell
Road；
Register is set between first multiple selector and the combinational logic circuit, and by the input of the register
It holds and is directly connected to the output end of first multiple selector, by the output end of the register and the combinational logic circuit
Input terminal be directly connected to；And the output end of the input terminal of first multiple selector and the input-output unit is connected
It connects.
7. FPGA circuitry design method as claimed in claim 6, which is characterized in that it is described first multiple selector with
It includes: that the register is set in the routing cell that register is arranged between the combinational logic circuit, by described
The output signal that first multiple selector exports is sent to the combinational logic circuit by register.
8. FPGA circuitry design method as claimed in claim 6, which is characterized in that it is described first multiple selector with
Register is set between the combinational logic circuit further include: the register is set in the configurable logic cell,
The output signal of output is sent directly to the register in the configurable logic cell by first multiple selector, described
The output signal received is sent to the combinational logic circuit by register.
9. FPGA circuitry design method as claimed in claim 7, which is characterized in that when the register is set to the cloth
When in line unit, further includes: buffer cell and the second multiple selector are set in the routing cell；
Receive the output signal of first multiple selector output by the buffer cell, and using the output signal as
Second output signal is sent to the second multiple selector；
The output signal is sent to second multiple selector by the register；
Second multiple selector receives selection signal selection and sends first output signal or the second output signal
To the combinational logic circuit.
10. FPGA circuitry design method as claimed in claim 9, which is characterized in that second multiple selector receives choosing
It selects signal behavior first output signal or the second output signal is sent to the combinational logic circuit and specifically include:
When the selection signal is the first selection signal that first output signal is chosen in instruction, from the first output letter
Number and second output signal in choose first output signal and be sent to the combinational logic circuit；
When the selection signal is the second selection signal that second output signal is chosen in instruction, from the first output letter
Number and second output signal in choose second output signal and be sent to the combinational logic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610120404.3A CN105680847B (en) | 2016-03-03 | 2016-03-03 | An FPGA circuit and its design method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610120404.3A CN105680847B (en) | 2016-03-03 | 2016-03-03 | An FPGA circuit and its design method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105680847A CN105680847A (en) | 2016-06-15 |
| CN105680847B true CN105680847B (en) | 2019-02-12 |
Family
ID=56306613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610120404.3A Active CN105680847B (en) | 2016-03-03 | 2016-03-03 | An FPGA circuit and its design method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105680847B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0707382A2 (en) * | 1994-09-20 | 1996-04-17 | Xilinx, Inc. | Circuit for fast carry and logic |
| CN102541707A (en) * | 2010-12-15 | 2012-07-04 | 中国科学院电子学研究所 | Multiplex JTAG (Joint Test Action Group) interface-based FPGA (Field Programmable Gate Array) on-chip logic analyzer system and method |
| CN104424367A (en) * | 2013-08-22 | 2015-03-18 | 京微雅格（北京）科技有限公司 | Technological mapping method and integrated circuit for optimizing register control signal |
| CN205068374U (en) * | 2014-10-01 | 2016-03-02 | 吉林克斯公司 | A circuit for processing data in integrated equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6014038A (en) * | 1997-03-21 | 2000-01-11 | Lightspeed Semiconductor Corporation | Function block architecture for gate array |
-
2016
- 2016-03-03 CN CN201610120404.3A patent/CN105680847B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0707382A2 (en) * | 1994-09-20 | 1996-04-17 | Xilinx, Inc. | Circuit for fast carry and logic |
| CN102541707A (en) * | 2010-12-15 | 2012-07-04 | 中国科学院电子学研究所 | Multiplex JTAG (Joint Test Action Group) interface-based FPGA (Field Programmable Gate Array) on-chip logic analyzer system and method |
| CN104424367A (en) * | 2013-08-22 | 2015-03-18 | 京微雅格（北京）科技有限公司 | Technological mapping method and integrated circuit for optimizing register control signal |
| CN205068374U (en) * | 2014-10-01 | 2016-03-02 | 吉林克斯公司 | A circuit for processing data in integrated equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105680847A (en) | 2016-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Zeferino et al. | SoCIN: a parametric and scalable network-on-chip | |
| CN107005241A (en) | Mixed radix and/or mixed mode switch matrix architectural framework and integrated circuit, and the method for operating it | |
| CN201409126Y (en) | Clock synchronous circuit in serialization of high-speed parallel data | |
| US20100306429A1 (en) | System and Method of Signal Processing Engines With Programmable Logic Fabric | |
| CN101808032A (en) | Static XY routing algorithm-oriented two-dimensional grid NoC router optimization design method | |
| CN110569596B (en) | Hybrid clock tree structure for system-on-chip | |
| CN110399317A (en) | A kind of multifunctional controller that the software of embedded system is adaptive | |
| KR102571068B1 (en) | Optional provision of clock signals using programmable control circuitry | |
| CN104424367B (en) | A process mapping method and integrated circuit for optimizing register control signals | |
| CN109981084A (en) | Burst pulse output system and method based on FPGA | |
| CN109905116A (en) | Programmable Pipeline interface circuit | |
| CN107957967A (en) | Configuration through high speed serialization link | |
| CN105827217B (en) | One kind having limit for length's impulse response filter circuit and programmable logic device | |
| CN114330191A (en) | Signal multiplexing transmission method and device | |
| CN104796343A (en) | Communication structure based on network-on-chip | |
| CN106960087B (en) | Clock distribution network structure and generation method thereof | |
| CN105680847B (en) | An FPGA circuit and its design method | |
| CN110018654A (en) | Fine granularity programmable timing sequence control logic module | |
| CN101867376A (en) | Clock synchronous circuit | |
| Lee et al. | A high-speed and decentralized arbiter design for NoC | |
| CN107425844A (en) | A kind of configurable clock buffer suitable for SRAM type FPGA | |
| CN105629803B (en) | FPGA logic cell with feedback path | |
| Singh et al. | Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip | |
| CN204794927U (en) | Super large time delay volume element circuit | |
| CN105471422B (en) | Programmable logic module with integrated auxiliary logic operation unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 518057 Guangdong city of Shenzhen province Nanshan District high tech Industrial Park Road eight South South technology Howare Technology Building 16 Applicant after: SHENZHEN PANGO MICROSYSTEMS Co.,Ltd. Address before: 518057 Guangdong city of Shenzhen province Nanshan District high tech Industrial Park Road eight South South technology Howare Technology Building 16 Applicant before: Shenzhen Tongchuang Guoxin Electronics Co.,Ltd. |
|
| COR | Change of bibliographic data | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 518000 Guowei R & D building 401, No.015, Gaoxin South 1st Road, high tech Zone community, Yuehai street, Nanshan District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Ziguang Tongchuang Electronics Co.,Ltd. Country or region after: China Address before: 16th Floor, Haowei Technology Building, Science and Technology South Eighth Road, Nanshan District, Shenzhen, Guangdong Province, China Patentee before: SHENZHEN PANGO MICROSYSTEMS Co.,Ltd. Country or region before: China |