[go: up one dir, main page]

CN105122445A - 不具有tsv结构的低cte中介片和方法 - Google Patents

不具有tsv结构的低cte中介片和方法 Download PDF

Info

Publication number
CN105122445A
CN105122445A CN201480022444.3A CN201480022444A CN105122445A CN 105122445 A CN105122445 A CN 105122445A CN 201480022444 A CN201480022444 A CN 201480022444A CN 105122445 A CN105122445 A CN 105122445A
Authority
CN
China
Prior art keywords
sealant
cte
layer
dielectric regions
microelectronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201480022444.3A
Other languages
English (en)
Other versions
CN105122445B (zh
Inventor
C·沃伊奇克
C·E·尤佐
M·纽曼
T·卡斯基
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vertical Circuits Inc
Original Assignee
Vertical Circuits Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vertical Circuits Inc filed Critical Vertical Circuits Inc
Publication of CN105122445A publication Critical patent/CN105122445A/zh
Application granted granted Critical
Publication of CN105122445B publication Critical patent/CN105122445B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/809—Constructional details of image sensors of hybrid image sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/018—Manufacture or treatment of image sensors covered by group H10F39/12 of hybrid image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/804—Containers or encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

提供了一种微电子组件，包括介电区域、多个导电元件、密封剂和微电子元件。密封剂的热膨胀系数(CTE)可以不大于与介电区域或微电子元件中的至少一个相关联的CTE的两倍。

Description

不具有TSV结构的低CTE中介片和方法
技术领域
本公开涉及微电子器件的封装，尤其涉及半导体器件的封装。
背景技术
微电子器件通常包括半导体材料(诸如硅或砷化镓)的板(slab)，其通常称为裸片或半导体芯片。半导体芯片通常设置为独立的预封装单元。在一些单元设计中，半导体芯片被安装至衬底或芯片载体，衬底或芯片载体又安装在诸如印刷电路板的电路板上。
在半导体芯片的第一面(例如，前表面)中制造有源电路装置。为了利于到有源电路装置的电连接，芯片在同一面上设置有接合焊盘。接合焊盘通常在裸片的边缘周围或者对于许多存储器件来说在裸片中心中以规则阵列进行放置。接合焊盘通常由导电金属(诸如铜或铝)制造为大约0.5微米(μm)厚。接合焊盘可以包括单个金属层或多个金属层。接合焊盘的尺寸将随着器件类型而变化，但是通常在一侧测量为几十到几百微米。
中介片可用于在微电子元件(诸如一个或多个彼此未封装或封装半导体芯片)之间或者在一个或多个未封装或封装半导体芯片与其他部件(诸如其上具有无源电路元件的芯片上集成无源器件(“IPOC”)、分立无源器件(例如，电容器、电阻器或电感器或它们的组合))之间提供电连接，但不限于此。中介片可以将这种芯片或多个芯片与诸如电路板的其他结构耦合。
尺寸是芯片的任何物理布置中的重要考虑因素。随着便携式电子设备的快速发展，对于芯片的更紧凑物理布置的需求变得越来越强烈。仅通过示例，通常被称为“智能手机”的设备将蜂窝电话的功能与强有力的数据处理器、存储器和辅助设备(诸如全球定位系统接收器、电子相机和局域网连接)以及高分辨率显示器和相关联的图像处理芯片进行集成。这种设备可以在封装件大小的设备中提供诸如全因特网连接、娱乐(包括全分辨率视频)、导航、电子银行等的能力。复杂的便携式设备要求将多个芯片封装到小空间中。此外，一些芯片具有许多输入和输出连接，通常称为“I/O”。这些I/O必须与其他芯片的I/O互连。互连应该短且应该具有低阻抗以使得信号传播延迟最小。来自互连的部件不应该显著增加组件的尺寸。在其他应用中也存在类似需求，例如诸如在因特网搜索引擎中所使用的数据服务器中。例如，在复杂芯片之间提供大量短且低阻抗互连的结构可以增加搜索引擎的带宽并降低其功耗。
尽管在中介片结构和制造中所取得的进步，还可以进行进一步的改进以增强用于制造可从工艺中得到的中介片和结构的这种工艺。
发明内容
本发明的一个方面可提供一种微电子组件，包括：介电区域，具有第一表面、与第一表面相对的第二表面以及多条迹线和多个接触件，多条迹线在平行于第一表面和第二表面的至少一个方向上延伸，多个接触件位于介电区域的第一表面处；多个导电元件，耦合至迹线并在第二表面上方突出；密封剂，在第二表面上方延伸，密封剂填充相邻导电元件之间的空间并具有上覆且背对第二表面的表面，其中导电元件的端部位于密封剂的表面处；微电子元件，具有一表面和位于该表面处的多个元件接触件，元件接触件面对并接合至多个接触件，其中密封剂的热膨胀系数(CTE)不大于与介电区域或微电子元件中的至少一个相关联的CTE的两倍。
在一个示例中，密封剂可以是第一密封剂，微电子组件还包括在第一表面上方延伸的第二密封剂。
在一个示例中，第二密封剂的CTE可等于第一密封剂的CTE。
在一个示例中，第一密封剂和第二密封剂可密封介电区域。
在一个示例中，微电子元件可包括在平行于第一表面的至少一个方向上隔开的至少两个微电子元件。
在一个示例中，介电区域可包括第一介电材料的第一层和被配置为用作工艺停止层的不同介电材料的第二层。
在一个示例中，多个导电元件包括选自由焊料、锡、铟、铜、镍、金、共晶成分、非共晶成分和导电基质材料组成的组中的接合材料的至少一块。
在一个示例中，多个导电元件可包括具有主要由选自铜、铜合金、镍和镍合金的至少一种金属组成的至少一个核心的多个金属柱，柱具有高于300℃的熔化温度。
在一个示例中，微电子组件还可以包括电路板，其中多个导电元件与位于电路板的表面处的对应接触件接合。
在一个示例中，介电层选自由后端制程(BEOL)和再分布层(RDL)组成的组。
本公开的另一方面可以提供上述微电子组件以及电连接至结构的一个或多个其他电子部件。
在一个示例中，该系统还可以包括壳体，微电子组件和其他电子部件安装至所述壳体。
本公开的另一方面可以提供一种中介片，包括：介电区域，具有第一表面、与第一表面相对的第二表面以及多条迹线和多个接触件，多条迹线在平行于第一表面和第二表面的至少一个方向上延伸，多个接触件位于介电区域的第一表面处；多个导电元件，耦合至迹线并在第二表面上方突出；密封剂，在第二表面上方延伸，密封剂填充相邻导电元件之间的空间并具有上覆且背对第二表面的表面，其中导电元件的端部位于密封剂的表面处，其中密封剂的热膨胀系数(CTE)不大于与至少介电区域或微电子元件相关联的CTE的两倍，微电子元件具有被配置用于与第一表面处的接触件的倒装连接的接触件。
在一个示例中，第二密封剂的CTE可等于第一密封剂的CTE。
在一个示例中，介电区域可包括第一介电材料的第一层和被配置为用作工艺停止层的不同介电材料的第二层。
在一个示例中，多个导电元件可包括选自由焊料、锡、铟、铜、镍、金、共晶成分、非共晶成分和导电基质材料组成的组中的接合材料的至少一块。
在一个示例中，多个导电元件可包括具有主要由选自铜、铜合金、镍和镍合金的至少一种金属组成的至少一个核心的多个金属柱，柱具有高于300℃的熔化温度。
在一个示例中，介电层可选自由后端制程(BEOL)和再分布层(RDL)组成的组。
本公开的另一方面可以提供一种制造微电子组件的方法，包括：形成填充设置在支持结构上的介电区域的第二表面上方向上突出的相邻导电元件之间的空间，其中与导电元件电连接的多条迹线在平行于第一表面和第二表面的至少一个方向上延伸，密封剂具有上覆且背对第二表面的表面，其中导电元件的端部位于密封剂的表面处；在朝向介电区域的第一表面的方向上去除支持结构的厚度的至少一部分；组装具有一面和位于该面处的多个元件接触件的微电子元件，使得元件接触件面对并接合至多个接触件，其中密封剂的热膨胀系数(CTE)不大于与介电区域或微电子元件中的至少一个相关联的CTE的两倍。
在一个示例中，该方法可进一步包括：在组装微电子元件之后，去除密封剂的表面处的密封剂的一部分，从而去除密封剂的表面处的导电元件的部分。
在一个示例中，该方法可进一步包括：在去除密封剂的一部分之后，将多个接合元件附接至表面处的导电元件的部分，接合元件被配置为与第二部件的表面处的多个接触件接合。
在一个示例中，密封剂可以是第一密封剂，该方法进一步包括形成第二密封剂，第二密封剂在第一表面上方延伸，第二密封剂的CTE等于第一密封剂的CTE。
在一个示例中，该方法可进一步包括：在组装具有介电区域的微电子元件之后，在微电子元件与介电区域的第一表面相对的表面处研磨微电子元件，以去除微电子元件的厚度的至少一部分。
在一个示例中，微电子元件可包括多个微电子元件。
在一个示例中，该方法可进一步包括：将多个导电元件与电路板的表面处的对应接触件接合。
在一个示例中，集成形成支持结构和介电区域。
在一个示例中，支持结构可主要由第一材料组成，并且介电区域可主要由第二材料组成。
在一个示例中，该方法可进一步包括：沉积工艺停止层；以及利用工艺停止层停止去除工艺。
附图说明
图1是示出包括中介片的微电子组件的制造阶段的截面图；
图2是介电区域的放大截面图；
图3是示出包括中介片的微电子组件的制造阶段的截面图；
图4是示出包括中介片的微电子组件的制造阶段的截面图；
图5是示出包括中介片的微电子组件的制造阶段的截面图；
图6是示出包括中介片的微电子组件的制造阶段的截面图；
图7是示出包括中介片的微电子组件的制造阶段的截面图；
图8是示出包括中介片的微电子组件的制造阶段的截面图；
图9是示出包括中介片的微电子组件的制造阶段的截面图；以及
图10是示出包括微电子组件的系统的截面图。
具体实施方式
图1示出了根据本公开的方面的包括中介片的微电子组件的制造方法中的阶段。如图1所示阶段的所示，介电区域110被设置在厚度为T的支持元件或支持结构上方。支持结构105可以由任何材料形成，并且在一些示例中可以由硅、模制材料、玻璃衬底或除上述材料之外的任何附加材料形成。典型地，介电区域110形成在支持结构105的上方。例如，介电区域110可以具有第一表面110a和与第一表面110a相对的第二表面110b。在一个示例中，第一表面110a可以限定为介电区域110与支持结构105的界面。在其他示例中，介电区域110可以集成设置有支持结构105，并且在一些情况下可以由相同的介电材料形成，使得第一表面110a不存在直到稍后的制造过程。
图2是示出介电区域110和其上支持的迹线和互连件的集合的放大截面图。介电区域110可以支持一个或多个布线层以及相关联的互连结构，诸如包括在后端制程(“BEOL”)结构中的通孔或再分布结构。例如，介电区域110可以包括多个介电层111、112和114以及嵌入到介电层111、112和114中的一个或多个中的多条迹线113(例如，布线层)。迹线113可以在任何方向上延伸，并且可以相对于介电区域110的表面110a、110b以平行、垂直或任何其他方向延伸。
当介电区域110是BEOL区域时，其可以具有近似为50纳米至10微米的厚度T。在其他示例中，介电区域可以是或者包括再分布层(RDL)，其具有更大厚度T且其上迹线113在平行于表面110a的方向上的宽度可以例如在20纳米到20微米的范围内。
介电层111可以是任何类型的介电层，诸如焊料掩模。在其他示例中，介电区域110可以不包括介电层111。介电层112也可以是任何类型的介电层，并且在一个示例中可以包括硅的氧化物。介电层114可以是任何类型的介电层，并且在一个示例中其可以是抛光停止、研磨停止或其他工艺停止层，当在支持结构105的研磨、打磨或抛光期间遇到时，其在一个示例中可以使得这些工艺停止或迅速减慢。例如当介电层包括氧化硅时，这种层可以包括或者由硅的氮化物制成。在一个示例中，工艺停止层可以是在到达这种层时可被工艺设备使用(诸如用于检测工艺的端点)的端点层或端点检测层。
在一个示例中，介电层111和112以及介电区域110的迹线113可以形成在介电层114上方。例如通过在支持结构105上方沉积介电层114，介电层114(例如，抛光停止、研磨停止或其他工艺停止层)本身可以形成在支持结构105上方。
一个或多个导电元件115可以设置为从介电区域110的第二表面110b上方突出。如本文所使用的，“上方”和“向上”不是指重力参考系，而是可以表示垂直远离表面的方向。在一个示例中，如图2所示，导电元件115可以包括导电块(例如，焊球)，其可以在表面110b处附接至诸如金属焊盘116的导电元件。如本文所使用的，术语“在…处”可以包括可用于连接的元件位于表面处、以及可以与表面平齐、凹陷在表面内或者在表面上方突出。例如，焊盘116可以在平行于表面110b的方向上具有近似2微米至100微米的尺寸。例如，导电元件115可以包括接合材料(诸如焊料、锡、铟、铜、镍、金、共熔合金、非共熔合金和导电基质材料)的至少一块。在另一示例中，如图2所示，导电元件可以是柱115a，诸如可以通过在焊盘上镀金属或者可选地通过设置金属层(诸如铜、铜合金、镍或镍合金或这些金属的组合)然后蚀刻该金属层以形成柱115a来形成。当通过蚀刻形成时，柱115a可以具有例如如图2所示的截锥形状。导电元件115可以为上述焊球和柱的任何组合以及其他类型的导电元件。以这种方式，导电元件115可以包括主要由至少一种金属(选自由铜、铜合金、镍或镍合金组成的组)组成的核心，这种柱具有高于300℃的熔化温度。
可以在介电区域110的第一表面110a处设置多个接触件110a1。在一个示例中，如以下更详细描述的，接触件110a1可以包括微凸块接触件，用于连接至一个或多个微电子元件。
在所示结构中，一个或多个接触件110a1可以通过迹线113与导电元件115或导电元件115a中的一个或多个电耦合。接触件110a1、导电元件115和迹线113可以根据任何期望的结构进行配置，使得可以实现导电元件和接触件110a1之间的互连件的任何期望结构。
应该理解，接触件110a1可以定位在表面110a处以具有最小间距，其与设置在介电区域110的与第一表面相对的第二表面110b处的导电元件115或115a的最小间距相同或不同。在具体示例中，导电元件115的最小间距可以按照大于1:1的比率大于接触件110a1的最小间距，该比率在一些示例中可以大于或等于2:1或者在其他情况下大于或等于3:1或者可能更大。
介电区域110可以具有多达10ppm/摄氏度的热膨胀系数(“CTE”)，并且在一些情况下可以具有与硅或其他半导体材料的CTE相同或接近的CTE，例如低于5ppm/摄氏度的CTE。
如图3所示，可以在介电区域110的第二表面110b上设置密封剂120。在一个示例中，密封剂120可以是成型物，其可以部分地或完全地密封导电元件115。密封剂120可以填充相邻的导电元件115之间的空间。在一个示例中，密封剂120可以具有多达10ppm/摄氏度范围内的CTE。
参照图4，与图1相比，可以从介电区域110的第一表面110a去除支持结构105的厚度T的至少一部分。例如，这可以根据各种方法来进行，诸如研磨、打磨或抛光或剥离、断裂、蚀刻或上述工艺的任何组合，它们可以与其他工艺进行组合。在去除工艺期间，设置为研磨停止层或端点检测层的介电层114可以被检测或暴露。这可以帮助确保支持结构105(尤其是一种半导体材料或非绝缘体)被完全去除，同时还确保不去除介电区域110自身的任何部分。
如图5所示，多个微电子元件130可以定位在介电区域110的第一表面110a上方。微电子元件可以具有达到10ppm/摄氏度范围内的热膨胀系数。在一个示例中，微电子元件130可以是或者包括其上具有有源电路元件(诸如晶体管)的半导体芯片。微电子元件130可以在平行于第一表面110a的方向上隔开。在另一示例中，微电子元件130可以是或者包括无源电路元件，诸如芯片上集成无源器件(“IPOC”)。还可以设置附加微电子元件130a。微电子元件130a可以是无源微电子元件，诸如无源裸片。
每个微电子元件130都具有面131以及位于面131处的多个接触件，接触件可以面对介电区域的面110a并与介电区域的面110a处的对应接触件110a1接合(诸如通过导电接合金属)。以相同方式，元件130a还可以与接触件110a1接合。
如图6所示，可以设置密封剂135。密封剂可以包括底部填充物和/或成型物。在一个示例中，密封剂135可以具有比与密封剂120相关联的CTE大的CTE，具体是因为微电子元件130中的硅用作加固物并具有较大的杨氏模量。在其他示例中，密封剂120和135可以具有相同值的CTE，或者密封剂135可以具有比密封剂120小的CTE。
如图所示，密封剂120和135的组合可以分别或者组合至少部分地或完全地密封介电区域110。这可以提供容易处理的组件。在其他示例中，可以从组件中省略密封剂135。
如图7所示，可以去除部分密封剂120和/或导电元件115以至少部分地露出导电元件115。这可以通过诸如研磨、打磨、抛光等的磨损工艺来实现。可选地，导电元件115(可以包括焊料、锡或其他导电材料的导电块)可以形成为与其他导电结构(例如，焊盘116、通孔、迹线，它们在去除工艺期间露出)接触。
在一个示例中，还可以去除部分密封剂135和部分微电子元件130。这也可以通过研磨、打磨等来实现。
如图8所示，接合元件140可以附接至接触件130。例如，接合元件可以由焊接材料(例如但不限于焊料、锡、共晶成分或导电基质材料，即加载有金属颗粒或薄片的聚合材料)的导电块制成或包括焊接材料的导电块。在具体示例中，接合元件可以包括金属元件，其具有低熔化温度组成和高熔化温度组成。
图9示出了根据本公开的方面的包括中介片的微电子组件200。例如，中介片可以包括介电区域110、导电元件115和密封剂120。在该阶段，接合元件140可连接至衬底150。此外，可以设置诸如底部填充物的密封剂145以填充密封剂120、衬底150和接合元件140之间的空间。
在一个示例中，密封剂120可具有不大于与微电子元件或与微电子元件接合的介电区域110相关联的CTE的两倍的CTE。
尽管未示出，但衬底150可进一步经由衬底接触件(未示出)在电路板的表面处连接至电路板。此外或可选地，衬底150本身可以是电路板或者可以包括无源、有源或其他电路元件。
上述结构提供了卓越的三维互连能力。这些能力可被任何类型的芯片使用。仅通过示例，可以在上述结构中包括芯片的以下组合：(i)处理器和被处理器使用的存储器；(ii)相同类型的多个存储芯片；(iii)不同类型的多个存储芯片，诸如DRAM和SRAM；(iv)图像传感器和用于处理来自传感器的图像的图像处理器；(v)专用集成电路(“ASIC”)和存储器。上述结构可以在不同的电子系统的结构中使用。例如，根据本发明又一实施例的系统300包括上述结构306结合其他电子部件308和310。在所示示例中，部件308是半导体芯片，而部件310是显示屏，但是还可以使用任何其他部件。当然，尽管仅为了说明清楚而在图10中示出了两个附加部件，但该系统可包括任何数量的这些部件。例如，上述结构306例如可以为上面结合图1至图9讨论的微电子组件。结构306以及部件308和310被安装在公共壳体301(以虚线示意性示出)并且根据需要相互电互连以形成期望的电路。在所示示例性系统中，系统包括电路板302(诸如柔性印刷电路板)，而电路板包括多个导体304(在图10中仅示出一个，用于将部件相互互连)。然而，这仅仅是示例性的；可以使用用于进行电连接的任何适当的结构。壳体301被示为例如可在蜂窝电话或个人数字助理中使用的类型的便携式壳体，并且屏幕310在壳体的表面处露出。在结构306包括光敏元件(诸如成像芯片)的情况下，还可以设置用于将光传输至结构的透镜311或其他光学设备。再次，图10所示的简化系统仅仅是示例性的；可以使用上述结构制造其他系统，包括通常认为是固定结构的系统，诸如台式计算机、路由器等。
在不背离本发明的精神的情况下可以使用上述特性的这些和其他变型和组合，应该通过说明来进行优选实施例的描述而不用于限制权利要求所限定的本发明。

Claims (28)

1.一种微电子组件，包括：
介电区域，具有第一表面、与所述第一表面相对的第二表面以及多条迹线和多个接触件，所述多条迹线在平行于所述第一表面和所述第二表面的至少一个方向上延伸，所述多个接触件位于所述介电区域的所述第一表面处；
多个导电元件，耦合至所述迹线并在所述第二表面上方突出；
密封剂，在所述第二表面上方延伸，所述密封剂填充相邻导电元件之间的空间并具有上覆且背对所述第二表面的表面，其中所述导电元件的端部位于所述密封剂的表面处；
微电子元件，具有一面和位于所述面处的多个元件接触件，所述元件接触件面对并接合至所述多个接触件，
其中所述密封剂的热膨胀系数(CTE)不大于与所述介电区域或所述微电子元件中的至少一个相关联的CTE的两倍。
2.根据权利要求1所述的微电子组件，其中所述密封剂是第一密封剂，所述微电子组件还包括：
第二密封剂，在所述第一表面上方延伸。
3.根据权利要求2所述的微电子元件，其中所述第二密封剂的CTE等于所述第一密封剂的CTE。
4.根据权利要求2所述的微电子组件，其中所述第一密封剂和所述第二密封剂密封所述介电区域。
5.根据权利要求1所述的微电子组件，其中所述微电子元件包括在平行于所述第一表面的至少一个方向上隔开的至少两个微电子元件。
6.根据权利要求1所述的微电子组件，其中所述介电区域包括第一介电材料的第一层和被配置为用作工艺停止层的不同介电材料的第二层。
7.根据权利要求1所述的微电子组件，其中所述多个导电元件包括选自由焊料、锡、铟、铜、镍、金、共晶成分、非共晶成分和导电基质材料组成的组中的接合材料的至少一块。
8.根据权利要求1所述的微电子组件，其中所述多个导电元件包括具有主要由选自铜、铜合金、镍和镍合金的至少一种金属组成的至少一个核心的多个金属柱，所述柱具有高于300℃的熔化温度。
9.根据权利要求1所述的微电子组件，还包括电路板，其中所述多个导电元件与位于所述电路板的表面处的对应接触件接合。
10.根据权利要求1所述的微电子组件，其中所述介电层选自由后段制程(BEOL)层和再分布层(RDL)组成的组。
11.一种系统，包括根据权利要求1所述的微电子组件以及电连接至结构的一个或多个其他电子部件。
12.根据权利要求11所述的系统，还包括壳体，所述微电子组件和所述其他电子部件安装有所述壳体。
13.一种中介片，包括：
介电区域，具有第一表面、与所述第一表面相对的第二表面以及多条迹线和多个接触件，所述多条迹线在平行于所述第一表面和所述第二表面的至少一个方向上延伸，所述多个接触件位于所述介电区域的所述第一表面处；
多个导电元件，耦合至所述迹线并在所述第二表面上方突出；
密封剂，在所述第二表面上方延伸，所述密封剂填充相邻导电元件之间的空间并具有上覆且背对所述第二表面的表面，其中所述导电元件的端部位于所述密封剂的表面处，
其中所述密封剂的热膨胀系数(CTE)不大于与至少所述介电区域或微电子元件相关联的CTE的两倍，所述微电子元件具有被配置用于与所述第一表面处的接触件的倒装连接的接触件。
14.根据权利要求13所述的中介片，其中所述第二密封剂的CTE等于所述第一密封剂的CTE。
15.根据权利要求13所述的中介片，其中所述介电区域包括第一介电材料的第一层和被配置为用作工艺停止层的不同介电材料的第二层。
16.根据权利要求13所述的中介片，其中所述多个导电元件包括选自由焊料、锡、铟、铜、镍、金、共晶成分、非共晶成分和导电基质材料组成的组中的接合材料的至少一块。
17.根据权利要求13所述的中介片，其中所述多个导电元件包括具有主要由选自铜、铜合金、镍和镍合金的至少一种金属组成的至少一个核心的多个金属柱，所述柱具有高于300℃的熔化温度。
18.根据权利要求13所述的中介片，其中所述介电层选自由后段制程(BEOL)层和再分布层(RDL)组成的组。
19.一种制造微电子组件的方法，包括：
形成填充设置在支持结构上的介电区域的第二表面上方向上突出的相邻导电元件之间的空间，其中与所述导电元件电连接的多条迹线在平行于第一表面和所述第二表面的至少一个方向上延伸，所述密封剂具有上覆且背对所述第二表面的表面，其中所述导电元件的端部位于所述密封剂的表面处；
在朝向所述介电区域的第一表面的方向上去除所述支持结构的厚度的至少一部分；
组装具有一面和位于所述面处的多个元件接触件的微电子元件，使得所述元件接触件面对并接合至所述多个接触件，
其中所述密封剂的热膨胀系数(CTE)不大于与所述介电区域或所述微电子元件中的至少一个相关联的CTE的两倍。
20.根据权利要求19所述的方法，还包括：
在组装所述微电子元件之后，去除所述密封剂的表面处的所述密封剂的一部分，从而去除所述密封剂的表面处的导电元件的部分。
21.根据权利要求19所述的方法，还包括：
在去除所述密封剂的一部分之后，将多个接合元件附接至所述表面处的导电元件的部分，所述接合元件被配置为与第二部件的表面处的多个接触件接合。
22.根据权利要求19所述的方法，其中所述密封剂是第一密封剂，所述方法还包括形成第二密封剂，所述第二密封剂在所述第一表面上方延伸，所述第二密封剂的CTE等于所述第一密封剂的CTE。
23.根据权利要求19所述的方法，还包括：
在组装具有所述介电区域的所述微电子元件之后，在所述微电子元件与所述介电区域的第一表面相对的表面处研磨所述微电子元件，以去除所述微电子元件的厚度的至少一部分。
24.根据权利要求19所述的方法，其中所述微电子元件包括多个微电子元件。
25.根据权利要求19所述的方法，还包括：
将所述多个导电元件与电路板的表面处的对应接触件接合。
26.根据权利要求19所述的方法，其中集成地形成所述支持结构和所述介电区域。
27.根据权利要求19所述的方法，其中所述支持结构主要由第一材料组成，并且所述介电区域主要由第二材料组成。
28.根据权利要求19所述的方法，还包括：
沉积工艺停止层；以及
利用所述工艺停止层停止去除工艺。
CN201480022444.3A 2013-03-14 2014-03-14 不具有tsv结构的低cte中介片和方法 Active CN105122445B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/828,938 2013-03-14
US13/828,938 US8884427B2 (en) 2013-03-14 2013-03-14 Low CTE interposer without TSV structure
PCT/US2014/027699 WO2014152756A1 (en) 2013-03-14 2014-03-14 Low cte interposer without tsv structure and method

Publications (2)

Publication Number Publication Date
CN105122445A true CN105122445A (zh) 2015-12-02
CN105122445B CN105122445B (zh) 2018-09-21

Family

ID=50686162

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480022444.3A Active CN105122445B (zh) 2013-03-14 2014-03-14 不具有tsv结构的低cte中介片和方法

Country Status (5)

Country Link
US (3) US8884427B2 (zh)
KR (1) KR102037114B1 (zh)
CN (1) CN105122445B (zh)
TW (1) TWI559474B (zh)
WO (1) WO2014152756A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101195786B1 (ko) 2008-05-09 2012-11-05 고쿠리츠 다이가쿠 호진 큐슈 코교 다이가쿠 칩 사이즈 양면 접속 패키지의 제조 방법
US8884427B2 (en) * 2013-03-14 2014-11-11 Invensas Corporation Low CTE interposer without TSV structure
US9213361B1 (en) * 2013-09-18 2015-12-15 Amazon Technologies, Inc. Temperature sensor in flex circuit
US9916999B2 (en) 2015-06-04 2018-03-13 Micron Technology, Inc. Methods of fabricating a semiconductor package structure including at least one redistribution layer
US10181447B2 (en) 2017-04-21 2019-01-15 Invensas Corporation 3D-interconnect
KR102450580B1 (ko) 2017-12-22 2022-10-07 삼성전자주식회사 금속 배선 하부의 절연층 구조를 갖는 반도체 장치
KR20220083438A (ko) 2020-12-11 2022-06-20 삼성전자주식회사 반도체 패키지
KR102778452B1 (ko) 2021-03-24 2025-03-11 삼성전자주식회사 관통 비아 구조물을 갖는 반도체 장치
KR20230029115A (ko) * 2021-08-23 2023-03-03 삼성전자주식회사 코어 기판, 코어 기판을 포함하는 패키지 구조체, 및 반도체 패키지의 제조 방법
US12040284B2 (en) 2021-11-12 2024-07-16 Invensas Llc 3D-interconnect with electromagnetic interference (“EMI”) shield and/or antenna

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005059993A2 (en) * 2003-12-17 2005-06-30 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US20080050901A1 (en) * 2006-08-23 2008-02-28 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
EP1028463B1 (en) * 1999-01-18 2008-10-08 Kabushiki Kaisha Toshiba Method for manufacturing a module with a flexible package having a very thin semiconductor chip
US20110080713A1 (en) * 2009-10-06 2011-04-07 Shinko Electric Industries Co., Ltd. Interposer mounted wiring board and electronic component device
CN102646668A (zh) * 2011-02-17 2012-08-22 三星电子株式会社 具有基板穿孔的中间体的半导体封装及其制造方法
US20120267751A1 (en) * 2011-04-21 2012-10-25 Tessera Research Llc Interposer having molded low cte dielectric

Family Cites Families (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855868A (en) * 1987-01-20 1989-08-08 Harding Ade Yemi S K Preformed packaging arrangement for energy dissipating devices
US4829403A (en) * 1987-01-20 1989-05-09 Harding Ade Yemi S K Packaging arrangement for energy dissipating devices
US5030796A (en) * 1989-08-11 1991-07-09 Rockwell International Corporation Reverse-engineering resistant encapsulant for microelectric device
JPH0376255A (ja) * 1989-08-18 1991-04-02 Fujitsu Ltd 半導体装置の実装構造
JPH0372655A (ja) 1990-08-03 1991-03-27 Hitachi Ltd 半導体集積回路装置
US5483421A (en) 1992-03-09 1996-01-09 International Business Machines Corporation IC chip attachment
US5454161A (en) 1993-04-29 1995-10-03 Fujitsu Limited Through hole interconnect substrate fabrication process
US5406117A (en) * 1993-12-09 1995-04-11 Dlugokecki; Joseph J. Radiation shielding for integrated circuit devices using reconstructed plastic packages
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
US6465743B1 (en) * 1994-12-05 2002-10-15 Motorola, Inc. Multi-strand substrate for ball-grid array assemblies and method
US6046076A (en) * 1994-12-29 2000-04-04 Tessera, Inc. Vacuum dispense method for dispensing an encapsulant and machine therefor
US5629241A (en) 1995-07-07 1997-05-13 Hughes Aircraft Company Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements, and method of fabricating the same
US5766987A (en) * 1995-09-22 1998-06-16 Tessera, Inc. Microelectronic encapsulation methods and equipment
US6255738B1 (en) * 1996-09-30 2001-07-03 Tessera, Inc. Encapsulant for microelectronic devices
US6127724A (en) * 1996-10-31 2000-10-03 Tessera, Inc. Packaged microelectronic elements with enhanced thermal conduction
WO1998044564A1 (en) * 1997-04-02 1998-10-08 Tessera, Inc. Chip with internal signal routing in external element
US5884396A (en) * 1997-05-01 1999-03-23 Compeq Manufacturing Company, Limited Transfer flat type ball grid array method for manufacturing packaging substrate
US5990418A (en) * 1997-07-29 1999-11-23 International Business Machines Corporation Hermetic CBGA/CCGA structure with thermal paste cooling
US6046910A (en) * 1998-03-18 2000-04-04 Motorola, Inc. Microelectronic assembly having slidable contacts and method for manufacturing the assembly
US6426642B1 (en) * 1999-02-16 2002-07-30 Micron Technology, Inc. Insert for seating a microelectronic device having a protrusion and a plurality of raised-contacts
TW512467B (en) 1999-10-12 2002-12-01 North Kk Wiring circuit substrate and manufacturing method therefor
US6602740B1 (en) * 1999-11-24 2003-08-05 Tessera, Inc. Encapsulation of microelectronic assemblies
KR20010094893A (ko) 2000-04-07 2001-11-03 정보영 손가방용 소매치기방지장치
TW512567B (en) 2001-11-04 2002-12-01 Uis Abler Electronics Co Ltd Electricity resonance protection module
US6873039B2 (en) * 2002-06-27 2005-03-29 Tessera, Inc. Methods of making microelectronic packages including electrically and/or thermally conductive element
US7535100B2 (en) * 2002-07-12 2009-05-19 The United States Of America As Represented By The Secretary Of The Navy Wafer bonding of thinned electronic materials and circuits to high performance substrates
JP3874108B2 (ja) 2002-08-13 2007-01-31 信越化学工業株式会社 エポキシ樹脂組成物
US6734039B2 (en) * 2002-09-06 2004-05-11 Advanpack Solutions Pte Ltd. Semiconductor chip grid array package design and method of manufacture
US7166491B2 (en) 2003-06-11 2007-01-23 Fry's Metals, Inc. Thermoplastic fluxing underfill composition and method
US8641913B2 (en) 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
US7501839B2 (en) * 2005-04-21 2009-03-10 Endicott Interconnect Technologies, Inc. Interposer and test assembly for testing electronic devices
US7253518B2 (en) * 2005-06-15 2007-08-07 Endicott Interconnect Technologies, Inc. Wirebond electronic package with enhanced chip pad design, method of making same, and information handling system utilizing same
US7622309B2 (en) * 2005-06-28 2009-11-24 Freescale Semiconductor, Inc. Mechanical integrity evaluation of low-k devices with bump shear
US7759782B2 (en) 2006-04-07 2010-07-20 Tessera, Inc. Substrate for a microelectronic package and method of fabricating thereof
US8476735B2 (en) * 2007-05-29 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Programmable semiconductor interposer for electronic package and method of forming
US8304915B2 (en) 2008-07-23 2012-11-06 Nec Corporation Semiconductor device and method for manufacturing the same
US8692135B2 (en) 2008-08-27 2014-04-08 Nec Corporation Wiring board capable of containing functional element and method for manufacturing same
US7776649B1 (en) * 2009-05-01 2010-08-17 Powertech Technology Inc. Method for fabricating wafer level chip scale packages
US20100327421A1 (en) * 2009-06-30 2010-12-30 Stmicroelectronics Asia Pacific Pte. Ltd. Ic package design with stress relief feature
US8039304B2 (en) * 2009-08-12 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structures
US8164158B2 (en) 2009-09-11 2012-04-24 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device
US8368232B2 (en) * 2010-03-25 2013-02-05 Qualcomm Incorporated Sacrificial material to facilitate thin die attach
US8535989B2 (en) * 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8278690B2 (en) * 2010-04-27 2012-10-02 Omnivision Technologies, Inc. Laser anneal for image sensors
US8896136B2 (en) * 2010-06-30 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark and method of formation
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8587126B2 (en) * 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8492203B2 (en) 2011-01-21 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers
CN103430298B (zh) * 2011-03-16 2016-03-16 Memc电子材料有限公司 在处理晶片中具有高电阻率区域的绝缘体上硅结构及制造此类结构的方法
US8841765B2 (en) * 2011-04-22 2014-09-23 Tessera, Inc. Multi-chip module with stacked face-down connected dies
US8525321B2 (en) * 2011-07-06 2013-09-03 Fairchild Semiconductor Corporation Conductive chip disposed on lead semiconductor package
TWI492680B (zh) 2011-08-05 2015-07-11 Unimicron Technology Corp 嵌埋有中介層之封裝基板及其製法
US8988895B2 (en) * 2011-08-23 2015-03-24 Tessera, Inc. Interconnection elements with encased interconnects
US9123763B2 (en) * 2011-10-12 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure having at least one package comprising one die being disposed in a core material between first and second surfaces of the core material
TWI503935B (zh) * 2011-10-17 2015-10-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9484319B2 (en) * 2011-12-23 2016-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming extended semiconductor device with fan-out interconnect structure to reduce complexity of substrate
US9401308B2 (en) * 2013-03-12 2016-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices, methods of manufacture thereof, and packaging methods
US8900922B2 (en) * 2012-02-16 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Fine-pitch package-on-package structures and methods for forming the same
US8372741B1 (en) * 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
TWI517274B (zh) * 2012-03-21 2016-01-11 矽品精密工業股份有限公司 晶圓級半導體封裝件之製法及其晶圓級封裝基板之製法
US8978247B2 (en) 2012-05-22 2015-03-17 Invensas Corporation TSV fabrication using a removable handling structure
US20140048951A1 (en) * 2012-08-14 2014-02-20 Bridge Semiconductor Corporation Semiconductor assembly with dual connecting channels between interposer and coreless substrate
US8946884B2 (en) 2013-03-08 2015-02-03 Xilinx, Inc. Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product
TWI496270B (zh) * 2013-03-12 2015-08-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US8884427B2 (en) * 2013-03-14 2014-11-11 Invensas Corporation Low CTE interposer without TSV structure
US9318452B2 (en) * 2014-03-21 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
JP2016048729A (ja) * 2014-08-27 2016-04-07 株式会社東芝 仮接着用支持基板及び半導体デバイスの製造方法
TWI559488B (zh) * 2014-12-27 2016-11-21 矽品精密工業股份有限公司 封裝結構及其製法
JP6313251B2 (ja) * 2015-03-12 2018-04-18 東芝メモリ株式会社 半導体装置の製造方法
US9818684B2 (en) * 2016-03-10 2017-11-14 Amkor Technology, Inc. Electronic device with a plurality of redistribution structures having different respective sizes

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1028463B1 (en) * 1999-01-18 2008-10-08 Kabushiki Kaisha Toshiba Method for manufacturing a module with a flexible package having a very thin semiconductor chip
WO2005059993A2 (en) * 2003-12-17 2005-06-30 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US20080050901A1 (en) * 2006-08-23 2008-02-28 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US20110080713A1 (en) * 2009-10-06 2011-04-07 Shinko Electric Industries Co., Ltd. Interposer mounted wiring board and electronic component device
CN102646668A (zh) * 2011-02-17 2012-08-22 三星电子株式会社 具有基板穿孔的中间体的半导体封装及其制造方法
US20120267751A1 (en) * 2011-04-21 2012-10-25 Tessera Research Llc Interposer having molded low cte dielectric

Also Published As

Publication number Publication date
WO2014152756A1 (en) 2014-09-25
US20170194373A1 (en) 2017-07-06
US10396114B2 (en) 2019-08-27
KR102037114B1 (ko) 2019-10-28
CN105122445B (zh) 2018-09-21
KR20150129773A (ko) 2015-11-20
US20150044820A1 (en) 2015-02-12
TWI559474B (zh) 2016-11-21
US8884427B2 (en) 2014-11-11
TW201448138A (zh) 2014-12-16
US20140264794A1 (en) 2014-09-18
US9558964B2 (en) 2017-01-31

Similar Documents

Publication Publication Date Title
CN105122445B (zh) 不具有tsv结构的低cte中介片和方法
JP5857065B2 (ja) 能動チップを接続するインターポーザを有する積層超小型電子アセンブリ
US9917042B2 (en) 2.5D microelectronic assembly and method with circuit structure formed on carrier
US8709913B2 (en) Simultaneous wafer bonding and interconnect joining
US8951845B2 (en) Methods of fabricating a flip chip package for dram with two underfill materials
US10181411B2 (en) Method for fabricating a carrier-less silicon interposer
US9859234B2 (en) Methods and structures to repair device warpage
US10403510B2 (en) Method of fabricating a carrier-less silicon interposer using photo patterned polymer as substrate
US9543277B1 (en) Wafer level packages with mechanically decoupled fan-in and fan-out areas

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant