CN104752203A - Thin film transistor manufacturing method - Google Patents

Abstract

The invention discloses a manufacturing method of a thin film transistor, which comprises the following steps: (1) first depositing a layer of amorphous silicon on the substrate of the thin film transistor by chemical vapor deposition; Crystallized silicon becomes polysilicon. During the crystallization process, a large number of protrusions caused by laser annealing crystallization are produced on the surface of polysilicon; (3) A planarization layer is made on the polysilicon with protrusions by coating method, so that the planarization layer is completely The protrusions covering the polysilicon; (4) etching the planarization layer, when the protrusions are etched, the planarization layer is etched away together with the protrusions, leaving a remaining flat surface on the polysilicon layer with a small amount of bumps remaining. Adopting the manufacturing method of the thin film transistor of the present invention can greatly reduce the protrusion height of the polysilicon after ELA crystallization, improve the uniformity of the AMOLED back plate, and make the display effect better.

Description

A method of manufacturing a thin film transistor

technical field

The present invention relates to a method for manufacturing a thin film transistor (TFT, Thin Film Transistor) in an active matrix organic light emitting display (AMOLED, Active Matrix Organic Light Emitting Diode), in particular to a method that can effectively reduce excimer laser annealing polysilicon protrusions. A method of fabricating a highly advanced thin film transistor.

Background technique

At present, LTPS (Low Temperature Poly-silicon, low temperature polysilicon) backplane preparation technology mainly adopts ELA (Excimer Laser Annealer, excimer laser annealing) mainstream crystallization technology, under the irradiation of high-energy laser, a-Si (amorphous silicon) recrystallizes to form Poly (polysilicon), but this layer of Poly film has obvious existence at the grain boundary of polysilicon The protrusions affect the thickness and step coverage of the subsequent gate oxide layer, which mainly affects the electrical properties of the TFT. Take a-Si with a thickness of 500Å as an example to illustrate the influence of this protrusion: 500Å a-Si is used as the ELA precursor, and the height of the protrusion generated after crystallization is about 400~500Å, after which a gate oxide layer of 1200Å is deposited. If the protrusion If the rise appears in the channel region, the thickness of the gate oxide layer is only 700~800Å in the raised part, and the thickness of the gate oxide layer in the non-raised area is 1200Å. If the same gate voltage and source-drain voltage are applied , the TFT with a thinner gate oxide layer (700Å) is turned on before the TFT with a thicker gate oxide layer (1200Å), which reduces the Vth (threshold voltage) uniformity of the entire backplane and deteriorates the display effect.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a thin film transistor manufacturing method that can effectively reduce the height of ELA-Poly protrusions and make the backplane uniformly displayed.

In order to achieve the above object, the present invention provides a method for manufacturing a thin film transistor, which includes the following steps:

(1) First, a layer of amorphous silicon is deposited on the substrate of the thin film transistor by chemical vapor deposition;

(2) Use excimer laser annealing technology to crystallize amorphous silicon into polysilicon. During the crystallization process, a large number of protrusions are generated on the surface of polysilicon due to laser annealing crystallization;

(3) Making a planarization layer on the polysilicon with protrusions by coating, so that the planarization layer completely covers the protrusions of the polysilicon;

(4) Etching the planarization layer, when the protrusion is etched, the planarization layer and the protrusion are etched away, leaving the remaining planarization layer and the remaining protrusion on the polysilicon .

In step (4), the etching method is dry etching or reactive ion etching.

In step (1), the thickness of the amorphous silicon is 300-1000 Å.

In step (2), the thickness of the polysilicon is 500-1000 Å, and the height of the protrusion is 300-700 Å.

In step (2), the planarization layer has a thickness of 500-5000 Å.

The material of the planarization layer is a planarization material such as polyimide, resin or inorganic glue.

The thickness of the remaining planarization layer and the height of the remaining protrusions are 100 Å.

The manufacturing method of the thin film transistor further includes etching the remaining planarization layer by using a stripping device.

After etching in the step (4), the remaining protrusions are higher than the remaining planarization layer, or the tops of the remaining protrusions are lower than the tops of the remaining planarization layer, or the remaining protrusions are The remaining planarization layer is leveled.

The remaining protrusions higher than the remaining flattening layer have a trapezoidal structure, and the remaining protrusions lower than the remaining flattening layer have a crescent-shaped structure.

Adopting the manufacturing method of the thin film transistor of the present invention can greatly reduce the protrusion height of the polysilicon after ELA crystallization, improve the uniformity of the AMOLED back plate, and make the display effect better.

Description of drawings

Figure 1 is a schematic diagram of the TFT substrate structure after depositing amorphous silicon by CVD;

Fig. 2 is a schematic diagram of the structure of a polysilicon TFT substrate with protrusions after crystallization by ELA;

3 is a schematic diagram of a substrate structure with a planarization layer made on a polysilicon TFT substrate with protrusions;

4 is a schematic diagram of the structure of the TFT substrate after etching the planarization layer;

5 is a schematic diagram of the structure of the substrate after peeling off the remaining planarization layer;

Figure 6 (a), (b), and (c) are schematic diagrams of the structures of three kinds of etched polysilicon bumps;

Figure 7 is a schematic diagram of polysilicon SEM (scanning electron microscope) with bumps crystallized by ELA;

FIG. 8 is a process flow chart of the manufacturing method of the thin film transistor of the present invention.

Detailed ways

In order to facilitate a further understanding of the method and the achieved effects of the present invention, preferred embodiments are described in detail below in conjunction with the accompanying drawings.

Referring to the process flow diagram of Fig. 8 and other accompanying drawings of the present invention, first, a layer of amorphous silicon 011 is deposited on the TFT substrate 02 by CVD (Chemical Vapor Deposition, chemical vapor deposition) deposition method, as shown in Fig. 1, the deposited Schematic diagram of the structure, the substrate 02 is a glass substrate, and the thickness of the amorphous silicon 011 film is 300-1000 Å.

Use ELA (excimer laser annealing) technology to crystallize amorphous silicon 011 to become polysilicon 01. During the crystallization process, a large number of protrusions 03 are generated on the surface of polysilicon 01 due to ELA crystallization, as shown in Figure 2, with protrusions 03 Schematic diagram of the polysilicon 01 TFT substrate structure. At this time, the TFT backplane is composed of substrate 02 and ELA crystallized polysilicon 01, and the thickness of polysilicon 01 is 500-1000 Å, where the height of the protrusion 03 on the crystallized polysilicon surface is generally between 300-700 Å, as shown in Figure 7, the SEM photo of the protrusion 03 of polysilicon 01 crystallized by ELA, the height of the protrusion is about 600 Å .

Make a planarization layer 04 on the polysilicon 02 with protrusions 03 by coating, as shown in Figure 3, the material of the planarization layer 04 can be polyimide, resin, inorganic glue, etc., the thickness of the planarization layer 04 For 500-5000 Å, make sure to completely cover the bump 03 of the polysilicon 02.

After the protrusion 03 is covered with the planarization layer 04 , the planarization layer 04 is etched, and the etching method may be dry etching or RIE (Reactive Ion Etching, reactive ion etching). When the part of the protrusion 03 is etched, the planarization layer 04 and the protrusion 03 are etched away together. In order not to damage the interface of the polysilicon 02, the thickness of the planarization layer 04 and the protrusion 03 can be kept at about 100 Å, such as As shown in FIG. 4 , there are remaining planarization layers 042 and remaining protrusions 032 above the polysilicon 02 after etching, and the remaining thickness is about 100 Å. Using this method, the protrusion 03 of the polysilicon 02 can be reduced from the original 300-700 Å to about 100 Å, and at the same time, due to the setting of the planarization layer 04, it can be guaranteed that the polysilicon 02 will not be damaged during the etching process.

After the etching of the planarization layer 04 and the protrusion 03 is completed, the remaining planarization layer 042 can be used as a part of the insulating layer, and then the normal process can be carried out; in addition, the remaining planarization layer 042 can be etched completely by using a stripping device, only Keep the remaining bumps 032, as shown in FIG. 5, and then carry out the normal process.

In the etching process, since the materials of the planarization layer 04 and the protrusion 03 are different, the etching selectivity ratio of the planarization layer 04 and the protrusion 03 is often different, and the structure of the remaining protrusion 032 is different, such as As shown in Figure 6, when the etching rate of the planarization layer 04 is greater than the etching rate of the protrusion 03, the structure of Figure 6(a) is obtained, the remaining protrusion 032 is higher than the remaining planarization layer 042, and the remaining protrusion 032 is Trapezoidal structure; when the etching rate of the planarization layer 04 is lower than the etching rate of the protrusion 03, the structure in Figure 6(b) is obtained, and the top of the remaining protrusion 032 is depressed, which is a crescent-shaped structure, that is, the top of the remaining protrusion 032 lower than the top of the remaining planarization layer 042; when the etching rate of the planarization layer 04 is equal to the etching rate of the protrusion 03, the structure in Figure 6(c) under ideal conditions is obtained, and the remaining protrusion 032 and the remaining planarization layer 042 flush.

Therefore, by adopting the manufacturing method of the thin film transistor of the present invention, the protrusion height of the polysilicon after ELA crystallization can be greatly reduced, the uniformity of the AMOLED backplane can be improved, and the display effect can be better.

The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, any person with ordinary knowledge in the technical field, without departing from the spirit and scope of the present invention, Some changes and modifications can be made, so the protection scope of the present invention should be defined by the claims.

Claims (10)

1. a manufacture method for thin-film transistor, is characterized in that, it comprises the steps:

(1) chemical vapour deposition technique is first utilized to deposit one deck amorphous silicon on the substrate of thin-film transistor;

(2) utilize quasi-molecule laser annealing technology by recrystallized amorphous silicon, become polysilicon, in crystallization process, polysilicon surface produces a large amount of projection caused due to laser-annealing crystallization;

(3) utilize coating method to make planarization layer on the polysilicon with projection, make this planarization layer cover the projection of polysilicon completely;

(4) etch described planarization layer, when etching into bossing, planarization layer is etched away together with projection, and on described polysilicon, leave residue planarization layer protruding with residue.

2. the manufacture method of thin-film transistor as claimed in claim 1, is characterized in that, in step (4), the method for described etching is carved or reactive ion etching for dry.

3. the manufacture method of thin-film transistor as claimed in claim 1, it is characterized in that, in step (1), the thickness of described amorphous silicon is 300-1000.

4. the manufacture method of thin-film transistor as claimed in claim 1, it is characterized in that, in step (2), the thickness of described polysilicon is 500-1000, and the height of described projection is 300-700.

5. the manufacture method of thin-film transistor as claimed in claim 1, it is characterized in that, in step (2), the thickness of described planarization layer is 500-5000.

6. the manufacture method of thin-film transistor as claimed in claim 1, it is characterized in that, the material of described planarization layer is polyimides, resin or inorganic glue.

7. the manufacture method of thin-film transistor as claimed in claim 1, it is characterized in that, the thickness of described residue planarization layer and the height of described residue projection are 100.

8. the manufacture method of thin-film transistor as claimed in claim 1, is characterized in that, the manufacture method of described thin-film transistor also comprises and utilizes peel-off device complete for residue planarization layer etching.

9. the manufacture method of thin-film transistor as claimed in claim 1, it is characterized in that, in described step (4) after etching, described residue projection exceeds described residue planarization layer, or described residue protruding apex is lower than described residue planarization layer top, or described residue is protruding concordant with described residue planarization layer.

10. the manufacture method of thin-film transistor as claimed in claim 9, is characterized in that, the residue projection exceeding described residue planarization layer is trapezium structure, and the residue projection lower than described residue planarization layer is crescent structure.