CN104320125B - Low-power consumption synchronous sequence digital circuit chip and the clock signal chip generation method - Google Patents
Low-power consumption synchronous sequence digital circuit chip and the clock signal chip generation method Download PDFInfo
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- CN104320125B CN104320125B CN201410554082.4A CN201410554082A CN104320125B CN 104320125 B CN104320125 B CN 104320125B CN 201410554082 A CN201410554082 A CN 201410554082A CN 104320125 B CN104320125 B CN 104320125B
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Abstract
The invention discloses a kind of low-power consumption synchronous sequence digital circuit chip and the chip clock tree signal creating method.Using duplex feeding power supply, high-voltage power supply and LVPS, Clock Tree structure division individually is supplied electricity to the relatively low power supply of voltage all the way, the power consumption of Clock Tree can be significantly reduced, so reducing the overall power of chip.Wherein high-voltage power supply supplies electricity to each register and combinational circuit part, and LVPS mainly supplies electricity to Clock Tree part, is matched signal amplitude, it is necessary in place be changed high low-clock signal mutually using level translator.Because register and combinational circuit can use High Voltage Power Supply, the speed of chip is unaffected, so the power consumption of chip can be greatly reduced in the present invention on the premise of ensureing that chip performance is constant.
Description
Technical field
The present invention relates to low-power chip design field, in particular to a kind of low-power consumption synchronous sequence digital circuit core
Piece and the clock signal chip generation method.
Background technology
Most of current integrated circuit be CMOS (Complementary Metal Oxide Semiconductor, mutually
Mend metal-oxide semiconductor (MOS)) the synchronous sequence digital circuit chip of technique, necessarily include clock signal in this chip.Mesh
Before, the scale of cmos digital circuit chip is increasing, and speed is more and more faster, the power consumption nature more and more higher of chip, a lot
In application field, power consumption has become overriding concern factor or restraining factors.When the bigger frequency of digital circuit chip scale is faster,
The structure of Clock Tree therein just becomes more and more huger and complicated, so the power consumption consumed on Clock Tree accounts for chip total power consumption
Ratio more and more higher, some data show that the power consumption of Clock Tree consumption accounts for the 30~50% of chip total power consumption.In general,
Digital circuit chip includes Clock Tree, register and combinational logic circuit unit and (completes logical calculated, the function of operation.By most
The tandem circuit unit composition such as basic " with door " circuit, disjunction gate circuit and " NOT gate ") this three parts.Current in general core
In piece design, they are powered using same power supply.For this digital circuit chip, technical staff typically adopts
Low-frequency mode drops with reduction supply voltage or dynamically to save power consumption as needed, but these schemes also reduce simultaneously
The performance of chip is frequency.
The content of the invention
Present invention aim to provide a kind of low-power consumption synchronous sequence digital circuit chip and the clock signal chip
Work(can be greatly reduced on the premise of ensureing that chip frequency performance is constant in generation method, the chip and clock signal creating method
Consumption.
In order to achieve this, the low-power consumption synchronous sequence digital circuit chip designed by the present invention, it include Clock Tree, when
Clock signal driving unit, multiple registers and multiple combinational logic circuit units, the Clock Tree include source clock unit, more
Nodal clock unit and multiple corresponding end clock units corresponding to individual, combinational logic corresponding to each register connection
Circuit unit, it is characterised in that：It also includes high-voltage power supply, LVPS, high level to low transition device and multiple
Low level to high level translator, the output end of the high-voltage power supply connect respectively the feeder ear of clock signal driver element,
High level is to the high voltage power supply feeder ear of low transition device, the high voltage power supply power supply of each low level to high level translator
The feeder ear at end, the feeder ear of each register and each combinational logic circuit unit, the output end point of the LVPS
Not Lian Jie the feeder ear of source clock unit, the feeder ear of each nodal clock unit, each end clock unit feeder ear,
High level is to the low-tension supply feeder ear of low transition device, the low-tension supply power supply of each low level to high level translator
End, the clock signal output terminal of the clock signal driver element connect source in Clock Tree by high level to low transition device
The clock signal input terminal of head clock unit, the clock signal output terminal of each end clock unit passes through right in the Clock Tree
The low level answered to high level translator connects the clock signal input terminal of corresponding register.
A kind of clock signal generation method of above-mentioned low-power consumption synchronous sequence digital circuit chip, it is characterised in that it is wrapped
Include following steps：
Step 1：Feeder ear, high level to low transition device of the high-voltage power supply to clock signal driver element
High voltage power supply feeder ear, the high voltage power supply feeder ear of each low level to high level translator, each register feeder ear and
The feeder ear power supply of each combinational logic circuit unit, feeder ear, Ge Gejie of the LVPS to source clock unit
The feeder ear of the feeder ear of Dot Clock unit and each end clock unit, the low-tension supply of high level to low transition device supply
Electric end, the low-tension supply feeder ear power supply of each low level to high level translator, the power supply electricity of the high-voltage power supply output
Pressure is more than the supply voltage of LVPS output；
Step 2：The clock signal of the clock signal driver element output reference amplitude of oscillation, the benchmark amplitude of oscillation is high-voltage power supply
Voltage amplitude, the clock signal of the benchmark amplitude of oscillation is converted to the clock signal of the low amplitude of oscillation by high level to low transition device,
High level is to low transition device by the source clock unit of the clock signal input of the low amplitude of oscillation to Clock Tree；
Step 3：The clock signal of the low amplitude of oscillation is transmitted in above-mentioned Clock Tree, by extending step by step, finally by
Each end clock unit of Clock Tree by the clock signal transmission of the low amplitude of oscillation to corresponding low level into high level translator；
Step 4：Each low level reduces the clock signal of the above-mentioned low amplitude of oscillation received to high level translator
Into the clock signal of the said reference amplitude of oscillation；
Step 5：Each low level passes the clock signal of the benchmark amplitude of oscillation obtained in step 4 to high level translator
It is defeated by corresponding register.
The present invention principle be：
The general principle of cmos digital circuit power consumption is P=a*F*V2, wherein, P is power consumption, and a is the upset rate of signal, F
For the frequency of signal, V is the voltage of signal.If reducing some voltages, power consumption can be largely reduced.In fact, V
The turning height of signal is can be understood as, inside cmos circuit design field, the signal turning height base of some circuit unit
Originally it is the height of its supply voltage.If reduce voltage, then the turning height of signal just reduces.Come for clock signal
Say, the upset rate a of signal is very high, each clock cycle, and it is needed to overturn twice, and this can not be reduced.The frequency F of signal is core
The working frequency of piece, although there is some technologies to reduce frequency dynamically as needed to save power consumption, chip simultaneously
Performance also reduce.There is the global voltage that some technologies reduce chip in addition, but if chip integrally reduces voltage, chip
Speed can be serious slack-off, performance seriously reduces.The present invention uses two power supplies of height to chip power supply, wherein, low electricity
Voltage source is powered to clock tree construction, and high-voltage power supply is powered to register and combinational logic circuit unit, is coordinated and is turned with level
Parallel operation changes suitable signal level.When chip need to be operated in performance it is higher when deposited (when i.e. frequency is higher)
Device and combinational circuit part need apply high voltage can speed it is enough fast, because in the present invention, Clock Tree employs low electricity
Pressure power supply, the power consumption of this part can be greatly lowered, so the overall power consumption of chip is lower than conventional method.If in addition, core
When the supply voltage of register and combinational circuit reduces in piece, the supply voltage of Clock Tree part can also be further continued for reducing
Some, as long as chip operation is normal in the range of trouble free service, then overall power consumption can be lower than conventional method.The present invention
The power consumption that chip is greatly reduced on the premise of ensureing that chip performance is constant is realized by above-mentioned design, is advantageous to cmos digital
The design and use of circuit chip.
Brief description of the drawings
Fig. 1 is the structured flowchart of the present invention；
Fig. 2 is structured flowchart when each clock unit is buffer (buffer) in the present invention；
Fig. 3 is structured flowchart when each clock unit is phase inverter (inverter) in the present invention；
Fig. 4 is that the contrast of the amplitude of the square-like clock signal of the benchmark amplitude of oscillation and the square-like clock signal of the low amplitude of oscillation is shown in the present invention
It is intended to.
Fig. 5 is power net structural representation in the present invention.
Wherein, 1-high-voltage power supply, 2-LVPS, 3-Clock Tree, 3.1-source clock unit, 3.2-section
Dot Clock unit, 3.3-end clock unit, 3a-buffer, 3b-phase inverter, 4-clock signal driver element, 5-are posted
Storage, 6-high level to low transition device, 7-low level to high level translator, 8-combinational logic circuit unit.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail：
It is understood that power consumption is in square, P=a*F*V with voltage2, when voltage reduces, power consumption can be significantly
Reduce.Clock signal is the signal that chip internal is most active, upset is most frequent, but it does not do the place of any signal really
Reason, simply gives the chip synchronization sequence circuit i.e. clock end of register as the time reference function of reference.So for clock
This partial circuit of unit is set, goes to transmit clock signal using minimum energy as far as possible.Method is exactly that can reduce clock
The voltage of tree circuit part, while ensure that Clock Tree is working properly, it is possible to reaching reduces the purpose of this part power consumption.With current
Exemplified by the 28nm techniques of main flow, typical operating voltage is 1.0V or so.Pay attention to, factory is different, and technological parameter has difference, had
Slight fluctuation, only it is signal scope below.If improving voltage, high voltage range about can be to 1.2V~1.4V.Low voltage range
0.7V even 0.6V can be fallen to approximately.If so individually apply lower supply voltage, Clock Tree to Clock Tree part
Circuit is still can be with normal work, and simply performance is varied from, so needing carefully to design Clock Tree in the design process
Layout and pay attention to the control many factors such as clock signal characteristic, reach the purpose of normal work.
According to cmos circuit general principle, supply voltage needs the transistor threshold voltage more than 1.5 times or 2 times, circuit
Could normal work, for example regulatory thresholds voltage under 28nm techniques is 0.3V to 0.4V or so.If use some low thresholds
The transistor of threshold voltage, for example 0.2V to 0.3V low threshold voltage transistor is come if constructing Clock Tree, then Clock Tree
Supply voltage can also reduce again, more save power consumption.
The present invention devises following technical scheme based on the principle：
Low-power consumption synchronous sequence digital circuit chip as shown in Figure 1, it includes Clock Tree 3, clock signal driver element
4th, multiple registers 5 and multiple combinational logic circuit units 8, the Clock Tree 3 include source clock unit 3.1, multiple correspondences
Nodal clock unit 3.2 and multiple corresponding end clock units 3.3, each register 5 connect corresponding to combination patrol
Collect circuit unit 8, it is characterised in that：It also includes high-voltage power supply 1, LVPS 2, high level to low transition device 6
With multiple low levels to high level translator 7, the output end of the high-voltage power supply 1 connects clock signal driver element 4 respectively
Feeder ear, high voltage power supply feeder ear, the height of each low level to high level translator 7 of high level to low transition device 6
The feeder ear of voltage source feeder ear, the feeder ear of each register 5 and each combinational logic circuit unit 8, the low-voltage electricity
The output end in source 2 connects the feeder ear of source clock unit 3.1, feeder ear, the Ge Gemo of each nodal clock unit 3.2 respectively
Hold the feeder ear of clock unit 3.3, the low-tension supply feeder ear of high level to low transition device 6, the paramount electricity of each low level
The low-tension supply feeder ear of flat turn parallel operation 7, the clock signal output terminal of the clock signal driver element 4 is by high level to low
Level translator 6 connects the clock signal input terminal of source clock unit 3.1 in Clock Tree 3, each end in the Clock Tree 3
The clock signal output terminal of clock unit 3.3 by corresponding low level to high level translator 7 connect corresponding register 5 when
Clock signal input part (CLK pins).The clock signal output terminal connection first layer of source clock unit 3.1 in the Clock Tree 3
Each nodal clock unit 3.2 clock signal input terminal, each nodal clock unit 3.2 of the first layer clock letter
Number output end connects the clock signal input terminal of nodal clock unit 3.2 corresponding to next floor, during each node of last layer
The signal input part of the clock signal output terminal connection respective ends clock unit 3.3 of clock unit 3.2.
In above-mentioned technical proposal, Clock Tree 3 can be by the transistor configurations of regular threshold voltage, can also be by low-threshold power
The transistor configurations of pressure.As long as reach design needs.If using the transistor configurations Clock Tree of low threshold voltage, can adopt
With lower low voltage power supply to Clock Tree so that the upset amplitude of clock signal is smaller, while meets the speed for building Clock Tree
Degree requires.Clock Tree 3 is extended since source with tree, is sent to the position that all registers 5 need always.In reality
In, extension that may be Jing Guo plurality of layers, whole Clock Tree will almost spread to the scope (as shown in Figure 5) of whole chips.
In above-mentioned technical proposal, the supply voltage of the LVPS 2 for the supply voltage of high-voltage power supply 1 55~
65%, preferably 60%, or it is different according to technique, it is reduced to the relatively low voltage for causing Clock Tree normal work.
In above-mentioned technical proposal, the source clock unit 3.1, each nodal clock unit 3.2 and each end clock
Unit 3.3 is buffer 3a (buffer), as shown in Figure 2.Or the source clock unit 3.1, each nodal clock list
Member 3.2 and each end clock unit 3.3 form by two phase inverter 3b (inverter), wherein, first phase inverter 3b
Signal output part connect second phase inverter 3b signal input part, as shown in Figure 3.Two phase inverter 3b so connections are to letter
Number effect it is identical with said one buffer 3a.
In above-mentioned technical proposal, the buffer 3a and phase inverter 3b can be that the transistor of regulatory thresholds voltage is formed,
It can also be the transistor composition of low threshold voltage.Such as under 28nm process conditions, shown buffer 3a is voltage threshold
Scope is 0.2~0.4V low threshold voltage transistor, and shown phase inverter 3b is the low threshold that voltage threshold scope is 0.2~0.4V
Threshold voltage transistor.It is different according to the technological process of specific plant, it can change.In addition, under other techniques, magnitude of voltage and phase
Corresponding threshold voltage can be all varied from.
In above-mentioned technical proposal, the power generation configuration in chip is network structure, abbreviation power net.Power net has two, such as
Shown in Fig. 5.VDD is supplied with the power net (i.e. high-voltage power supply 1) of register 5 in chip, and VDD_CLK is to be supplied separately to Clock Tree
3 power net (i.e. LVPS 2).Because the clock unit of Clock Tree is dispersed in whole chip range, so VDD_CLK
Scope also to cover whole chip range.
A kind of clock signal generation method of above-mentioned low-power consumption synchronous sequence digital circuit chip, it comprises the following steps：
Step 1：Feeder ear, high level to low transition device of the high-voltage power supply 1 to clock signal driver element 4
The power supply of 6 high voltage power supply feeder ear, each low level to the high voltage power supply feeder ear, each register 5 of high level translator 7
The feeder ear of end and each combinational logic circuit unit 8 is powered, power supply of the LVPS 2 to source clock unit 3.1
End, the feeder ear of the feeder ear of each nodal clock unit 3.2 and each end clock unit 3.3, high level to low level turn
The low-tension supply feeder ear of parallel operation 6, the low-tension supply feeder ear power supply of each low level to high level translator 7, the high electricity
The supply voltage that voltage source 1 exports is more than the supply voltage that LVPS 2 exports；
Step 2：The clock signal of the output reference amplitude of oscillation of clock signal driver element 4, the benchmark amplitude of oscillation is high power supply
Voltage amplitude (be the signal swing below high voltage domain, inside cmos circuit, the letter for the circuit being operated under which power supply
Number amplitude of oscillation is exactly the amplitude of its supply voltage), the clock signal of the benchmark amplitude of oscillation is changed by high level to low transition device 6
For the clock signal of the low amplitude of oscillation, high level to low transition device 6 is by the clock signal input of the low amplitude of oscillation to the source of Clock Tree 3
In clock unit 3.1；
Step 3：The clock signal of the low amplitude of oscillation is transmitted in above-mentioned Clock Tree 3, by extending step by step, finally by
Each end clock unit 3.3 of Clock Tree 3 by the clock signal transmission of the low amplitude of oscillation corresponding to low level to high level conversion
In device 7；
Step 4：Each low level reduces the clock signal of the above-mentioned low amplitude of oscillation received to high level translator 7
Into the clock signal of the said reference amplitude of oscillation；
Step 5：Each low level is to high level translator 7 by the clock signal of the benchmark amplitude of oscillation obtained in step 4
Register 5 corresponding to being transferred to.
In above-mentioned technical proposal, the 55 of the clock signal excursion of the amplitude of oscillation on the basis of the clock signal excursion of the low amplitude of oscillation~
65%.Or cause Clock Tree normal work and reach the relatively low voltage of requirement.
In above-mentioned technical proposal, amplitude of oscillation square-like clock signal on the basis of the clock signal of the shown benchmark amplitude of oscillation, the low pendulum
The clock signal of width is that (ideal situation is usually square-wave signal to low amplitude of oscillation square-like clock signal.Slope is had in actual circuit, i.e.,
Similar filtered output), as shown in Figure 4.
In above-mentioned technical proposal, when chip is under 28nm techniques, the amplitude of benchmark amplitude of oscillation square-like clock signal is 1V, described
The amplitude of low amplitude of oscillation square-like clock signal is 0.6V, and the supply voltage that the LVPS 2 exports is the high-voltage power supply 1
The 60% of the supply voltage of output.Such scheme is only an example, as long as twin voltage in practice, the voltage of Clock Tree
It is more slightly lower than the voltage of other parts circuit, belong to the covering category of the present invention.
The content that this specification is not described in detail belongs to prior art known to professional and technical personnel in the field.
Claims (11)
1. a kind of low-power consumption synchronous sequence digital circuit chip, it includes Clock Tree (3), clock signal driver element (4), multiple
Register (5) and multiple combinational logic circuit units (8), the Clock Tree (3) include source clock unit (3.1), multiple right
The nodal clock unit (3.2) answered and multiple corresponding end clock units (3.3), each register (5) connection are corresponding
Combinational logic circuit unit (8), it is characterised in that：It also includes high-voltage power supply (1), LVPS (2), high level extremely
Low transition device (6) and multiple low levels to high level translator (7), the output end of the high-voltage power supply (1) connect respectively
Connect the high voltage power supply feeder ear, each low of the feeder ears of clock signal driver element (4), high level to low transition device (6)
Level is to the high voltage power supply feeder ear of high level translator (7), the feeder ear of each register (5) and each combinational logic circuit
The feeder ear of unit (8), the output end of the LVPS (2) connect the feeder ear of source clock unit (3.1), each respectively
The feeder ear of individual nodal clock unit (3.2), feeder ear, the high level to low transition of each end clock unit (3.3)
Low-tension supply feeder ear, the low-tension supply feeder ear of each low level to high level translator (7) of device (6), the clock letter
When the clock signal output terminal of number driver element (4) connects source in Clock Tree (3) by high level to low transition device (6)
The clock signal input terminal of clock unit (3.1), the clock signal of each end clock unit (3.3) is defeated in the Clock Tree (3)
Go out the clock signal input terminal that end connects corresponding register (5) by corresponding low level to high level translator (7).
2. low-power consumption synchronous sequence digital circuit chip according to claim 1, it is characterised in that：The Clock Tree (3)
The clock letter of each nodal clock unit (3.2) of the clock signal output terminal connection first layer of middle source clock unit (3.1)
Number input, the clock signal output terminal of each nodal clock unit (3.2) of the first layer connects to be saved corresponding to next layer
The clock signal input terminal of Dot Clock unit (3.2), the clock signal output of each nodal clock unit (3.2) of last layer
The signal input part of end connection respective ends clock unit (3.3).
3. low-power consumption synchronous sequence digital circuit chip according to claim 1 or 2, it is characterised in that：The low-voltage
The supply voltage of power supply (2) is the 55~65% of high-voltage power supply (1) supply voltage.
4. low-power consumption synchronous sequence digital circuit chip according to claim 2, it is characterised in that：The source clock list
First (3.1), each nodal clock unit (3.2) and each end clock unit (3.3) are buffer (3a).
5. low-power consumption synchronous sequence digital circuit chip according to claim 2, it is characterised in that：The source clock list
First (3.1), each nodal clock unit (3.2) and each end clock unit (3.3) form by two phase inverters (3b), its
In, the signal output part of first phase inverter (3b) connects the signal input part of second phase inverter (3b).
6. low-power consumption synchronous sequence digital circuit chip according to claim 4, it is characterised in that：The buffer (3a)
The transistor for being 0.2~0.4V for voltage threshold scope.
7. low-power consumption synchronous sequence digital circuit chip according to claim 5, it is characterised in that：The phase inverter (3b)
The transistor for being 0.2~0.4V for voltage threshold scope.
8. the clock signal generation method of low-power consumption synchronous sequence digital circuit chip, its feature exist described in a kind of claim 1
In it comprises the following steps：
Step 1：Feeder ear, high level to low transition device of the high-voltage power supply (1) to clock signal driver element (4)
(6) high voltage power supply feeder ear, high voltage power supply feeder ear, each register (5) of each low level to high level translator (7)
Feeder ear and each combinational logic circuit unit (8) feeder ear power supply, the LVPS (2) is to source clock unit
(3.1) feeder ear, the height of feeder ear, the feeder ear of each nodal clock unit (3.2) and each end clock unit (3.3)
Level to the low-tension supply of the low-tension supply feeder ear of low transition device (6), each low level to high level translator (7) supplies
Electric end power supply, the supply voltage of high-voltage power supply (1) output are more than the supply voltage of LVPS (2) output；
Step 2：The clock signal of clock signal driver element (4) the output reference amplitude of oscillation, the benchmark amplitude of oscillation are high power supply electricity
The amplitude of pressure, the clock signal of the benchmark amplitude of oscillation are converted to the clock signal of the low amplitude of oscillation by high level to low transition device (6),
High level is to low transition device (6) by the source clock unit (3.1) of the clock signal input of the low amplitude of oscillation to Clock Tree (3)
In；
Step 3：The clock signal of the low amplitude of oscillation is transmitted in above-mentioned Clock Tree (3), by extending step by step, finally by when
By the clock signal transmission of the low amplitude of oscillation, low level to the high level corresponding to turns Zhong Shu (3) each end clock unit (3.3)
In parallel operation (7)；
Step 4：The clock signal of the above-mentioned low amplitude of oscillation received is reduced into by each low level to high level translator (7)
The clock signal of the said reference amplitude of oscillation；
Step 5：Each low level passes the clock signal of the benchmark amplitude of oscillation obtained in step 4 to high level translator (7)
It is defeated by corresponding register (5).
9. the clock signal generation method of low-power consumption synchronous sequence digital circuit chip according to claim 8, its feature
It is：The 55~65% of the clock signal excursion of the amplitude of oscillation on the basis of the clock signal excursion of the low amplitude of oscillation.
10. the clock signal generation method of low-power consumption synchronous sequence digital circuit chip according to claim 9, its feature
It is：Amplitude of oscillation square-like clock signal on the basis of the clock signal of the shown benchmark amplitude of oscillation, the clock signal of the low amplitude of oscillation is low pendulum
Width square-like clock signal.
11. the clock signal generation method of low-power consumption synchronous sequence digital circuit chip according to claim 10, it is special
Sign is：The amplitude of the benchmark amplitude of oscillation square-like clock signal is 1V, and the amplitude of the low amplitude of oscillation square-like clock signal is 0.6V,
The supply voltage of LVPS (2) output is the 60% of the supply voltage of the high-voltage power supply (1) output.
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| CN110134178B (en) * | 2019-04-29 | 2023-04-07 | 中山大学 | Wireless clock tree, method and circuit |
| US11018653B1 (en) | 2020-05-04 | 2021-05-25 | Apple Inc. | Low voltage clock swing tolerant sequential circuits for dynamic power savings |
| CN114236230B (en) * | 2021-12-13 | 2023-10-24 | 广西电网有限责任公司电力科学研究院 | Multi-voltage-domain power consumption optimization and stable power supply design method for power quality chip |
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