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CN103594123A - Non-volatile memory and calibration method thereof - Google Patents

Non-volatile memory and calibration method thereof Download PDF

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CN103594123A
CN103594123A CN201310625597.4A CN201310625597A CN103594123A CN 103594123 A CN103594123 A CN 103594123A CN 201310625597 A CN201310625597 A CN 201310625597A CN 103594123 A CN103594123 A CN 103594123A
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information
volatile memory
current
calibration
calibration information
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CN103594123B (en
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龙爽
陈岚
陈巍巍
杨诗洋
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Abstract

本发明提供了一种非挥发性存储器及其校调方法，包括：配置信息存储单元、控制逻辑单元、测试模式控制模块和检测电路，在传统的非挥发性存储器的电路中加入了检测电路，当非挥发性存储器上电后，检测电路开始工作，实时检测非挥发性存储器的工作状态信息，并根据所述工作状态信息生成对应的校调信息，然后再根据所述校调信息对非挥发性存储器进行校调，由于测试电路不需要连接外部设备输入外部指令，即可实时生成校调信息，从而实现了非挥发性存储器的自动校调，大大节约了测试时间，降低了测试成本。

Figure 201310625597

The invention provides a non-volatile memory and a calibration method thereof, comprising: a configuration information storage unit, a control logic unit, a test mode control module and a detection circuit. The detection circuit is added to the circuit of the traditional non-volatile memory, When the non-volatile memory is powered on, the detection circuit starts to work, detects the working state information of the non-volatile memory in real time, and generates corresponding calibration information according to the working state information, and then adjusts the non-volatile memory according to the calibration information. Since the test circuit does not need to connect external devices to input external instructions, it can generate calibration information in real time, thereby realizing automatic calibration of non-volatile memory, which greatly saves test time and reduces test costs.

Figure 201310625597

Description

Non-volatility memorizer and correcting and regulating method thereof
Technical field
The present invention relates to a kind of non-volatility memorizer and correcting and regulating method thereof, belong to semiconductor memory field.
Background technology
Non-volatility memorizer is owing to being subject to the impact of the factors such as temperature variation of process corner and working environment, its performance can produce a certain amount of skew, be that voltage in non-volatile memory circuit, electric current etc. can change, therefore, need to carry out school tune to non-volatility memorizer, just can make non-volatility memorizer reach initial designs index request.
Traditional non-volatile memory circuit structure as shown in Figure 1, mainly comprises: storage array (Cell Array), configuration information storage unit (NVR), column decode circuitry (X decoder), array decoding circuit (Y decoder), steering logic (Control Logic), inputoutput buffer (IO Buffer), sense amplifier (SA), address buffer (Address Buffer), test pattern control module (Test Mode), electric current and voltage external interface (V/I Monitor) etc.
Traditional non-volatility memorizer is carrying out school timing, must, by the external unit input instruction being connected with electric current and voltage external interface, make non-volatility memorizer enter test pattern and obtain school adjusting information, and then carry out school tune according to the school adjusting information obtaining.This correcting and regulating method needs constantly from outside, to input instruction, and the test duration is long, and testing apparatus and cost of labor are relatively high.
Summary of the invention
For solving the problems of the technologies described above, the invention provides a kind of non-volatility memorizer and correcting and regulating method thereof, in the circuit of traditional non-volatility memorizer, add testing circuit, by testing circuit, detect in real time the work state information of non-volatility memorizer, and generate corresponding school adjusting information according to described work state information, and then according to described school adjusting information, non-volatility memorizer is carried out to school tune, thus having realized the automatic school tune of non-volatility memorizer, technical scheme is as follows:
, comprising: configuration information storage unit, steering logic unit, test pattern control module and testing circuit, wherein:
Described testing circuit is connected with described steering logic unit, for detecting in real time the work state information of non-volatility memorizer, generates corresponding school adjusting information, and export described school adjusting information to steering logic unit according to described work state information;
Described steering logic unit, for described school adjusting information and canonical reference information are compared, when described school adjusting information and canonical reference information are when inconsistent, according to described school adjusting information, non-volatility memorizer is carried out to school tune, wherein, the initial state information that described canonical reference information is described non-volatility memorizer;
Test pattern control module, is stored in described configuration information storage unit for controlling described steering logic unit by described school adjusting information.
Process corner and state of temperature information when preferably, described work state information is non-volatility memorizer work.
Preferably, described steering logic unit, is further used for, when described school adjusting information and canonical reference information are when inconsistent, producing control signal, and described control signal is used for activating described test pattern control module.
Preferably, described school adjusting information is the information of school tune that the electric current in the whole circuit of non-volatility memorizer, voltage, capacitor's capacity or metal-oxide-semiconductor quantity are carried out.
Preferably, described test circuit comprises: the first current source, the second current source, a PMOS pipe, a NMOS pipe, voltage-current converter, current comparator, bank of latches and school adjusting information scrambler, wherein:
The input end of described the first current source is connected with power supply, and the output terminal of described the first current source is connected with the source electrode of a described PMOS pipe, and the drain electrode of a described PMOS pipe is connected with earth terminal, and grid and the drain electrode of a described PMOS pipe are joined;
The input end of described the second current source is connected with power supply, and the output terminal of described the second current source is connected with the drain electrode of a described NMOS pipe, and the source electrode of a described NMOS pipe is connected with earth terminal, and the drain and gate of a described NMOS pipe joins;
A described source electrode for PMOS pipe and the input end of described voltage-current converter are connected, and for the voltage transitions that a described PMOS is managed to source electrode, are the first electric current;
The first input end of described current comparator is connected with the output terminal of described voltage-current converter, the second input end of described current comparator is connected with the grid of a described NMOS pipe, described current comparator is for obtaining n first mirror image current by described the first current ratio mirror image, and the n that the current ratio mirror image in a described NMOS pipe is obtained second image current, and described n first mirror image current compared with described n corresponding the second image current respectively, obtain n comparative result, wherein, n is greater than 2 positive integer;
The input end of described bank of latches is connected with the n of described current comparator output terminal, for latching n comparative result of described current comparator output;
The input end of described school adjusting information scrambler is connected with the output terminal of described bank of latches, and described school adjusting information scrambler is for by the described n comparative result generating digital school adjusting information of encoding, and offers described steering logic unit.
Preferably, described voltage-current converter comprises: the 2nd NMOS pipe and the 2nd PMOS pipe, wherein:
The grid of described the 2nd NMOS pipe is the input end of described voltage-current converter, the source ground of described the 2nd NMOS pipe, described the 2nd NMOS pipe drain electrode is connected with the drain electrode of described the 2nd PMOS pipe, drain electrode and the grid of described the 2nd PMOS pipe join, the output terminal that the grid of described the 2nd PMOS pipe is described voltage-current converter.
Preferably, described current comparator comprises: n PMOS pipe and n NMOS manage, and n is greater than 2 integer, wherein:
The source electrode of n PMOS pipe is all connected with direct supply, and the grid of n PMOS pipe is connected as the first input end of current comparator, and the source electrode of n NMOS pipe is all connected with earth terminal, and the grid of n NMOS pipe is connected as the second input end of current comparator;
The drain electrode of n PMOS pipe is connected as the output terminal of described current comparator with the drain electrode of NMOS pipe corresponding in n NMOS pipe respectively.
, be applied to non-volatility memorizer, comprising:
Detect the work state information of described non-volatility memorizer, and generate corresponding school adjusting information according to described work state information;
More described school adjusting information and canonical reference information, when described school adjusting information and canonical reference information are when inconsistent, be stored in configuration information storage unit by described school adjusting information;
According to described school adjusting information, described non-volatility memorizer is carried out to school tune.
Preferably, also comprise:
Read the school adjusting information in described configuration information storage unit, according to described school adjusting information, non-volatility memorizer is carried out to school tune.
From above technical scheme provided by the invention, non-volatility memorizer provided by the invention and correcting and regulating method thereof, in the circuit of traditional non-volatility memorizer, added testing circuit, after non-volatility memorizer powers on, testing circuit is started working, detect in real time the work state information of non-volatility memorizer, and generate corresponding school adjusting information according to described work state information, and then according to described school adjusting information, non-volatility memorizer is carried out to school tune, because test circuit does not need to connect external unit input external command, can generate in real time school adjusting information, thereby adjust in the automatic school of having realized non-volatility memorizer, greatly saved the test duration, reduced testing cost.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, the accompanying drawing the following describes is only some embodiment that record in the application, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the circuit structure diagram of traditional non-volatility memorizer;
Fig. 2 is the circuit structure diagram of the disclosed non-volatility memorizer of the embodiment of the present invention;
Fig. 3 is the structural drawing of the disclosed testing circuit of the embodiment of the present invention;
Fig. 4 is the process flow diagram of the disclosed correcting and regulating method of the embodiment of the present invention.
Embodiment
In order to make those skilled in the art person understand better the technical scheme in the application, below in conjunction with the accompanying drawing in the embodiment of the present application, technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment is only the application's part embodiment, rather than whole embodiment.Embodiment based in the application, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all should belong to the scope of the application's protection.
The embodiment of the invention discloses a kind of non-volatility memorizer, its circuit structure as shown in Figure 2, comprise: configuration information storage unit 201, steering logic unit 202, test pattern control module 203 and test circuit 204, compare with traditional non-volatility memorizer, it has added test circuit 204 in circuit, and test circuit 204 is connected with steering logic unit 202.
Described test circuit 204, for detecting in real time the work state information of non-volatility memorizer, generates corresponding school adjusting information according to described work state information, and exports described school adjusting information to steering logic unit 202.
Wherein, process corner and state of temperature information when work state information is non-volatility memorizer work, the foundation of school adjusting information and process corner and state of temperature information corresponding relation, be by the breadth length ratio of PMOS pipe P1-Pn reasonable in design and NMOS pipe N1-Nn, make in different process corner different with the school adjusting information under working temperature.
Steering logic unit 202, for high-ranking officers' adjusting information and canonical reference information, compare, when school adjusting information and canonical reference information are when inconsistent, according to school adjusting information, non-volatility memorizer is carried out to school tune, what wherein, canonical reference information was corresponding is the initial state information of non-volatility memorizer.
Steering logic unit 202 is, according to the school adjusting information being stored in steering logic unit internal register, non-volatility memorizer is carried out to school tune.
School adjusting information in register is not longer-term storage, school adjusting information in power-off late register may disappear, therefore, need high-ranking officers' adjusting information to be stored in the configuration information storage unit 201 of non-volatility memorizer, this is because the information in configuration information storage unit 201 can not lost after power-off.After non-volatility memorizer powers on again, the processor in the system of non-volatility memorizer place can read school adjusting information, and according to school adjusting information, non-volatility memorizer be carried out to school tune from described configuration information storage unit 201.
Test pattern control module 203, when described school adjusting information and canonical reference information are when inconsistent, steering logic unit 202 produces control signal and activates test pattern control module 203, make non-volatility memorizer enter test pattern, and control described steering logic unit 202 high-ranking officers' adjusting informations and be stored in configuration information storage unit 201, after having stored, test pattern control module 203 is closed, and non-volatility memorizer exits test pattern.
Certainly, in other embodiments, test pattern control module 203 also has other functions, does not repeat them here.
Adjust in the school to non-volatility memorizer described in arbitrary embodiment disclosed by the invention, is all that the quantity of electric current, voltage, resistance value, capacitor's capacity or metal-oxide-semiconductor in the whole circuit of non-volatility memorizer is carried out to school tune.
The circuit structure of the testing circuit in above-described embodiment as shown in Figure 3, mainly comprises: the first current source 301, the second current source 302, a PMOS pipe Pt, a NMOS pipe Nt, voltage-current converter 303, current comparator 304, bank of latches 305 and school adjusting information scrambler 306.
The input end of the first current source 301 is connected with direct supply, and the output terminal of the first current source 301 is connected with the source electrode of a PMOS pipe Pt, and the drain electrode of a PMOS pipe Pt is connected with earth terminal, and grid and the drain electrode of a PMOS pipe Pt are joined.
The input end of the second current source 302 is connected with power supply, and the output terminal of the second current source 302 is connected with the drain electrode of a NMOS pipe Nt, and the source electrode of a NMOS pipe Nt is connected with earth terminal, and the drain and gate of a NMOS pipe Nt joins.
Concrete, the identical It that is of electric current that the first current source 301 produces with the second current source 302.The one PMOS pipe Pt is identical with the breadth length ratio of a NMOS pipe Nt, and described breadth length ratio is the ratio of channel width with the channel length of MOS device.
When non-volatility memorizer powers on, the flow through source electrode of the described PMOS pipe Pt that connects in diode mode of the output current It of described the first current source 301, the flow through drain electrode of the described NMOS pipe Nt that connects in diode mode of the output current It of described the second current source 302.
Voltage-current converter 303 comprises: the 2nd PMOS pipe P0, the 2nd NMOS pipe N0, wherein, the grid of the 2nd NMOS pipe P0 is the source electrode that the input end of voltage-current converter 303 connects a described PMOS pipe Pt, the source ground of the 2nd NMOS pipe N0, the drain electrode of the 2nd NMOS pipe N0 is connected with the drain electrode of the 2nd PMOS pipe P0, drain electrode and the grid of the 2nd PMOS pipe P0 join, and the grid of the 2nd PMOS pipe P0 is the output terminal of voltage-current converter 303.Voltage-current converter 303 is the first electric current I p0 for the voltage transitions that a described PMOS is managed to source electrode.
Current comparator 304 comprises: n PMOS pipe P1, P2 ... Pn, n NMOS pipe N1, N2 ... Nn, and n is greater than 2 integer.
The source electrode of n PMOS pipe is all connected with direct supply, and the grid of n PMOS pipe is connected as the first input end of current comparator 304, is connected with the output terminal of voltage-current converter 303.
The source electrode of n NMOS pipe is connected with earth terminal, and the grid of n NMOS pipe is connected as the second input end of current comparator 304, is connected with the grid of a described NMOS pipe Nt.
The drain electrode of n PMOS pipe is connected with the drain electrode of n NMOS pipe respectively, the output terminal that is current comparator with points of common connection n NMOS pipe n PMOS pipe.
Concrete, the drain electrode of P1 is connected with the drain electrode of N1, and the drain electrode of P2 is connected with the drain electrode of N2, the like, the drain electrode of Pn is connected with the drain electrode of Nn.
Current comparator 304 is for obtaining n first mirror image current Ip1～Ipn by the first electric current I p0 scaled mirror, wherein, Ip1=k1 * Ip0 ... Ipn=kn * Ip0.
Current comparator 304, also for the electric current I n0 scaled mirror of a NMOS pipe Nt is obtained to n second image current In1～Inn, wherein, In0 is identical with the electric current I t in the second current source 302, In1=M1 * In0, In2=M2 * In0, the like, Inn=Mn * In0, and scale-up factor M1 is determined by the breadth length ratio of P1 and N1, M2 determines by the breadth length ratio of P2 and N2, the like Mn by the breadth length ratio of Pn and Nn, determined.
Current comparator 304 is also for comparing described n first mirror image current respectively with corresponding described n the second image current, i.e. Ip1 and In1, Ip2 and In2 ... Ipn and Inn compare, and obtain n comparative result.
The input end of bank of latches 305 is connected with n output terminal of current comparator 304 respectively, for latching n comparative result of current comparator 304 outputs.
The input end of school adjusting information scrambler 306 is connected with the output terminal of bank of latches 305, for generating digital school adjusting information that a described n comparative result is encoded, and offers described steering logic unit 202.
The non-volatility memorizer that the embodiment of the present invention provides, in the circuit of traditional non-volatility memorizer, add testing circuit, after non-volatility memorizer powers on, testing circuit is started working, detect in real time the work state information of non-volatility memorizer, and generate corresponding school adjusting information according to described work state information, and then according to described school adjusting information, non-volatility memorizer is carried out to school tune, because test circuit does not need to connect external unit input external command, can generate in real time school adjusting information, thereby adjust in the automatic school of having realized non-volatility memorizer, greatly reduced the test duration, reduced testing cost.
The embodiment of the invention also discloses a kind of method that adjust in school, the non-volatility memorizer in application above-described embodiment, the process flow diagram of the method as shown in Figure 4, comprises the following steps:
Step 401: detect the work state information of non-volatility memorizer, and generate corresponding school adjusting information according to described work state information.
After non-volatility memorizer powers on, testing circuit is started working, constantly detect the work state information of non-volatility memorizer, and generate corresponding school adjusting information according to work state information, process corner and state of temperature information when wherein, described work state information is non-volatility memorizer work.
Step 402: more described school adjusting information and canonical reference information, when described school adjusting information and canonical reference information are when inconsistent, be stored in configuration information unit by described school adjusting information.
Wherein, canonical reference information is corresponding to the initial state information of described non-volatility memorizer.When school adjusting information exports to behind steering logic unit, steering logic unit can high-ranking officers' adjusting information and canonical reference information compare, when school adjusting information and canonical reference information are when inconsistent, high-ranking officers' adjusting information is stored in configuration information storage unit.
Step 403: described non-volatility memorizer is carried out to school tune according to described school adjusting information.
When school adjusting information and canonical reference information are when inconsistent, steering logic unit can carry out school tune according to described school adjusting information to described non-volatility memorizer in real time.After power-off, the school adjusting information being stored in configuration information storage unit can not disappear, after again powering on, the processor in steering logic unit or non-volatility memorizer place system can read the school adjusting information in configuration information storage unit, and again carries out school tune according to described school adjusting information.
The disclosed correcting and regulating method of the present embodiment, can detect in real time the work state information of non-volatility memorizer, and generate corresponding school adjusting information according to described work state information, and then according to described school adjusting information, non-volatility memorizer is carried out to school tune, having realized the automatic school of non-volatility memorizer adjusts, greatly saved the test duration, reduced testing cost.
The above is only the application's embodiment; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of the application's principle; can also make some improvements and modifications, these improvements and modifications also should be considered as the application's protection domain.

Claims (9)

1.一种非挥发性存储器，其特征在于，包括：配置信息存储单元、控制逻辑单元、测试模式控制模块和检测电路，其中：1. A non-volatile memory, characterized in that it includes: a configuration information storage unit, a control logic unit, a test mode control module and a detection circuit, wherein: 所述检测电路与所述控制逻辑单元相连，用于实时检测非挥发性存储器的工作状态信息，根据所述工作状态信息生成对应的校调信息，并将所述校调信息输出至控制逻辑单元；The detection circuit is connected to the control logic unit, and is used to detect the working status information of the non-volatile memory in real time, generate corresponding calibration information according to the working status information, and output the calibration information to the control logic unit ; 所述控制逻辑单元，用于将所述校调信息与标准参考信息进行比较，当所述校调信息与标准参考信息不一致时，根据所述校调信息对非挥发性存储器进行校调，其中，所述标准参考信息为所述非挥发性存储器的初始状态信息；The control logic unit is configured to compare the calibration information with standard reference information, and to calibrate the non-volatile memory according to the calibration information when the calibration information is inconsistent with the standard reference information, wherein , the standard reference information is initial state information of the non-volatile memory; 测试模式控制模块，用于控制所述控制逻辑单元将所述校调信息存储于所述配置信息存储单元。A test mode control module, configured to control the control logic unit to store the calibration information in the configuration information storage unit. 2.根据权利要求1所述的非挥发性存储器，其特征在于，所述工作状态信息为非挥发性存储器工作时的工艺角和温度状态信息。2 . The non-volatile memory according to claim 1 , wherein the working state information is process angle and temperature state information when the non-volatile memory is working. 3.根据权利要求1所述的非挥发性存储器，其特征在于，所述控制逻辑单元，进一步用于当所述校调信息与标准参考信息不一致时，产生控制信号，所述控制信号用于激活所述测试模式控制模块。3. The non-volatile memory according to claim 1, wherein the control logic unit is further configured to generate a control signal when the calibration information is inconsistent with the standard reference information, and the control signal is used for activating the test mode control module. 4.根据权利要求1-3任一项所述的非挥发性存储器，其特征在于，所述校调信息是对非挥发性存储器整个电路中的电流、电压、电容容值或MOS管数量进行校调的信息。4. The non-volatile memory according to any one of claims 1-3, wherein the calibration information is the current, voltage, capacitance value or MOS transistor quantity in the entire circuit of the non-volatile memory. calibration information. 5.根据权利要求1所述的非挥发性存储器，其特征在于，所述测试电路包括：第一电流源、第二电流源、第一PMOS管、第一NMOS管、电压-电流转换器、电流比较器、锁存器组和校调信息编码器，其中：5. The non-volatile memory according to claim 1, wherein the test circuit comprises: a first current source, a second current source, a first PMOS transistor, a first NMOS transistor, a voltage-current converter, current comparator, set of latches, and trim information encoder, where: 所述第一电流源的输入端与电源相连，所述第一电流源的输出端与所述第一PMOS管的源极相连，所述第一PMOS管的漏极与接地端相连，所述第一PMOS管的栅极和漏极相接；The input terminal of the first current source is connected to the power supply, the output terminal of the first current source is connected to the source of the first PMOS transistor, the drain of the first PMOS transistor is connected to the ground terminal, and the The gate and the drain of the first PMOS transistor are connected; 所述第二电流源的输入端与电源相连，所述第二电流源的输出端与所述第一NMOS管的漏极相连，所述第一NMOS管的源极与接地端相连，所述第一NMOS管的漏极和栅极相接；The input terminal of the second current source is connected to the power supply, the output terminal of the second current source is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is connected to the ground terminal, and the The drain and the gate of the first NMOS transistor are connected; 所述第一PMOS管的源极与所述电压-电流转换器的输入端相连，用于将所述第一PMOS管源极的电压转换为第一电流；The source of the first PMOS transistor is connected to the input terminal of the voltage-current converter for converting the voltage at the source of the first PMOS transistor into a first current; 所述电流比较器的第一输入端与所述电压-电流转换器的输出端相连，所述电流比较器的第二输入端与所述第一NMOS管的栅极相连，所述电流比较器用于将所述第一电流比例镜像得到n个第一镜像电流，以及将所述第一NMOS管中的电流比例镜像得到的n个第二镜像电流，并将所述n个第一镜像电流分别与对应的所述n个第二镜像电流进行比较，得到n个比较结果，其中，n为大于2的正整数；The first input terminal of the current comparator is connected to the output terminal of the voltage-current converter, the second input terminal of the current comparator is connected to the gate of the first NMOS transistor, and the current comparator is used for Mirroring the first current proportionally to obtain n first mirror currents, and mirroring the current ratio in the first NMOS transistor to obtain n second mirror currents, and dividing the n first mirror currents respectively Comparing with the corresponding n second mirror currents to obtain n comparison results, where n is a positive integer greater than 2; 所述锁存器组的输入端与所述电流比较器的n个输出端相连，用于锁存所述电流比较器输出的n个比较结果；The input terminals of the latch group are connected to the n output terminals of the current comparator, and are used to latch the n comparison results output by the current comparator; 所述校调信息编码器的输入端与所述锁存器组的输出端相连，所述校调信息编码器用于将所述n个比较结果进行编码生成数字校调信息，并提供给所述控制逻辑单元。The input end of the calibration information encoder is connected to the output end of the latch group, and the calibration information encoder is used to encode the n comparison results to generate digital calibration information, and provide it to the control logic unit. 6.根据权利要求5所述的非挥发性存储器，其特征在于，所述电压-电流转换器包括：第二NMOS管和第二PMOS管，其中：6. The non-volatile memory according to claim 5, wherein the voltage-current converter comprises: a second NMOS transistor and a second PMOS transistor, wherein: 所述第二NMOS管的栅极为所述电压-电流转换器的输入端，所述第二NMOS管的源极接地，所述第二NMOS管漏极与所述第二PMOS管的漏极相连，所述第二PMOS管的漏极与栅极相接，所述第二PMOS管的栅极为所述电压-电流转换器的输出端。The gate of the second NMOS transistor is the input terminal of the voltage-current converter, the source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor , the drain of the second PMOS transistor is connected to the gate, and the gate of the second PMOS transistor is the output terminal of the voltage-current converter. 7.根据权利要求6所述的非挥发性存储器，其特征在于，所述电流比较器包括：n个PMOS管和n个NMOS管，且n为大于2的整数，其中：7. The non-volatile memory according to claim 6, wherein the current comparator comprises: n PMOS transistors and n NMOS transistors, and n is an integer greater than 2, wherein: n个PMOS管的源极均与直流电源相连，n个PMOS管的栅极相连作为电流比较器的第一输入端，n个NMOS管的源极均与接地端相连，n个NMOS管的栅极相连作为电流比较器的第二输入端；The sources of the n PMOS transistors are all connected to the DC power supply, the gates of the n PMOS transistors are connected as the first input terminal of the current comparator, the sources of the n NMOS transistors are connected to the ground terminal, and the gates of the n NMOS transistors are connected to the ground terminal. The poles are connected as the second input terminal of the current comparator; n个PMOS管的漏极分别与n个NMOS管中对应的NMOS管的漏极相连作为所述电流比较器的输出端。The drains of the n PMOS transistors are respectively connected to the drains of the corresponding NMOS transistors among the n NMOS transistors as the output terminals of the current comparator. 8.一种校调方法，应用于非挥发性存储器，其特征在于，该方法包括：8. A calibration method applied to a non-volatile memory, characterized in that the method comprises: 检测所述非挥发性存储器的工作状态信息，并依据所述工作状态信息生成对应的校调信息；Detecting the working state information of the non-volatile memory, and generating corresponding calibration information according to the working state information; 比较所述校调信息和标准参考信息，当所述校调信息与标准参考信息不一致时，将所述校调信息存储于配置信息存储单元；comparing the calibration information with standard reference information, and storing the calibration information in a configuration information storage unit when the calibration information is inconsistent with the standard reference information; 根据所述校调信息对所述非挥发性存储器进行校调。The non-volatile memory is calibrated according to the calibrated information. 9.根据权利要求8所述的校调方法，其特征在于，还包括：9. The calibration method according to claim 8, further comprising: 读取所述配置信息存储单元中的校调信息，根据所述校调信息对非挥发性存储器进行校调。Reading the adjustment information in the configuration information storage unit, and adjusting the non-volatile memory according to the adjustment information.
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