CN102866875B - Multioperand adder - Google Patents
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Abstract
The present invention discloses a kind of Universal multi-operand summator, can be used for digital arithmetic to calculate field multiple multidigit binary number and run simultaneously to be added and realize, it is made up of module 110,120 and 130, and module 110 adopts on-off circuit to solve the parallel addition of a multiple bit from configuration aspects, module 120 also solves the addition of 2 one digit numbers and a carry digit by on-off circuit, module 130 is made up of module 110 and 120 etc., complete the carry computation and transmission that exceed operand figure place, first the present invention adopts module 110 to run simultaneously calculating to the operand value corresponding to the power of all positions, then result of calculation to be recombinated every addition number according to position power corresponding relation, and reuse module 110, so until rear each the power of restructuring only has 2 addition numbers, realize carry by module 130 to produce and transmission simultaneously, and finally add in conjunction with 120 acquisitions and, circuit structure of the present invention is simple, design regular, plenty of time expense and hardware spending can be reduced.
Description
Technical field
The invention belongs to electronic technology field and field of computer architecture, be realize all bit parallels of multiple operand to be added and the synchronous adding circuit producing each weights position carry and final sum, can be widely used in the arithmetic unit of all kinds of microprocessor, digital signal processor and some special-purposes.
Background technology
Totalizer both can realize additive operation also can realize subtraction, the basic building block of multiplier and divider is become as basic arithmetic operation unit, direct impact and determine cost, the arithmetic speed and operational precision etc. of the computing circuit such as multiplier and divider, and then determine performance and the cost of the large-scale dedicated system such as all kinds of microprocessor and digital signal processor.
In the past few decades, totalizer obtains scholar, scientific research personnel's enough attention and further investigation, also obtain widespread use.In totalizer family, 2 operand binary adders especially seem important, have occurred a large amount of relevant achievement in research.These achievements mainly can be summarized as chain carry totalizer (Ripple-CarryAdder), carry-skip adder (Carry-SkipAdder), carry lookahead adder (Carry-Look-AheadAdder), conditional-sum adder (Conditional-SumAdder), carry-select adder (Carry-SelectAdder) and carry save adder (Carry-SaveAdder) according to project organization, and the various totalizer variants etc. proposed through the improvement to various totalizer above.Moreover, also have the totalizer adopting Manchester carry chain, adopt the totalizer of self synchronization circuit, adopt the totalizer of differential cascade switching voltage logic, and adopt totalizer of selection circuit etc.As: in Chinese invention patent No. 200610127132.6 (publication number CN101140511A), disclose one " cascaded carry binary adder ".This invention is the adding circuit based on Ripple structure, have modified the carry generating circuit in carry propagate circuit, and with even number, Data Placement is become different units according to odd number, to use the used time that different carry generating circuits too much increases to reduce gate circuit progression.One " XOR carry generator and use its condition-selecting adder and method " is disclosed in No. 02140712.6th, Chinese invention patent (publication number CN101432907).This invention is that a kind of condition selects binary adder, realizes carry select and add and select by segmentation and selector switch.But in carry select, use low order carry to cause the used time to increase as alternative condition because existing.One " method of the carry logic circuits that binary adder and production wherein use " is disclosed in No. 200310101005.5th, Chinese invention patent (publication number CN1497428).This invention synchronously generate different pieces of information section to be low order carry add with 1 and 0 respectively and, and produced the carry value of each data segment by carry generating portion, select finally to add and result.This invention decreases the critical path that carry produces, and shorten time delay, but circuit is still very complicated.One " carry save adder and system thereof " is disclosed in No. 200410064426.Xth, Chinese invention patent (publication number CN1614553A).This invention comprises the logical block being coupled to high-order full adder, by when generating carry in prime instead of previous stage, decreases the delay of the input position being input to high-order full adder, thus reduces the delay that high-order full adder exports summation and carry.It is large equally to there is hardware spending in this invention, and time delay is many.
Also current totalizer achievement in research can be divided into numeric addition device and symbolic number totalizer according to numerical value expression form.The structural type totalizer introduced above mainly belongs to numeric addition device, and for symbolic number totalizer, mainly contains redundant symbol number addition electrical equipment and hybrid digital totalizer etc.They still postpone excessive, and hardware spending is higher.
When people cannot find breakthrough from theoretical analysis, computational algorithm and project organization, some researchists also attempt from design technology, it is desirable to find new discovery.So in succession there is employing ECL technique, static CMOS technology, the totalizer etc. that dynamic CMOS technique and BiCMOS technique etc. make, but effect not obvious.
Even to this day, deliver with paper form and all could not solve the problem such as too much hardware spending and carry time delay very well with the totalizer of patent form application, cause the totalizer more than 64 to lose practical value in hardware spending and time delay.The present invention also proposes a kind of 2 operand binary adders.This totalizer hardware spending is little, is directly proportional to addition number figure place; This totalizer is few for computing time, only needs the used time of 3 gate circuits, with addition number figure place have nothing to do, be easily extended to 128,256, even higher.Thus say, the invention solves the problem such as too much hardware spending and carry time delay that current 2 operand binary adders run into.
Be added for multiple operand, multiple numbers that the current scheme generally used is main or traditional are added between two successively.Although this hardware spending is little, operation time is short, once addition number quantity is more, it amounts to the used time will be very large.Such as: even if use 2 number parallel synchronous totalizers proposed by the invention to add up to 256 operands, its total used time also needs (256-1) × 3=765 gate circuit used time.Visible, it is not desirable selection for the addition of more operand that multiple number is added scheme between two successively.
Be added in document at existing multiple operand, also have the scheme that employing is first compressed, rear use 2 number parallel synchronous is added.This scheme not only causes used time and hardware spending comparatively large because each adopts multistage compressor, and also because using 2 number parallel synchronous to be added and Shortcomings on final sum calculates.In addition, need to add up to partial product in mlultiplying circuit implementation procedure, this also becomes separates a kind of approach that current multiple operand is added development situation.In mlultiplying circuit, partial product adds up scheme mainly repeat array (IterativeArray, be called for short IA), Wallace tree construction and BoothEncoding structure, and their mutation etc.Although IA structure compound with regular structure, be easy to layout design, speed is the slowest.Wallace tree construction mainly adopts carry save adder (CSA) computing method and Wallace to set structural texture, decreases the compression number of plies compared with IA structure.Such scheme realizes because being unsuitable for high bit number multiplication along with operand figure place increase meeting index increase hardware spending or operation use time.BoothEncoding structure mainly adopt the synchronous calculating section of the mode of coding and, but can not accomplish that all operations number is run simultaneously addition, still need repeatedly loop computation, too much add operation time.
From upper surface analysis, current multioperand adder also needs further further investigation, needs to form simple and practical design proposal.The present invention not only proposes multiple one digit number adding circuit and 2 operand parallel synchronous addition devices, also proposed Universal multi-operand summator.These inventions not only solve parallel synchronous operational problem, reduce hardware spending, reduce and calculate the used time, also make circuit structure regular, are easy to realize.
Summary of the invention
The invention discloses a kind of Universal multi-operand summator, be solve multiple multidigit binary number to run simultaneously cumulative scheme, mainly comprise the adder circuit of running simultaneously of multioperand identical weights bit value adder circuit, carry synthetic circuit and 2 operands.Wherein, multioperand identical weights bit value adder circuit is the totalizer realizing the addition of multiple one digit number.First it adopt switch matrix to add up the number of high level in multiple one digit number (as " 1 ") or low level (as " 0 "), and then use on-off circuit acquisition to add and result.Whole process only needs the time of 2 basic gate circuits.The adder circuit of running simultaneously of 2 operands is a kind of 2 operand adder, each bit value in addition 2 operands that can walk abreast, the issuable carry value of everybody low level all with it entirety of synchronization gain, and finally added simultaneously and circuit.It first by on-off circuit obtain everybody 2 addition numbers and, and obtain the possible carry numerical value to a high position by on-off circuit and carry propagate Channel Synchronous, finally by on-off circuit to everybody 2 numbers be added one's own department or units and and possible carry value from low level be added, obtain simultaneously each finally add with.Whole additive process only needs the time of 3 basic gate circuits.Carry synthetic circuit to be run simultaneously adder circuit composition primarily of multioperand identical weights bit value adder circuit and 2 operands, for completing the generation of all carries exceeding operand figure place, transmission and addition, can't introduce extra operation time.
Multioperand identical weights bit value adder circuit is made up of statistical circuit and coding circuit.Statistical circuit is added up the number of " 0 " and " 1 " in multiple input data, and coding circuit then can be encoded to the statistics of shape as " 0 " and continuous " 1 " forms continuously, acquisition one's own department or unit and with high-order carry.
2 operands run simultaneously adder circuit by statistical coding module, carry generate transport module with add and select module to form.Statistical coding module is added up low and high level in two numbers be added and encodes, obtain one's own department or unit and with accurate carry, and to provide addition two number be not the signal wire of " 0 " entirely; Carry generates the accurate carry of transport module process and low order carry, realizes accurate carry and produces carry for time " 1 ", for determining whether to transmit the carry from low level according to signal wire time " 0 "; Add and select module to select to determine final sum by one's own department or unit with low order carry.
Carry synthetic circuit achieves the carry value exceeding operand figure place and calculates, the perfect operation independent function of multioperand adder, do not introduce in expense situation extra time can adopt different multioperands identical weights bit value adder circuit flexibly, 2 operands run simultaneously adder circuit, and add and select the circuit such as module.
When the parallel synchronous for n m positional operand is added, wherein n and m be not less than 1 natural number, first totalizer of the present invention carries out parallel addition to the value corresponding to each power of n m positional operand by the adder circuit of the identical weights bit value of n operand, the addition obtaining n numerical value of each power and position with and
position carry value, each the addition number of then all result of calculations of m position being recombinated according to position power corresponding relation.Now addition number has
+ 1.Then, this general totalizer uses
the adder circuit of the identical weights bit value of+1 operand is to this
+ 1 addend carries out parallel cumulative again, and each the addition number of again recombinating according to position power corresponding relation to accumulation result, so until after restructuring each power only have 2 operands to be added.Meanwhile, for the carry more than m position, corresponding multiple one digit number adding circuits are adopted to reduce addition number according to the quantity of identical bits power addition number in the reassembled.Finally, the present invention completes 2 last operands by the adder circuit of running simultaneously of 2 operands and is added, and obtains n the final cumulative sum of m positional operand.
Carrying out in parallel synchronous sum operation to n m positional operand, repeatedly using multiple one digit number totalizer, and to operation result according to position weight Combination nova, to gradually reduce addition number quantity.In addition, multioperand identical weights bit value adder circuit is not the totalizer of a fixing operation number, but the general designation being not less than the one column adder of 2 operands that a class is made up of statistical circuit and coding circuit.
This Universal multi-operand summator is not only added for multiple operand, can also be applied in a variety of computing circuits such as complement addition, subtraction and multiplication.
Based on foregoing invention description of contents and the specific embodiment that provides of accompanying drawing subsequently, compared with prior art, the present invention is owing to adopting Regular Circuit, utilize on-off element, by interpretative version of running simultaneously, thus solve multiple multi-position action number and be difficult to cumulative problem of running simultaneously, not only reduce hardware spending and used time expense, also add the extensibility of circuit, such as 64 64 figure places add up, both can be implemented in only increase hardware spending and do not increase the used time when expand to 65 to 127 64 figure places add up, also the cumulative of 64 numbers more than 64 is realized can not increase used time situation only increasing hardware spending under.
By reading content of the present invention, combining innovation etc. pointed in the description of the drawings below and claims, those skilled in the art can have clearer understanding and understanding to above-mentioned content relevant with other of the present invention and target, some advantages of the present invention and new application may be there is do not provide at this, but still wish to be included in the limited range of following claims.
In order to complete understanding is at technology contents of the present invention, be described in further detail below in conjunction with accompanying drawing.
Accompanying drawing explanation
Fig. 1 is functional-block diagram of the present invention;
Fig. 2 is multiple operand of the present invention identical weights bit value adder circuit schematic diagram;
Fig. 3 is the schematic diagram of selector switch in the present invention;
Fig. 4 is the schematic diagram of tandem tap in the present invention;
Fig. 5 is the schematic diagram of two 1 bit adding circuits of the present invention;
Fig. 6 is that two multidigit binary numbers of the present invention are run simultaneously the schematic diagram of adding circuit;
Fig. 7 is that multiple multi-position action number is run simultaneously totalizer schematic diagram.
Embodiment
Hereinafter, with reference to accompanying drawing, the preferred embodiments of the present invention are described in detail.Described by note that hereafter is representative embodiment of the present invention, and should not be limited to following description when understanding of the present invention.
Fig. 1 is functional-block diagram of the present invention.It forms primarily of the adder Module 120 of adder Module 110,2 bits of a multiple bit and carry integration module 130.First this invention adopts module 110 to run simultaneously calculating to all operations number numerical value corresponding to each power, then the result of calculation of all positions to be recombinated every addition number according to position power corresponding relation, and reuse module 110, so until rear each the power of restructuring only has 2 addition numbers.Meanwhile, realize carry process higher than operand figure place and transmission by module 130, and binding modules 120 processes 2 last operands is added, run simultaneously obtain finally add and.
Module 110 adopts on-off circuit to solve adding up problem while a multiple bit from configuration aspects, instead of traditional interpretative version be made up of gate circuit, and its used time only needs used time of 2 gate circuits, to have nothing to do with addition number number; Its hardware spending is also only directly proportional to addition number number square, avoids higher-index relation.
Fig. 2 is multiple operand of the present invention identical weights bit value adder circuit specific embodiment, and namely module 110 is directed to the cumulative specific embodiment of 8 one digit numbers.To note when Understanding Module 110: module 110 adds up about multiple one digit number simultaneously, not only represent 8 one digit numbers and add up, also represent more than 2 one digit numbers and add up.Fig. 2 just adds up 8 one digit numbers and carrys out the principle of work of specification module 110 as specific embodiment, and not talkative module 110 is exactly the totalizer of 8 one digit numbers, or the totalizer of 8 one digit numbers is exactly module 110.
As can be seen from Figure 2, these 8 one digit number summation circuits have 8 input end ai_0 ~ ai_7, and 4 output terminal yi_0 ~ yi_3 are divided into module 111 and 112.Module 111 is statistical circuits, for adding up the number of " 0 " and " 1 " in summarized information.In module 111, when ai_0 input low level, all selector switch si_00 ~ si_07 selects left side port, and now si_07 selects directly to connect low level, si_07 output low level, shows there is a low level input in ai_0 ~ ai_7.When ai_0 input high level, all selector switch si_00 ~ si_07 selects the right port, and now si_00 selects directly to connect high level, and si_00 exports high level, shows there is a high level input in ai_0 ~ ai_7.As one group of input data { 01010101 } is added to port ai_0 ~ ai_7 simultaneously, then selector switch si_00 ~ si_07 selects left side port, ensure that si_07 receives low level, selector switch si_10 ~ si_16 selects the right port, ensures that si_00 receives high level by si_10.The like, last si_03 ~ si_07 output low level, si_00 ~ si_03 exports high level, has 4 contiguous ports and exports high level, corresponding with input data.Equally, as one group of input data { 11010111 } is added to port ai_0 ~ ai_7, then si_06 and si_07 output low level simultaneously, si_00 ~ si_05 exports high level, has 6 contiguous ports and exports high level.Obviously, have how many " 1 " in input data, from si_00 to si_07, just have how many continuous switches to be high level simultaneously.Si_00 is that low level then illustrates that input data are low level entirely, and si_07 is that high level then illustrates that input data are high level entirely.
Be coding circuit in module 112, on-off circuit can be used to encode according to the output level of si_00 ~ si_07.As: ensure that lowest order yi_0 is for " 1 ", si_00 and si_01 or si_02 and si_03 or si_04 and si_05 or si_06 and si_07 must be met for " 1 " and " 0 ", namely in si_00 ~ si_07, have odd number " 1 ".The tandem tap circuit that the present invention proposes can realize this function.In figure, " K-" represents the switch of Low level effective, and " K+ " represents the effective switch of high level.When si_00 and si_01 or si_02 and si_03 or si_04 and si_05 or si_06 and si_07 is " 1 " and " 0 ", switch conduction, yi_0 directly receives positive source, ensure as " 1 ", and when not having a pair to be " 1 " and " 0 " in them, switch by, yi_0 is defined as low level " 0 " by pull down resistor.Yi_1 with yi_2 also adopts on-off circuit to realize according to logical relation as yi_0, only has yi_3 directly to adopt si_07 to export.This is because only when addition number is 8 " 1 ", corresponding output encoder is " 1000 ", and it is high level that si_07 exports; For other situation, it is low level that si_07 exports, and yi_3 is also low level.
In fig. 2, have employed on-off circuit, tandem tap in the composition selection circuit of switch matrix and module 112 can be made with different materials, requires and applied environment, such as atom switch, quantum switch, photon switch, transistor switch and electric switch etc. as long as meet switch designs.Fig. 3 and Fig. 4 is a specific embodiment of selection circuit and tandem tap respectively, and they have employed metal-oxide-semiconductor design, but this does not represent the present invention and only uses this type of switch.As long as can inventive concept be implemented, no matter use which kind of fret switch all to belong to scope.The switch that the present invention uses should have following features: once switch conduction, signal can transmit at a terrific speed, such as metal-oxide-semiconductor switch, and conducting resistance is infinitely small, and conduction path is as metallic conductor; Once switch disconnects, signal transmission is difficult to pass through, such as metal-oxide-semiconductor switch, and off resistance is infinitely great, and electric current is very little.
In figure 3, Q
1and Q
2for 2 metal-oxide-semiconductors of symmetry.When control end ai is low level, Q
2conducting, port 3 is connected with 1; When control end ai is high level, Q
1conducting, port 2 is connected with 1.
In the diagram, Q
3and Q
4for 2 metal-oxide-semiconductors of symmetry.When control end 1 is low level, Q
4conducting; When control end 2 is high level, Q
3conducting.
Here remark additionally, current semiconductor process can to have produced between drain-source pole conducting resistance much smaller than the metal-oxide-semiconductor of 1 Ω, as good conductor between drain-source pole.When metal-oxide-semiconductor grid level changes, grid needs just can reach stable level certain Time Created, and then conducting between drain-source pole, is equivalent to conductor path.
In Fig. 5, be the embodiment of the adding circuit of two 1 bit band carries, generated transport module 122 by statistical coding module 121, carry and added and select module 123 to form.First statistical coding module 121 is added up the level in addend ai and bi by selector switch.If the output that the output of Si_00 is high level Si_01 is low level, illustrate in addend to only have a high level; If the output of Si_01 and Si_00 is all high level, show that addend and summand are all high level.Like this, the output of Si_00, i.e. mi are low levels, then illustrate that addition two number is all low level; The output of Si_01, i.e. zi_1 are that high level then shows that addition two number is all high level.Then, module 121 by K switch-and K+ encode, obtain two number be added one's own department or unit and zi_0, namely in the middle of and.The carry that two numbers are added, is defined the carry that is as the criterion, directly can uses the output of selector switch Si_01, i.e. zi_1.Can find out, module 121 needs the time of 2 gate circuits namely can complete coding.
Module 122 is for carry production and transfer, its design concept is as follows: 1. when two addition numbers are all high level, Cout to high position power carry is high level, have nothing to do with from low order carry Cin, therefore accurate carry zi_1 can be adopted to control to receive the switch of positive source, to ensure to high-order carry; 2., when only having one to be high level in two addition numbers, the low level of zi_1 and the high level of mi is used to control the switches of two series connection respectively, to guarantee that carry value Cout is determined by low order carry Cin.If Cin is high level, then Cout is high level, represents carry, otherwise represents no-carry.Here it should be noted that once switch conduction, be equivalent to conductor between Cout and Cin two end points, can think without time delay.3., when two addition numbers are all low level, no matter what value, no-carry Cin is, also namely Cout must be low level.Two the input switch branch roads be connected with Cout in the present invention are all disconnect, and Cout is no longer subject to VCC and Cin impact, and Cout is low level to adopt pull down resistor to guarantee.Module 122 works with the coded portion in module 121 simultaneously, all only needs the time of 1 gate circuit, and therefore the generation of carry and transmission do not take extra time.
Module 123 generates for final sum, selects final sum result by on-off circuit.When zi_0 and Cin is 0 and 1, or when 1 and 0, in upper and lower 2 tandem tap groups, always there is one group of conducting, final sum Si receives positive source by switch, represents and exports high level, in other situations, the not conductings of upper and lower 2 tandem tap groups, Si is restricted to low level by pull down resistor.This module needs 1 gate circuit used time.In addition 2 gate circuit used times of module 121, these two one digit number totalizers with carry need 3 gate circuit used times altogether.
2 multidigit addition of binary number implement body embodiments based on module 120 are shown in Fig. 6, and this is aimed at the adder circuit of 2 64 bits.In the 1st gate circuit used time, 2 addition numbers of all positions are added to the input end of circuit, and the output terminal of selection matrix exports statistics in respective modules 121; In the 2nd gate circuit used time, be on the one hand that module 122 that each is corresponding produces may carry to high position transmission, be that in module 121, coding circuit produces coding result on the other hand, be namely added 2 numbers centres and; In the 3rd gate circuit used time, middle and jointly obtained by selection circuit with low order carry and finally add and result.
Such as: two addition numbers are 64 continuous print " 1 " and " 0 " respectively, and carry value Cin is " 1 ", and after the 1st gate circuit used time, zi_1 is " 0 ", and mi is " 1 ", here i ∈ [0,63]; After the 2nd gate circuit used time, zi_0 is " 1 ", simultaneously because zi_1 is " 0 ", mi is " 1 ", cause all switches conducting simultaneously path from Cin to Cout, " 1 " of Cin end along path to most significant digit fast transport, and makes the carry of every be all " 1 "; After the 3rd gate circuit used time, because zi_0 and low order carry value are all " 1 ", thus export Si and be restricted to " 0 " by pull down resistor, most significant digit carry value is " 1 " simultaneously.Like this, result of calculation is exactly 1 " 1 " and 64 continuous print " 0 ".
Fig. 6 is only an embodiment, for other not isotopic number two number be added, only need swap modules 120, its operation use time also only needs 3 gate circuit used times, be added two number figure places have nothing to do.
Fig. 7 is that n of the present invention m positional operand is run simultaneously the specific embodiment of totalizer.This embodiment selects 8 16 bits to run simultaneously addition, both gives extended mode, and in turn gives independent addition calculation scheme.This embodiment comprises four working linings, and ground floor is made up of 16 modules 110.This module completes the coding of each 8 addition number, obtains corresponding one's own department or unit and Yi_0 and 3 carry value Yi_3, Yi_2 and Yi_1 to high-order carry.The second layer is by 18 module compositions, and they are the module 121 of most significant digit, secondary high-order module 110 and remaining 16 equal modules 110 respectively.Low 16 modules 110 are not only structurally distinguished to some extent with ground floor module 110, functionally also different, complete the coding of each 4 addition number, obtain corresponding one's own department or unit and Xi_0 and 2 carry value Xi_2 and Xi_1 to high-order carry.17th module 110 is also different with low 16 modules 110, completes the coding of the 17th 3 addition numbers, obtains corresponding one's own department or unit and X16_0 and carry value X16_1.The module 121 of most significant digit completes the coding of the 18th 2 addition numbers, obtains corresponding one's own department or unit and X17_0 and carry value X17_1.The input number of the second layer, namely the addition number of every not only arranges by the Output rusults of ground floor the array one-tenth obtained according to identical power and position, and the carry digit Y-3_3 introduced according to expanded function by low level in addition, Y-2_3, Y-2_2, Y-1_3, Y-1_2 and Y-1_1 form.In addition, in order to complete expanded function, 6 of ground floor export Y13_3, Y14_3, Y14_2, Y15_3, Y15_2 and Y15_1 and are drawn.
Third layer is by 19 module compositions, and they are the module 121 low level module 110 identical with 18 of most significant digit respectively.Low 18 modules 110 have been codings of every 3 addition numbers, obtain corresponding one's own department or unit and Ri_0 and carry value Ri_1.The module 121 of most significant digit completes the coding of the 19th 2 addition numbers, obtains corresponding one's own department or unit and R18_0 and carry value R18_1.The input number of third layer, namely the addition number of every not only arranges by the Output rusults of the second layer array one-tenth obtained according to identical power and position, and the carry digit X-2_2, X-1_2 and X-1_1 that are introduced according to expanded function by low level in addition form.In addition, in order to complete expanded function, 3 of the second layer export X14_2, X15_2 and X15_1 and are drawn.
4th layer by 20 module compositions, they are the module 123 low level module 120 identical with 19 of most significant digit respectively.19 low level modules 120 have been additions of every 2 addition numbers and carry value, to obtain final sum.The module 123 of most significant digit is for completing being added of time high-order carry value and third layer most significant digit carry value.Here module 123 why is adopted, instead of module 120 or module 110, reason is that the net result that 8 16 figure places are added can not more than 20, and that is, an addend of the 20th is added can not produces carry with the carry value of low level.The input number of the 4th layer, namely the addition number of every not only arranges by the Output rusults of third layer the array one-tenth obtained according to identical power and position, and the carry digit R-1_1 introduced according to expanded function by low level in addition forms.In addition, in order to complete expanded function, 1 of third layer exports R15_1 and is drawn.
For the 4th layer, in order to complete expanded function, adding carry input Cin at lowest order, adding carry output Cout at the 16th.
Consider independent addition calculation demand, namely the totalizer of these 8 16 bits belongs to most significant digit summation module, what its every one deck produced does not need directly to send higher than the carry of the 16th, but directly process in this inside modules and export, this treatment circuit is exactly carry integration module 130.Module 130 is made up of multiple module 110,120,121 and 123, is not increasing each layer carry data addition calculation completing more than the 16th in extra used time situation.
Fig. 7 shows, each working lining from ground floor to third layer needs 2 gate circuit used times, and only 3 gate circuit used times of the 4th layer of needs, visible, and only 9 gate circuit used times can complete 8 16 figure places additions.Can release from the present invention, the summarized information figure place in limited range does not affect the used time of adding circuit.The circuit used time of the present invention is only relevant with addition operand number, and as 4 ~ 7 operands need 7 gate circuit used times, 8 ~ 255 operands need 9 gate circuit used times, and more than 256 operands also only need more than 11 gate circuit used times.Hardware spending of the present invention, when not considering carry integration module 130, was both directly proportional to operand figure place, was also directly proportional to operand number square.
Although what Fig. 7 provided is, 8 16 bits are run simultaneously adder circuit, it is only that multiple multi-position action number of the present invention is run simultaneously a specific embodiment of totalizer.The present invention is not limited in 8 16 bits and runs simultaneously addition, to run simultaneously addition, can adopt flesh and blood of the present invention for any n m bit.
Although the present invention describes multiple multi-position action number to run simultaneously addition implementation, but it is also applicable in a variety of computing circuits such as complement addition, subtraction and multiplication, if the present invention put forward module and carry out reasonable combination and amendment just can realize the function that a lot of the present invention do not mentioned.
Although describe the present invention by describing specific embodiment of the present invention, should be understood that, the people being proficient in this area still can carry out the various amendments in pro forma and details to the present invention, and does not depart from the spirit and scope of the present invention.
Claims (8)
1. a multioperand adder, it is characterized in that, described totalizer mainly comprises multioperand identical weights bit value adder circuit, carry synthetic circuit and 2 operands are run simultaneously adder circuit, multioperand identical weights bit value adder circuit is the totalizer realizing the addition of multiple one digit number, first it adopt switch matrix to add up the number of high level " 1 " or low level " 0 " in multiple addition one digit number, and then use switch matrix acquisition to add and result, whole process only needs the time of 2 basic gate circuits, 2 operands adder circuit of running simultaneously is a kind of 2 operand adder, can be walked abreast each bit value in addition 2 operands, the overall issuable carry value of everybody and all low levels thereof of synchronization gain, and finally added simultaneously and circuit, it first by on-off circuit obtain everybody 2 addition numbers and, and obtain the possible carry numerical value to a high position by on-off circuit and carry propagate Channel Synchronous, finally by on-off circuit to everybody 2 numbers be added one's own department or units and and possible carry value from low level be added, obtain simultaneously each finally add and, whole additive process only needs the time of 3 basic gate circuits, carry synthetic circuit is made up of multioperand identical weights bit value adder circuit and 2 operands adder circuit of running simultaneously, for completing the generation of all carries exceeding operand figure place, transmission and addition, extra operation time can't be introduced, its calculating process comprises four working linings, ground floor is made up of 16 modules 110, this module completes the coding of each 8 addition number, obtain corresponding one's own department or unit and Yi_0 and 3 carry value Yi_3 to high-order carry, Yi_2 and Yi_1, the second layer is by 18 module compositions, they are the module 121 of most significant digit respectively, secondary high-order module 110 and remaining 16 equal modules 110, low 16 modules 110 are not only structurally distinguished to some extent with ground floor module 110, functionally also different, complete the coding of each 4 addition number, obtain corresponding one's own department or unit and Xi_0 and 2 carry value Xi_2 and Xi_1 to high-order carry, 17th module 110 is also different with low 16 modules 110, complete the coding of the 17th 3 addition numbers, obtain corresponding one's own department or unit and X16_0 and carry value X16_1, the module 121 of most significant digit completes the coding of the 18th 2 addition numbers, obtain corresponding one's own department or unit and X17_0 and carry value X17_1, the input number of the second layer, namely the addition number of every not only arranges by the Output rusults of ground floor the array one-tenth obtained according to identical power and position, the carry digit Y-3_3 introduced according to expanded function by low level in addition, Y-2_3, Y-2_2, Y-1_3, Y-1_2 and Y-1_1 forms, in addition, in order to complete expanded function, 6 of ground floor export Y13_3, Y14_3, Y14_2, Y15_3, Y15_2 and Y15_1 is drawn, third layer is by 19 module compositions, they are the module 121 low level module 110 identical with 18 of most significant digit respectively, low 18 modules 110 have been codings of every 3 addition numbers, obtain corresponding one's own department or unit and Ri_0 and carry value Ri_1, the module 121 of most significant digit completes the coding of the 19th 2 addition numbers, obtain corresponding one's own department or unit and R18_0 and carry value R18_1, the input number of third layer, namely the addition number of every not only arranges by the Output rusults of the second layer array one-tenth obtained according to identical power and position, the carry digit X-2_2 introduced according to expanded function by low level in addition, X-1_2 and X-1_1 forms, in addition, in order to complete expanded function, 3 of the second layer export X14_2, X15_2 and X15_1 is drawn, 4th layer by 20 module compositions, they are the module 123 low level module 120 identical with 19 of most significant digit respectively, 19 low level modules 120 have been additions of every 2 addition numbers and carry value, to obtain final sum, the module 123 of most significant digit is for completing being added of time high-order carry value and third layer most significant digit carry value, here module 123 why is adopted, instead of module 120 or module 110, reason is that the net result that 8 16 figure places are added can not more than 20, that is, an addend of the 20th is added can not produces carry with the carry value of low level, the input number of the 4th layer, namely the addition number of every not only arranges by the Output rusults of third layer the array one-tenth obtained according to identical power and position, the carry digit R-1_1 introduced according to expanded function by low level in addition forms, in addition, in order to complete expanded function, 1 of third layer exports R15_1 and is drawn, for the 4th layer, in order to complete expanded function, carry input Cin is added at lowest order, carry output Cout is added at the 16th, what its every one deck produced does not need directly to send higher than the carry of the 16th, but directly process in this treatment circuit inside and export, this treatment circuit is exactly carry integration module 130, module 130 is by multiple module 110, 120, 121 and 123 compositions, do not increasing each layer carry data addition calculation completing more than the 16th in extra used time situation.
2. multioperand adder according to claim 1, it is characterized in that: described multioperand identical weights bit value adder circuit is made up of statistical circuit and coding circuit, statistical circuit is added up the number of " 0 " and " 1 " in multiple input data, coding circuit then can to shape as continuously " 0 " and " 1 " forms continuously statistics be encoded, acquisition one's own department or unit and with high-order carry.
3. multioperand adder according to claim 1, it is characterized in that: 2 described operands run simultaneously adder circuit by statistical coding module, carry generate transport module with add and select module to form, statistical coding module is added up low and high level in two numbers be added and encodes, obtain one's own department or unit and with accurate carry, and to provide addition two number be not the signal wire of " 0 " entirely; Carry generates the accurate carry of transport module process and low order carry, realizes accurate carry and produces carry for time " 1 ", for determining whether to transmit the carry from low level according to signal wire time " 0 "; Add and select module to select to determine final sum by one's own department or unit with low order carry.
4. multioperand adder according to claim 1, it is characterized in that: described carry synthetic circuit achieves the carry value exceeding operand figure place and calculates, the perfect operation independent function of multioperand adder, do not introduce in expense situation extra time can adopt different multioperands identical weights bit value adder circuit flexibly, 2 operands run simultaneously adder circuit, and add and select modular circuit.
5. multioperand adder according to claim 1, is characterized in that have employed on-off circuit, as long as meet the switch that switch designs requires and applied environment just can select different materials to make.
6. multioperand adder according to claim 1, is characterized in that, can realize n m positional operand and carry out parallel synchronous addition.
7. multioperand adder according to claim 1, is characterized in that repeatedly using multiple one digit number totalizer, and to operation result according to position weight Combination nova, to gradually reduce addition number quantity.
8. multioperand adder according to claim 1, it is characterized in that multioperand identical weights bit value adder circuit is not the totalizer of a fixing operation number, but the general designation being not less than the one column adder of 2 operands that a class is made up of statistical circuit and coding circuit.
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| CN103345378B (en) * | 2013-07-03 | 2016-08-24 | 刘杰 | Three addend binary parallel synchronous addition devices |
| CN103324461B (en) * | 2013-07-03 | 2015-12-23 | 刘杰 | Four addend binary parallel synchronous addition devices |
| CN103885745B (en) * | 2013-08-17 | 2017-03-08 | 刘杰 | The general design method of more than 5 addend parallel synchronous adders |
| US9703531B2 (en) * | 2015-11-12 | 2017-07-11 | Arm Limited | Multiplication of first and second operands using redundant representation |
| CN108733408A (en) * | 2017-04-21 | 2018-11-02 | 上海寒武纪信息科技有限公司 | Counting device and method of counting |
| CN110427169B (en) * | 2019-07-12 | 2021-07-02 | 东南大学 | A Three-layer Configurable Approximate Bit Width Adder for Artificial Neural Networks |
| CN111258538B (en) * | 2020-01-13 | 2023-07-21 | 电子科技大学 | A FPGA-based high-performance adder circuit with large bit width |
| CN111694541B (en) * | 2020-05-06 | 2023-04-21 | 常熟理工学院 | Base 32 operation circuit for number theory transformation multiplication |
| CN111694540B (en) * | 2020-05-06 | 2023-04-21 | 常熟理工学院 | A radix-64 arithmetic circuit for number-theoretic transformation and multiplication |
| CN111931441B (en) * | 2020-07-14 | 2024-06-11 | 深圳市紫光同创电子有限公司 | Method, device and medium for establishing FPGA fast carry chain time sequence model |
| CN113268219B (en) * | 2021-07-19 | 2021-10-19 | 中科南京智能技术研究院 | Adder circuit with binary complement conversion |
| CN113419704B (en) * | 2021-07-23 | 2024-08-02 | 杭州缘及科技有限公司 | 49-Bit adder and implementation method thereof, operation circuit and chip |
| CN113658623B (en) * | 2021-08-20 | 2024-03-01 | 湘潭大学 | Ferroelectric memory array capable of realizing multi-operand memory calculation |
| CN116149599B (en) * | 2023-03-30 | 2023-08-08 | 杭州雄迈集成电路技术股份有限公司 | Step-by-step carry processing method, system and adder |
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