CN102866646B - Real-time control system and method - Google Patents
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Abstract
The invention discloses a real-time control system and method. The real-time control system comprises first and second single chip computers (1, 3), a clock source (4) and an on-site programmable gate array device (2), wherein the on-site programmable gate array device (2) is composed of first and second dual-port RAM (Random Access Memory) modules (U1, U2) with two sides respectively connected with the first and the second single chip computers (1, 3) and a semaphore module (U3) with two sides respectively connected with the first and the second single chip computers (1, 3) and the clock source (4). The first and the second single chip computers (1, 3) are used for operating the programmable gate array device (2); the clock source (4) is used for providing clock pulses to the programmable gate array device (2); the first and the second dual-port RAM modules (U1, U2) are used for converting the width of a data bus from 8 bits into 16 bits; and the semaphore module (U3) is used for controlling the first and the second dual-port RAM modules (U1, U2) via semaphore signals. The real-time control system and method disclosed by the invention have the effects of matched bus width, high transmission rate, strong anti-interference performance and the like.
Description
Technical field
The invention belongs to control system and method, specially refer to a kind of real-time control system for industry automatic control and control method, this real-time control system comprises that one for the first single-chip microcomputer with external data communication, and a second singlechip and of controlling for built-in function is for providing the clock source of time clock.
Background technology
In prior art, for coal, oil field, the real-time industrial control system of the industrial automations such as steel-making adds storer by a slice single-chip microcomputer, A/D converter and Peripheral Interface form, the defect of its existence is: because a real-time control system generally needs data acquisition, mould/number conversion, analytical calculation, D/A switch, the tasks such as real-time process control and demonstration, depending merely on a slice single-chip microcomputer completes these work meetings and greatly extends the control cycle of system to control object, thereby the work efficiency of system is reduced, can not realize high speed and real time control.In order to improve system control cycle, the control system higher to requirement of real-time adopts two CPU control modes conventionally, by the shared out the work and help one another control task of whole system of two CPU, if a CPU is for data collection and analysis, another CPU is for the data communication with host computer.During two CPU communication, usually adopt the data bus of same bit-width, but in real process, often can run into two unmatched communication issues of the data-bus width between CPU, need to carry out interface circuit design.For this reason, the mode that adopts two additional two-port RAM chip devices of bus driver to realize bus expansion as another solves the unmatched communication issue of data-bus width, the peripheral components that this mode needs is more, bus transmission path is long, potential stability and the real time problems that exists communication.
Summary of the invention
The technical problem to be solved in the present invention is to provide that a kind of transfer rate is high, data-bus width coupling, strong interference immunity, the real-time control system that cost is low.
For solving the problems of the technologies described above, real-time control system of the present invention, comprise the first single-chip microcomputer, second singlechip and clock source, it is characterized in that: also comprise a field programmable gate array device, this programmable gate array device is comprised of the first two-port RAM module and the second two-port RAM module and semaphore module; Described the first two-port RAM module is connected with described the first single-chip microcomputer with the second two-port RAM module one side, and opposite side is connected with second singlechip; Described semaphore module one side is connected with described the first single-chip microcomputer, and opposite side is connected with clock source with second singlechip;
Described the first single-chip microcomputer and second singlechip are used for operating programmable gate array device;
Described clock source is for providing time clock to operation programmable gate array device;
Described the first two-port RAM module and the second two-port RAM module are for realizing data-bus width by the conversion of 8 to 16;
Described for semaphore module semaphore code seml, semr the first two-port RAM module and the second two-port RAM module are controlled;
Described the first two-port RAM module is connected with single-chip microcomputer by reading writing signal line, 8 bit data bus, address bus, U1 chip select line, U2 chip select line with the second two-port RAM module one side; Between the first two-port RAM module and the second two-port RAM module, U1 chip select line, U2 chip select line and the first single-chip microcomputer, be provided with the first logical OR controller and the second logical OR controller, described the first single-chip microcomputer is connected by single-chip microcomputer address wire A0, single-chip microcomputer ground route selection with the first logical OR controller, between described single-chip microcomputer ground wire A0 and the second logical OR controller, is provided with a logic NOT controller; The opposite side of described the first two-port RAM module and the second two-port RAM module is connected with second singlechip by read-write chip select line, 8 bit data bus, address bus;
Described semaphore module both sides are connected with second singlechip with described the first single-chip microcomputer by reading writing signal line;
The quantity of address wire and the quantity of semaphore that described semaphore module connects match, and its mutual relationship is: semaphore module=2n, wherein n represents number of address lines.
Compared with prior art, real-time control system tool of the present invention has the following advantages:
Bus expansion only needs a field programmable gate array device, this field programmable gate array device is comprised of the first two-port RAM module, the second two-port RAM module and semaphore module this programmable gate array device, and the inner realization of programmable gate array device at the scene, structural reduction, is beneficial to the miniaturization of system; Bus expansion only needs a field programmable gate array device, and bus transmission path is short, thereby transfer rate is high; Bus expansion only needs a field programmable gate array device, and price is not high yet, thereby anti-interference is high, and cost is low.
[0007] another technical matters that the present invention will solve is to provide the control method of utilizing above-mentioned real-time control system, and the method comprises the following steps:
Start step: before agreement operation the first two-port RAM module, the first single-chip microcomputer and single-chip microcomputer first operate, control semaphore module with semaphore code seml and semr; Two-port RAM module U1, U2, by two semaphore code seml, semr, controlled, wherein seml is for determining left side single-chip microcomputer is whether the first single-chip microcomputer is operating two-port RAM module U1, U2, and semr is for determining right side single-chip microcomputer is whether second singlechip is operating two-port RAM module U1, U2;
Single-chip microcomputer is to the step of semaphore module address data writing; The first single-chip microcomputer is to the semaphore code seml data writing " 0 " of the first two-port RAM module;
Read the step of data writing: the semaphore code seml data writing result that is read previous step by semaphore module;
Judgement execution step: if reading result is " 0 ", show that second singlechip does not operate the first two-port RAM module and the second two-port RAM module; Now, the first single-chip microcomputer can read and write data to the first two-port RAM module and the second two-port RAM module;
If reading result is " 1 ", show that second singlechip operates the second two-port RAM module, now, the first single-chip microcomputer can not read and write data to the second two-port RAM module corresponding to semaphore code, trial is to other address data writing 0 of semaphore module U, and returns to the step that reads data writing;
So repetitive cycling above-mentioned steps, completes control procedure.This control method has guaranteed the Stability and dependability of data width conversion.
Accompanying drawing explanation
The structural representation of Fig. 1 real-time control system of the present invention;
In figure, the first single-chip microcomputer 1, second singlechip 3, clock source 4, field programmable gate array device 2, the first two-port RAM module U1, the second two-port RAM module U2, semaphore module U3, the first logical OR controller U11, the second logical OR controller U21, logic NOT controller U211;
Fig. 2 is the control method process flow diagram of real-time control system of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is entered to be further described in detail:
Real-time control system of the present invention as shown in Fig. 1, in Fig. 1, real-time control system of the present invention comprises the first single-chip microcomputer 1, second singlechip 3 and clock source 4; This real-time control system also comprises a field programmable gate array device 2, and this programmable gate array device 2 is comprised of the first two-port RAM module U1, the second two-port RAM module U2 and semaphore module U3; The read-write of described the first two-port RAM module U1 and the second dual-port AM module U2 mono-side, chip selection signal, data bus, address bus through the logical relation as shown in Fig. 1 with as described in the first single-chip microcomputer 1 be connected, the read-write of opposite side, chip selection signal, data bus, address bus through the logical relation as shown in Fig. 1 with as described in second singlechip 3 be connected, described semaphore module U3 mono-side is connected with the read-write semaphore code of described the first single-chip microcomputer 1, and opposite side is connected with the read-write semaphore code of second singlechip 3;
Described the first single-chip microcomputer 1 and second singlechip 3 are for operating programmable gate array device 2; This first single-chip microcomputer 1 is 8 figure place machines, this second singlechip 3 is 16 figure place machines, in practical application, also can to the first single-chip microcomputer 1 and second singlechip 3, adopt 8 figure place machines and 16 figure place machines as required simultaneously, or the first single-chip microcomputer 1 is 16 figure place machines conversely, second singlechip 3 is 8 figure place machines, to realize the conversion of various data.
Described clock source 4 is connected with the clock signal pin of programmable gate array device 2, to can operate programmable gate array device 2 from trend after system power supply, provides time clock;
Described the first two-port RAM module U1 and the second two-port RAM module U2 are for realizing data-bus width by the conversion of 8 to 16;
Described semaphore module for U3 semaphore code seml, semr the first two-port RAM module U1 and the second two-port RAM module U2 dual-port are controlled, wherein seml is for determining left side single-chip microcomputer is whether the first single-chip microcomputer is operating the first two-port RAM module U1 and the second two-port RAM module U2, and semr is for determining whether second singlechip is operating the first two-port RAM module U1 and the second two-port RAM module U2;
Described the first two-port RAM module U1 is connected with the first single-chip microcomputer 1 by reading writing signal line, 8 bit data bus, address bus, U1 chip select line, U2 chip select line with the second two-port RAM module U2 mono-side; Between the first two-port RAM module U1 and the second two-port RAM module U2, U1 chip select line, U2 chip select line and the first single-chip microcomputer 1, be provided with the first logical OR controller U11 and the second logical OR controller U21; Described the first single-chip microcomputer 1 is connected by single-chip microcomputer address wire A0, single-chip microcomputer ground route selection with the first logical OR controller U11, between described single-chip microcomputer ground wire A0 and the second logical OR controller U21, is provided with a logic NOT controller U211; The opposite side of described the first two-port RAM module U1 and the second two-port RAM module U2 is connected with second singlechip 3 by read-write chip select line, 8 bit data bus, address bus; Described semaphore module U3 both sides are connected with second singlechip 3 with described the first single-chip microcomputer 1 by reading writing signal line;
The quantity of address wire and the quantity of semaphore that described semaphore module U3 connects match, and its mutual relationship is: semaphore module (U3)=2n, and wherein n represents number of address lines;
Now describe for example connection, operation, conversion, the control procedure of real-time control system coherent signal of the present invention in detail: if when the first single-chip microcomputer 1 reads and writes data to address 0x0000, from signal annexation, now the first two-port RAM module U1 chip selection signal is effective, the second two-port RAM module U2 chip selection signal is invalid, read-write be the data in the actual specific address 0x0000 of the first two-port RAM module U1; When if the first single-chip microcomputer 1 reads and writes data to address 0x0001, from signal annexation, now the first two-port RAM module U1 chip selection signal is invalid, the second two-port RAM module U2 chip selection signal is effective, read-write be the data in the actual specific address x0000 of the second two-port RAM module U2; When if the first single-chip microcomputer 1 reads and writes data to address 0x0003, from signal annexation, now the first two-port RAM module U1 chip selection signal is effective, the second two-port RAM module U2 chip selection signal is invalid, read-write be the data in the actual specific address 0x0001 of the first two-port RAM module U1; When if the first single-chip microcomputer 1 reads and writes data to address 0x0004, from signal annexation, now the first two-port RAM module U1 chip selection signal is invalid, the second two-port RAM module U2 chip selection signal is effective, read-write be the data in the actual specific address 0x0001 of the second two-port RAM module U2; During the every operation even address of the first single-chip microcomputer 1, operated object must be the first two-port RAM module U1, and during every operation odd address, operated object must be the second two-port RAM module U2; By the above results, if the first single-chip microcomputer 1 is continuously to address 0x0000,0x0001 data writing 0x12,0x34, data 0x12 is stored in the actual specific address 0x0000 of the first two-port RAM module U1, and data 0x34 is stored in the actual specific address 0x0000 of the second two-port RAM module U2; If now during the data in second singlechip 3 reading address 0x0000, from signal annexation, the data that read are 0x1234; If in like manner operated by second singlechip 3, process is just in time contrary, has realized the mutual conversion between 8 bit data bus and 16 bit data bus.
The ginseng control method of utilizing above-mentioned real-time control system as shown in Figure 2, for ease of understanding and explanation, only take below the control method of the first two-port RAM module U1 is illustrated as example, to the control of the second two-port RAM module U2 with identical to the method for the control of the first two-port RAM module U1, no longer repeat specification.From Fig. 2, this control method comprises the following steps:
Start step: before agreement operation two-port RAM module U1, the first single-chip microcomputer 1 and second singlechip 3 first operate, control semaphore module U3 with semaphore code seml and semr;
Single-chip microcomputer is to the step of semaphore module address data writing; The first single-chip microcomputer 1 is to the semaphore code seml data writing " 0 " of the first two-port RAM module U1;
Read the step of data writing: by and then read this semaphore code seml, if read the semaphore code seml data writing result of previous step by semaphore module U3;
Judgement execution step: if reading result is " 0 ", show that second singlechip 3 is not to operating the first two-port RAM module U1 and the second two-port RAM module U2; Now, the first single-chip microcomputer 1 can read and write data to the first two-port RAM module U1 and the second two-port RAM module U2;
If reading result is " 1 ", show that second singlechip 3 operates the second two-port RAM module U2, now, the first single-chip microcomputer 1 can not read and write data to the second two-port RAM module U2 corresponding to semaphore code, trial is to other address data writing 0 of semaphore module U3, and returns to the step that reads data writing;
So repetitive cycling above-mentioned steps, completes control procedure.
Claims (6)
1. a real-time control system, comprise the first single-chip microcomputer (1), second singlechip (3) and clock source (4), it is characterized in that: also comprise a field programmable gate array device (2), this programmable gate array device (2) is by the first two-port RAM module (U1), the second two-port RAM module (U2) and semaphore module (U3) form, described the first two-port RAM module (U1) is connected with described the first single-chip microcomputer (1) with second two-port RAM module (U2) side, opposite side is connected with second singlechip (3), described semaphore module (U3) side is connected with described the first single-chip microcomputer (1), opposite side is connected with clock source (4) with second singlechip (3),
Described the first single-chip microcomputer (1) and second singlechip (3) are for operating programmable gate array device (2);
Described clock source (4) is for providing time clock to operation programmable gate array device (2);
Described the first two-port RAM module (U1) and the second two-port RAM module (U2) are for realizing data-bus width by the conversion of 8 to 16;
Described semaphore module (U3) is controlled the first two-port RAM module (U1) and the second two-port RAM module (U2) with semaphore code seml, semr.
2. according to the real-time control system described in claim 1, it is characterized in that: described the first two-port RAM module (U1) is connected with the first single-chip microcomputer (1) by reading writing signal line, 8 bit data bus, address bus, U1 chip select line, U2 chip select line with second two-port RAM module (U2) side;
Between the first two-port RAM module (U1) and the first single-chip microcomputer (1), be provided with the first logical OR controller (U11); Between the second two-port RAM module (U2) and the first single-chip microcomputer (1), be provided with the second logical OR controller (U21);
Described the first single-chip microcomputer (1) is connected by single-chip microcomputer address wire A0, single-chip microcomputer chip select line with the first logical OR controller (U11), between described single-chip microcomputer address wire A0 and the second logical OR controller (U21), is provided with a logic NOT controller (U211);
The opposite side of described the first two-port RAM module (U1) and the second two-port RAM module (U2) is connected with second singlechip (3) by read-write chip select line, 8 bit data bus, address bus.
3. according to the real-time control system described in claim 1, it is characterized in that: described semaphore module (U3) both sides are connected with second singlechip (3) with described the first single-chip microcomputer (1) by reading writing signal line.
4. according to the real-time control system described in claim 1, it is characterized in that, the quantity of address wire and the quantity of semaphore that described semaphore module (U3) connects match, and its mutual relationship is: semaphore module (U3)=2n, wherein n represents number of address lines.
5. according to the real-time control system described in any one in claim 1 to 3, it is characterized in that, the quantity of address wire and the quantity of semaphore that described semaphore module (U3) connects match, and its mutual relationship is: semaphore module (U3)=2n, wherein n represents number of address lines.
6. a control method of utilizing any one real-time control system in claim 1 to 4, comprises the following steps:
Start step: before, the first single-chip microcomputer (1) and second singlechip (3) first use semaphore code seml and semr that semaphore module (U3) is operated, controlled to agreement operation the first two-port RAM module (U1);
Single-chip microcomputer is to the step of semaphore module address data writing: the first single-chip microcomputer (1) is to the semaphore code seml data writing " 0 " of the first two-port RAM module (U1);
Read the step of data writing: the semaphore code seml the data writing result that by semaphore module (U3), are read previous step;
Judgement execution step: if reading result is " 0 ", show that second singlechip (3) does not operate the first two-port RAM module (U1) and the second two-port RAM module (U2); Now, the first single-chip microcomputer (1) can read and write data to the first two-port RAM module (U1) and the second two-port RAM module (U2);
If reading result is " 1 ", show that second singlechip (3) operates the second two-port RAM module (U2), now, the first single-chip microcomputer (1) can not read and write data to the second two-port RAM module (U2) corresponding to semaphore code, trial is to other address data writing 0 of semaphore module (U3), and returns to the step that reads data writing;
So repetitive cycling above-mentioned steps, completes control procedure.
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| CN201210351246.4A CN102866646B (en) | 2012-09-20 | 2012-09-20 | Real-time control system and method |
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| DE4005042C2 (en) * | 1989-02-17 | 1994-05-19 | Hughes Aircraft Co | Multi-computer system for performing motion controls |
| CN1713165A (en) * | 2005-07-18 | 2005-12-28 | 北京金自天正智能控制股份有限公司 | Data communicating circuit of VME bus and DSP processor |
| CN1996321A (en) * | 2006-11-03 | 2007-07-11 | 威海渔翁科技开发有限公司 | Encryption card based on PCI Express bus technology |
| CN201429791Y (en) * | 2008-10-14 | 2010-03-24 | 哈尔滨九洲电气股份有限公司 | High-speed data communication device in high-voltage reactive power compensation equipment |
| CN201813360U (en) * | 2010-06-29 | 2011-04-27 | 上海新华控制技术(集团)有限公司 | Semaphore circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4845522B2 (en) * | 2006-01-30 | 2011-12-28 | シャープ株式会社 | System bus control device, integrated circuit and data processing system |
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2012
- 2012-09-20 CN CN201210351246.4A patent/CN102866646B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4005042C2 (en) * | 1989-02-17 | 1994-05-19 | Hughes Aircraft Co | Multi-computer system for performing motion controls |
| CN1713165A (en) * | 2005-07-18 | 2005-12-28 | 北京金自天正智能控制股份有限公司 | Data communicating circuit of VME bus and DSP processor |
| CN1996321A (en) * | 2006-11-03 | 2007-07-11 | 威海渔翁科技开发有限公司 | Encryption card based on PCI Express bus technology |
| CN201429791Y (en) * | 2008-10-14 | 2010-03-24 | 哈尔滨九洲电气股份有限公司 | High-speed data communication device in high-voltage reactive power compensation equipment |
| CN201813360U (en) * | 2010-06-29 | 2011-04-27 | 上海新华控制技术(集团)有限公司 | Semaphore circuit |
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