CN102468209B - Method for forming buried layer of SiGe heterojunction bipolar transistor (HBT) - Google Patents
Method for forming buried layer of SiGe heterojunction bipolar transistor (HBT) Download PDFInfo
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- CN102468209B CN102468209B CN 201010550588 CN201010550588A CN102468209B CN 102468209 B CN102468209 B CN 102468209B CN 201010550588 CN201010550588 CN 201010550588 CN 201010550588 A CN201010550588 A CN 201010550588A CN 102468209 B CN102468209 B CN 102468209B
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 229910000577 Silicon-germanium Inorganic materials 0.000 title abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 53
- 229910052732 germanium Inorganic materials 0.000 claims description 28
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 150000002500 ions Chemical class 0.000 claims description 22
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 238000004528 spin coating Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000013459 approach Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 230000003247 decreasing effect Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
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Abstract
The invention discloses a method for forming a buried layer of a SiGe heterojunction bipolar transistor (HBT). The exposure of photoresist is divided into two times, the first time of the exposure is focused on a part approaching to the surface of the photoresist to form a main pattern, and the second time of the exposure is focused on a part approaching to a substrate of the photoresist to perform additional exposure on the bottom of the main pattern, so that the actual size formed at the bottom of the photoresist approaches a design size as far as possible.
Description
Technical field
The present invention relates to a kind of manufacture method of germanium silicium HBT, particularly relate to a kind of manufacture method of buried regions of germanium silicium HBT.
Background technology
Germanium silicon (SiGe) be silicon and germanium by the semiconducting compound that covalent bonds forms, be the instead type solid solution that these two kinds of elements infinitely dissolve each other.Germanium silicium HBT (Heterojunction Bipolar Transistor, heterojunction bipolar transistor) is a kind of high-frequency RF commonly used (Radio Frequency, radio frequency) device.Compare with traditional silicon transistor, it is adjustable that germanium silicon has energy gap, and the characteristics narrower than the band gap of silicon, is fit to very much high-speed high frequency and uses.
See also Fig. 1, this is a kind of existing germanium silicium HBT.Wherein, collector electrode 3 is embedded under the base stage 5, therefore needs buried regions 1 and collector electrode draw-out area 4 that collector electrode 3 is drawn and carries out line.
The buried regions manufacture method of germanium silicium HBT shown in Figure 1 comprises the steps:
In the 1st step, see also Fig. 3 a, spin coating photoresist 10 on substrate 01a.
The 2nd step saw also Fig. 3 b, and photoresist 10 is exposed.This moment, photoresist 10 can be divided into three zones at least according to the difference of light distribution.Middle regional 10a is the strongest zone of light intensity, and the photoresist 10 in this zone can be removed after development fully.Wai Ce regional 10b is the zone of light intensity from successively decreasing toward a little less than by force slightly, and the photoresist 10 in this zone can partly be removed part after development residual.Outermost regional 10c is that light intensity reduces to zero zone, and the photoresist 10 in this zone almost completely keeps after development.
The 3rd step saw also Fig. 3 c, and the photoresist 10 after the exposure is developed, and the photoresist 10 on the development back substrate 01a has just formed the buried regions ion and injected window, and the two side that this ion injects window all is a photoresist 10.
The 4th step saw also Fig. 3 d, makes ion and inject on the substrate 01a of the buried regions ion injection window that photoresist 10 forms, and formed buried regions 1, removed photoresist 10 then.
The 5th step saw also Fig. 3 e, grew epitaxial loayer 01b on substrate 01a.
The 6th step saw also Fig. 3 f, by annealing process the diffusion of impurities in the buried regions 1 was evenly distributed, and annealing back buried regions 1 part is diffused among the epitaxial loayer 01b.
The buried regions manufacture method of germanium silicium HBT need be used epitaxy technique shown in Fig. 3 a～Fig. 3 f, so cost is higher.But during to resist exposure, vertically light distribution is that promptly any vertical straight line is identical in the light intensity intensity of differing heights among Fig. 3 b uniformly.See also Fig. 5 a, this is in the light distribution of vertical negative direction (direction of arrow is represented from silicon chip surface toward inner) when going up the resist exposure shown in Fig. 3 b, shows as vertical light intensity and is evenly distributed.The size of the buried regions ion injection window that forms thus can accurately be controlled, and the sidewall that is reflected as photoresist 10 among Fig. 3 c approaches 90 degree.
See also Fig. 2, this is another kind of existing germanium silicium HBT.Wherein, have deep hole 8 in the isolation structure (isolating LOCOS or shallow-trench isolation STI as field oxygen) 2, this deep hole 8 is filled the back as the collector electrode draw-out area.
The buried regions manufacture method of germanium silicium HBT shown in Figure 2 comprises the steps:
The 1st step saw also Fig. 4 a, etched two grooves on active area 01c, and the top of the active area 01c between two grooves is covered by hard mask layer 9 and protects.
In the 2nd step, see also Fig. 4 b, spin coating photoresist 10 on silicon chip.Owing to the existence of groove and hard mask layer 9 is arranged, so photoresist 10 can present the pattern of projection above hard mask layer 9.
The 3rd step saw also Fig. 4 c, and photoresist 10 is exposed.This moment, photoresist 10 can be divided into three zones at least according to the difference of light distribution.Middle regional 10a is the strongest zone of light intensity, and the photoresist 10 in this zone can be removed after development fully.Wai Ce regional 10b is the zone of light intensity from successively decreasing toward a little less than by force slightly, and the photoresist 10 in this zone can partly be removed part after development residual.Outermost regional 10c is that light intensity reduces to zero zone, and the photoresist 10 in this zone almost completely keeps after development.
The 4th step saw also Fig. 4 d, and the photoresist 10 after the exposure is developed, and had formed two buried regions ions after the development and had injected window.It all is that a side sidewall by photoresist 10 and groove forms jointly that each buried regions ion injects window.
The 5th step saw also Fig. 4 e, and the active area 01c that injects the bottom of window at these two buried regions ions carries out the ion injection, forms two independently buried regions 1.
The 6th step saw also Fig. 4 f, by annealing process make these two independently buried regions 1 link to each other and diffusion of impurities wherein be evenly distributed.
The buried regions manufacture method of germanium silicium HBT is not used epitaxy technique shown in Fig. 4 a～Fig. 4 f, do not need additionally to introduce the photoetching process of collector electrode draw-out area, so manufacturing cost is lower yet.Simultaneously owing to there is not the collector electrode draw-out area, so the size of buried regions just can reduce significantly, so the more traditional HBT of device area of HBT part is little a lot, thus single transistor to share manufacturing cost equally lower.But during to resist exposure, vertically light distribution is successively decreased from top to bottom one by one, be the light intensity intensity that the light intensity intensity of any vertical straight line in the higher position was greater than or equaled lower position among Fig. 4 c, this is because the sidewall of groove has due to certain gradient.See also Fig. 5 b, this is the light distribution the during resist exposure shown in Fig. 4 c on vertical negative direction, shows as that the degree of depth that enters silicon chip inside is big more, light intensity intensity is more little.This can cause really need forming in the bottom of photoresist 10 position of figure, because light intensity is not enough, can't effectively form figure, and the therefore actual size that forms is far smaller than design size, shown in Fig. 4 d.Therefore and cmos device is integrated when doing the Bi-CMOS product therefore in this technology, the design rule of figure can only be forced to amplify, and, CMOS device area partly can increase.
Summary of the invention
Technical problem to be solved by this invention provides a kind of manufacture method of buried regions of germanium silicium HBT, when guaranteeing existing device architecture advantage, solves the buried regions ion and injects window to the design rule of the active area problem bigger than traditional devices size.
For solving the problems of the technologies described above, the buried regions formation method of germanium silicium HBT of the present invention comprises the steps:
The 1st step, adopt photoetching and etching technics on silicon chip, to etch two grooves, the top of the silicon chip between two grooves is covered by hard mask layer;
The 2nd step, spin coating photoresist on silicon chip;
In the 3rd step, it is 0.52～0.82 that numerical aperture is set, and coherence factor is 0.3～0.9, and focal length is-0.1～0.1 μ m, and exposure energy is 5～100mJ/cm
2(milli Jiao/square centimeter) carries out the exposure first time to photoresist, and do not develop this moment;
The 4th step, silicon chip does not leave the mask aligner platform, mask is not left the mask platform, it is 0.52～0.82 that numerical aperture is set, coherence factor is 0.3～0.9, and focal length is the described gash depth of 90% described gash depth～110%, exposure energy be for the first time exposure energy 50%～200%, photoresist is carried out the exposure second time, develop then;
Formed two buried regions ions this moment and injected windows, it all is that a side sidewall by photoresist and groove forms jointly that each buried regions ion injects window;
In the 5th step, the silicon chip that injects the bottom of window at these two buried regions ions carries out the ion injection, forms two independently buried regions;
The 6th step, by annealing process make these two independently buried regions link to each other and diffusion of impurities wherein be evenly distributed.
Compare with the buried regions formation method of traditional germanium silicium HBT, the present invention overcomes the photoetching process defective of bringing on the active area inclined plane in conjunction with the buried regions special construction of low-cost HBT.Among the present invention for the first time exposure focusing form the top figure in the part of photoresist near the surface.Exposure focusing carries out supplenmentary exposure in the part of photoresist near substrate to the bottom for the second time.Thereby the actual size that makes the formation of photoresist bottom is as far as possible near design size.
Description of drawings
Fig. 1 is the structural representation of existing a kind of germanium silicium HBT;
Fig. 2 is the structural representation of existing another kind of germanium silicium HBT;
Fig. 3 a～Fig. 3 f is each step schematic diagram of the buried regions manufacture method of germanium silicium HBT shown in Figure 1;
Fig. 4 a～Fig. 4 f is each step schematic diagram of the buried regions manufacture method of germanium silicium HBT shown in Figure 2;
Fig. 5 a is the vertical direction light intensity schematic diagram of germanium silicium HBT shown in Figure 1 when resist exposure;
Fig. 5 b is the vertical direction light intensity schematic diagram of germanium silicium HBT shown in Figure 2 when resist exposure;
Fig. 5 c is the vertical direction light intensity schematic diagram of germanium silicium HBT of the present invention to the photoresist re-expose;
Fig. 5 d is the horizontal direction light intensity schematic diagram of germanium silicium HBT of the present invention to the photoresist re-expose;
Fig. 6 a is the horizontal direction schematic diagram of existing double exposure technology;
Fig. 6 b is the vertical direction schematic diagram of existing double exposure technology;
Fig. 7 a～Fig. 7 c is the part steps schematic diagram of the buried regions manufacture method of germanium silicium HBT of the present invention.
Description of reference numerals among the figure:
01a is a substrate; 01b is an epitaxial loayer; 01c is an active area; 1 is buried regions; 2 is isolation structure; 3 is collector electrode; 4 is the collector electrode draw-out area; 5 is base stage; 6 is emitter; 7 is the emitter-window insulating barrier; 8 is deep hole; 9 is hard mask layer; 10 is photoresist; 10a is the strongest zone of light intensity; 10b is the light intensity zone of successively decreasing; 10c is that light intensity is kept to zero zone.
Embodiment
The buried regions formation method of germanium silicium HBT of the present invention comprises the steps:
The 1st step saw also Fig. 4 a, adopted photoetching and etching technics to etch two grooves on silicon chip (active area 01c), and these two grooves are normally parallel, and the degree of depth is identical.The top of the silicon chip (active area 01c) between these two grooves is covered by hard mask layer 9, and the silicon chip of these hard mask layer 9 its belows of protection is not etched into.
In the 2nd step, see also Fig. 4 b, spin coating photoresist 10 on silicon chip.
The 3rd step saw also Fig. 7 a, and it is 0.52～0.82 that numerical aperture is set, and coherence factor is 0.3～0.9, and focal length is-0.1～0.1 μ m, and exposure energy is 5～100mJ/cm
2, photoresist 10 is carried out the exposure first time, do not develop this moment.Some fill area among Fig. 7 a is the exposure area, develops as yet, therefore the just light of photoresist acid distribution signal.Exposure area exposure area big, that go deep into the silicon chip interior section near the silicon chip surface part is less.
The 4th step, see also Fig. 7 b, silicon chip does not leave the mask aligner platform, mask is not left the mask platform, and it is 0.52～0.82 that numerical aperture is set, and coherence factor is 0.3～0.9, focal length is the described gash depth of 90% described gash depth～110%, exposure energy be for the first time exposure energy 50%～200%, photoresist is carried out exposure second time, development then.Formed two buried regions ions this moment and injected windows, it all is that a side sidewall by photoresist 10 and groove forms jointly that each buried regions ion injects window.
The 5th step saw also Fig. 7 c, and the silicon chip (active area 01c) that injects the bottom of window at these two buried regions ions carries out the ion injection, forms two independently buried regions 1.
The 6th step saw also Fig. 4 f, by annealing process make these two independently buried regions 1 link to each other and diffusion of impurities wherein be evenly distributed.
Described method is in the 4th step, and more preferably, it is 0.68～0.75 that numerical aperture is set, and coherence factor is 0.8～0.9, exposure energy be the first time exposure energy 80%～150%.
See also Fig. 5 c, this is the light distribution during twice pair of resist exposure of the present invention on vertical negative direction, and wherein dotted line is represented exposure for the first time, and solid line is represented exposure for the second time.The vertical light intensity of exposure distribution for the first time is identical with Fig. 5 b, and light intensity concentrates near the silicon chip surface.The exposure second time that increases newly then concentrates on light intensity darker position, silicon chip inside.
See also Fig. 5 d, the light distribution when this is twice pair of resist exposure of the present invention in the horizontal direction, wherein dotted line is represented exposure for the first time, solid line is represented exposure for the second time.Obviously double exposure does not almost have difference in horizontal light distribution.
Double exposure technology is also arranged in the conventional semiconductor device fabrication, Fig. 6 a has shown the horizontal light distribution of existing double exposure technology, Fig. 6 b has shown that the vertical light intensity of existing double exposure technology distributes, and wherein dotted line is represented exposure for the first time, and solid line is represented exposure for the second time.Obviously, the vertical light intensity of existing double exposure technology distributes almost completely identical, and difference to some extent in horizontal light distribution.Double exposure technology of the present invention is then almost completely identical in horizontal light distribution, difference to some extent on vertical light intensity distributes, thereby with existing double exposure technology be diverse.
In sum, the buried regions formation method of germanium silicium HBT of the present invention has designed the double exposure at photoresist especially.Exposure for the first time makes slot wedge produce more light acid, and then carries out the exposure second time, can overcome the limited problem of design rule that causes because the bottom that inclined groove causes is under-exposed, thereby the germanium silicium HBT device area is dwindled.
Claims (2)
1. the buried regions formation method of a germanium silicium HBT is characterized in that, comprises the steps:
The 1st step, adopt photoetching and etching technics on silicon chip, to etch two grooves, the top of the silicon chip between two grooves is covered by hard mask layer;
The 2nd step, spin coating photoresist on silicon chip;
In the 3rd step, it is 0.52～0.82 that numerical aperture is set, and coherence factor is 0.3～0.9, and focal length is-0.1～0.1 μ m, and exposure energy is 5～100mJ/cm
2, photoresist is carried out the exposure first time, do not develop this moment;
The 4th step, silicon chip does not leave the mask aligner platform, mask is not left the mask platform, it is 0.52～0.82 that numerical aperture is set, coherence factor is 0.3～0.9, and focal length is the described gash depth of 90% described gash depth～110%, exposure energy be for the first time exposure energy 50%～200%, photoresist is carried out the exposure second time, develop then;
Formed two buried regions ions this moment and injected windows, it all is that a side sidewall by photoresist and groove forms jointly that each buried regions ion injects window;
In the 5th step, the silicon chip that injects the bottom of window at these two buried regions ions carries out the ion injection, forms two independently buried regions;
The 6th step, by annealing process make these two independently buried regions link to each other and diffusion of impurities wherein be evenly distributed.
2. the buried regions formation method of germanium silicium HBT according to claim 1 is characterized in that, described method is in the 4th step, and it is 0.68～0.75 that numerical aperture is set, and coherence factor is 0.8～0.9, exposure energy be the first time exposure energy 80%～150%.
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| CN 201010550588 CN102468209B (en) | 2010-11-19 | 2010-11-19 | Method for forming buried layer of SiGe heterojunction bipolar transistor (HBT) |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0553543A1 (en) * | 1992-01-31 | 1993-08-04 | Mitsubishi Denki Kabushiki Kaisha | Method for forming resist pattern |
| CN1139295A (en) * | 1995-04-21 | 1997-01-01 | 大宇电子株式会社 | Method for fabricating vertical bipolar transistor |
| US5856700A (en) * | 1996-05-08 | 1999-01-05 | Harris Corporation | Semiconductor device with doped semiconductor and dielectric trench sidewall layers |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0722433A (en) * | 1993-07-05 | 1995-01-24 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0553543A1 (en) * | 1992-01-31 | 1993-08-04 | Mitsubishi Denki Kabushiki Kaisha | Method for forming resist pattern |
| CN1139295A (en) * | 1995-04-21 | 1997-01-01 | 大宇电子株式会社 | Method for fabricating vertical bipolar transistor |
| US5856700A (en) * | 1996-05-08 | 1999-01-05 | Harris Corporation | Semiconductor device with doped semiconductor and dielectric trench sidewall layers |
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