CN101473426A - Dielectric deposition and etch back processes for bottom up gapfill - Google Patents
Dielectric deposition and etch back processes for bottom up gapfill Download PDFInfo
- Publication number
- CN101473426A CN101473426A CNA2007800231733A CN200780023173A CN101473426A CN 101473426 A CN101473426 A CN 101473426A CN A2007800231733 A CNA2007800231733 A CN A2007800231733A CN 200780023173 A CN200780023173 A CN 200780023173A CN 101473426 A CN101473426 A CN 101473426A
- Authority
- CN
- China
- Prior art keywords
- dielectric film
- annealing
- film
- etching
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
The invention discloses a method for reducing the crack of film in a dielectric layer. The method comprises a step of depositing a first dielectric film on a substrate and etching the first dielectric film to remove the top of the first dielectric film. The method also comprises a step of depositing a second dielectric film on the etched first dielectric film to remove the top of the second dielectric film. In addition, the method also comprises a step of annealing the first and second dielectric films to form the dielectric layers, wherein removing the tops of the first and second dielectric films can reduce the stress in the dielectric layers.
Description
Related application is quoted
It is 60/805,573 that the application requires application number, is filed in the U.S. Provisional Application No. on June 22nd, 2006, and the full content of above-mentioned application merges therewith by reference.The application is also relevant with following application: U. S. application number is 11/753,918, be filed on May 25th, 2007, be entitled as " method that deposition and processing low K film are used to fill and relevant film are used " (A METHODFOR DEPOSITING AND CURING LOW-K FILMS FOR GAPFILL ANDCONFORMAL FILM APPLICATIONS); And U. S. application number is 11/753,968, be filed on May 25th, 2007, be entitled as " the new deposition-plasma processing cycle process that is used to strengthen the silicon dioxide film quality " (A NOVEL DEPOSITION-PLASMA CU RE CYCLEPROCESS TO ENHANCE FILM QUALITY OF SILICON DIOXIDE).
Background technology
One of them difficult problem to be overcome such as in present semiconductor technology evolves process, continue and be to wish to improve the density of circuit unit and interconnect on the base material, but can not cause and palm reciprocation (spurious interaction) off as between circuit unit and the interconnect.Usually by providing irrigation canals and ditches or the gap of filling up the material that is electrically insulated to come physical property and keep apart those assemblies electrically, to avoid producing undesired reciprocation.Yet when current densities improved, the width in these gaps can dwindle and improve its depth-to-width ratio, and made and to fill up those gaps can not leave over the task of hole in the gap arduous more.Can cause harmful effect to the device running performance that manufacturing is finished owing to leave over hole in the gap, for example have impurity and be absorbed in the insulating material, therefore not wish to take place not fill up the situation that forms hole fully because of the gap.
The technology that is usually used in filling in the gap is chemical vapour deposition technique (CVD).Tradition hot CVD technology provides multiple reactant gas to substrate surface, forms the film of being desired in the substrate surface place thermal induction chemical reaction to take place.Plasma enhanced CVD technology (PECVD) is to apply the conversion zone of radio frequency (RF) energy to the adjacent base material surface, to impel the reactant gas activation and/or to dissociate.Compared to traditional hot CVD technology, because the species in the plasma have high response, can reduce energy needed when chemical reaction takes place, therefore be minimized the needed temperature of this type of CVD technological reaction.Use high density plasma chemical vapor deposition (HDPCVD) can further encourage these advantages,, can make the plasma species have more reactivity because high-density plasma is to form under low vacuum pressure.Though each above-mentioned technology all still drops in the category of CVD technology, those technology have characteristic separately, and make it may be fit to or be not suitable for some specific application area.
Have in some example of high-aspect-ratio and narrow width in the gap, can be with the step of carrying out deposition one material in regular turn, eat-backing this a part of material and deposition additional materials, the hot CVD technology of carrying out deposition/etching/depositing operation is to fill the gap.This etching step is to be used for once more moulding and to open the gap that this is partly filled, can deposit more materials at gap-closing and before staying inner hole.This kind deposition/etching/depositing operation also has been applied in the PECVD technology, even but some hot CVD and PECVD technology have been used cyclic deposition and etching step, still be not suitable for being used for filling gap with high depth-to-width ratio.
Deposition/etching/depositing operation also shows and can be applicable in the HDP-CVD technology to improve the gap filling effect.Be different from pecvd process, high density ionic species in the HDP-CVD technical process can cause in deposition and splash this effect of deposit film in one film, therefore originally will deposit/etching/depositing operation is applied in that HDP-CVD is technical to exceed the convention cognitive in.In depositing operation, splash simultaneously with deposition materials be for the gap is stayed open in deposition process, therefore in deposition process, insert one independently the middle etch step be considered to unnecessary way.Yet, in No. 6194038, United States Patent (USP) case that Kent Rossman was applied on March 20th, 1998, be illustrated in and use a deposition/etching/depositing operation can further improve the such unpredictable consequence of gap filling effect under some HDP-CVD process conditions.And after confirmed this result in No. 6030181, the United States Patent (USP) case of being applied on May 5th, 1998 by people such as George D.Papasouliotis.
Yet even those combine the dielectric gap fill process of HDP-CVD and deposition/etching/deposition, gap size that it can be filled and depth-to-width ratio are still limited.For example, for those little gaps, may need to carry out irrational deposition-etch cycle number of times and keep not excessive filled dielectric material of this top, gap with high-aspect-ratio.The frequency of etch cycle and process increase may damage the structure that is used for defining the gap.Such situation may occur in the material deficiency that last time deposition step deposited, and/or remove in etching step in the too much deposition materials.The characteristic of each reative cell and the characteristic of each wafer may influence this true optimization that hinders technical recipe of deposition and etching action.When industry trend continues need develop to be fit to be used for dielectric deposition method in the crack between depth-to-width ratio is cumulative when the device of more intensive configuration develops.
Summary of the invention
The embodiment of the invention comprises that several reduce the method for film breaks in the dielectric layer.Those methods can comprise that deposition one first dielectric film is in carrying out the step that is etched with the top that removes this first dielectric film on the base material and on this film.Those methods also can comprise that deposition one second dielectric film is on etched first dielectric film and the top that removes this second dielectric film.In addition, those methods can comprise this first and second dielectric film of annealing to form dielectric layer, and the step that wherein removes the top of this first and second dielectric film can reduce the stress in this dielectric layer.
The embodiment of the invention also comprises the method for filling irrigation canals and ditches with dielectric material.Those methods can comprise the film that is constituted with a dielectric material and fill irrigation canals and ditches, wherein the first fluid that can contain elemental oxygen by mixing with comprise one and contain second fluid of silicon precursor, and make this elemental oxygen this dielectric film of formation with siliceous precursors reaction and in irrigation canals and ditches.Those methods also can comprise by this film of etching removing the top of this dielectric film, and this etched film of annealing.
The embodiment of the invention more comprises the additional method that reduces film breaks in the dielectric layer.Those methods can comprise that depositing one first dielectric film is carrying out first annealing on one base material and on this first dielectric film.Those methods also can be included on this first dielectric film to be carried out first and is etched with the top that removes this first dielectric film of having annealed, and deposits one second dielectric film on etched first dielectric film.In addition, those methods can be included on this second dielectric film to be carried out second and is etched with the top that removes this second dielectric film, and this first and second dielectric film is carried out second annealing and formed this dielectric layer.The stress in this dielectric layer can be reduced in the top that removes this first and second dielectric film.
The embodiment of the invention also can more comprise come on the filling semiconductor base material with dielectric material between the multistage segmentation deposition process in crack.Those methods can comprise deposition one first dielectric film in the bottom in this gap, and carry out first annealing with this first dielectric film of annealing.Those methods can more comprise deposition one second dielectric film on this first dielectric film of having annealed, and carry out second annealing with this second dielectric film of annealing.
Other embodiments of the invention and feature some are described in the following content, and another part embodiment and feature then can see through personnel's acquistion and understanding by inspecting specification or enforcement the present invention of being familiar with this art.Can obtain according to method, equipment and the combination described in the specification and understand feature of the present invention and advantage.
Description of drawings
Figure 1A-when 1C demonstration comes filled dielectric material according to the embodiment of the invention, the profile of crack pattern between base material is interior;
Fig. 2 A and 2B show the method flow diagram according to embodiment of the invention deposition of dielectric materials on a base material;
Fig. 3 shows the dielectric deposition method flow diagram that comes deposition materials according to embodiment of the invention use elemental oxygen precursor;
Fig. 4 shows according to the flow chart of embodiment of the invention deposition with the method for heating dielectric material;
Fig. 5 A and 5B show according to the extra flow chart of embodiment of the invention deposition with the method for annealing dielectric material;
Fig. 6 A-6D shows the base material gap section figure that comes filled dielectric material according to the embodiment of the invention;
Fig. 7 A-7C shows the base material gap section figure that comes filled dielectric material according to the embodiment of the invention;
Fig. 8 A and 8B demonstration are deposited in the base material gap and the electron microscopic image of the dielectric material that deposits along base material ladder place according to the embodiment of the invention;
Fig. 9 A and 9B are presented in the base material gap and the electron microscopic image of the dielectric material comparative example that deposits along base material ladder place.
The primary clustering symbol description
102 base material 104a-c gaps
104d irrigation canals and ditches 106 dielectric materials
200,250,300,400,500,550 methods
202,204,206,208,210 steps
252,254,256,258 steps
302,304,306,308,310 steps
402,404,406,408,410,412,414,416 steps
502,504,506,508 steps
552,554,556,558 steps
602 base materials, 604 a-c gaps
606 irrigation canals and ditches, 608 first dielectric films
610 second dielectric films
702 base materials, 704 first dielectric films
706a-c gap 708 irrigation canals and ditches
710 second dielectric films
Embodiment
The embodiment of the invention comprise several be used for deposition of dielectric materials in substrate surface between method and system in crack and the irrigation canals and ditches.With reference to this paper content, those dielectric materials comprise the silicon oxide film that is widely used in this area, form but the present invention is not limited to any certain thin films.Have excellent gap filling characteristic according to the dielectric film that the technology of the present invention deposited, and can fill the high-aspect-ratio gap that for example in shallow trench isolation (STI) structure, may meet with.The dielectric material that utilizes the inventive method and system to deposit is particularly suitable for being used for filling 100 nanometers or more small dimension, for example gap in the technology such as 65 nanometers or 45 nanometers.
The dielectric deposition is included in and forms flowable dielectric material on the base material, in the bottom that is gathered in base material gap or irrigation canals and ditches in deposition process.Because flowable dielectric material tendency, therefore can reduce dielectric material and be blocked in around the end face of gap to a bottom that is from the gap top mobile, thereby reduces near the chance that produces hole between filling up the center, crack.
After partly filling or filling up this gap fully, can be by handling flowable dielectric material with this dielectric material that hardens such as processing methods such as curing, baking, annealing or etchings.These processing methods can reduce hydroxyl and the water vapour content in the dielectric material that can flow usually, and the size of physical property ground reduction deposit film, thereby improve its density.Yet when film shrank, film often broke (for example, hallrcuts) and dielectric property, barrier performance matter and the supportive of deposition of dielectric materials is caused harmful effect.The size of these slight cracks and quantity common the thickness of the dielectric film that deposited increase and increase.
When flowable dielectric deposition in the 104a to 104d of base material gap and after treatment, formed gap pattern (gap pattern) profile is shown in Figure 1A to 1C in the base material 102.Figure 1A shows the base material 102 of the pattern with gap 104a-d, and it comprises a plurality of narrow gap 104a-c and a broad gap 104d.Gap 104a-c has about 3:1 or higher depth-to-width ratio, for example about 5:1 or higher, 8:1 or higher, 10:1 or higher, 12:1 or higher.Base material can be made by semi-conducting material, for example silicon of silicon, doping, GaAs, and on this base material, have such as multiple circuit unit such as transistor, contact mat and form an integrated circuit.Base material can be semiconductor wafer, for example the wafer of 100 millimeters, 150 millimeters, 200 millimeters, 300 millimeters, 400 millimeters equidimensions.Base material 102 also can comprise one or more extra rete, dielectric layer (as contact layer, pmd layer, IMD layer etc.) for example, and in those layers, form gap 104a-d.
Figure 1B shows the base material 102 that has deposited after the dielectric material 106 of can flowing.The dielectric material that can flow can be the dielectric material of silica type, and it is by containing the oxygen precursor and siliceous precursors reaction forms.For example, can form oxide dielectric material with reacting by the oxygen atom free radical that makes long-range generation (that is, containing the oxygen precursor) such as tetramethyl orthosilicate organosilicon precursors such as (tetramethylorthosilicate) (that is, containing silicon precursor).
About can the flow example and the details of method of dielectric constituent of deposition can be consulted following commonly assigned U.S. patent application case, be respectively application on October 16th, 2006 and title U.S. patent application case sequence number 11/549930 for " FORMATIONOF HIGH QUA LITY DIELECTRIC FILMS OF SI LICON DIOXIDE FORSTI:USAGE OF DIFFERENT SILOXANE-BASED PRECURSORS FORHARP II-REMOTE PLASMA ENHANCED DEPOSITION PROCESSES ", and on May 29th, 2007 applied for and title is the U.S. patent application case sequence number 11/754440 of " CHEMICAL VAPOR DEPOSITION OF HIGH QUALITY FLOW-LIKESILICON DIOXIDE USING A SILICON CONTAINING PRECURSORAND ATOMIC OXYGEN ", and those patent application cases are included in herein for your guidance in full.
Shown in example in, the dielectric material 106 of can flowing is partly filled this gap 104a-d.The flowability of this dielectric material cause dielectric material from the top mobile of gap 104a-d to the gap bottom, and increase the film thickness of bottom, gap.The rate travel of dielectric material is looked closely film viscosity and technological parameter and is decided, for example depositing temperature.
Fig. 1 C is presented in the post-depositional dielectric material processing procedure, the dielectric material varied in thickness of crack 104c between one of them is partly filled.Shown in arrow among the figure, this processing has reduced the thickness of the dielectric material 106 that is deposited along 104c bottom surface, gap and sidewall, and the thickness that has reduced the dielectric material 106 that covers on the end face of gap.The clear effect of this contraction is to have expanded sidewall and the bottom formed depression of the dielectric material of processing partly among the 104c of this gap.The physical size of the dielectric material of having handled as mentioned above, changes also may cause film breaks.
Can carry out the reduction film dimensions and improve in the process of treatment step of density of film or before, this film of first etching is to reduce or eliminate the film breaks situation.For example, can on the film of new deposition, carry out etching step to remove the top of this film.This etching step can reduce the stress that may cause film breaks on the film in follow-up densification steps.After etching step, can before or after the dielectric film of etching has been handled to this, deposit extra dielectric material.And can carry out another time etching to the extra dielectric material that is deposited.
Fig. 2 A and 2B are flow chart, its show according to the embodiment of the invention be used for depositing with etching one base material on the demonstration methods 200 of dielectric material.The method 200 that is shown among Fig. 2 A comprises that deposition one the first film 202 is on base material.This film is flowable dielectric film, and it is deposited on the base material with one or more gap and/or irrigation canals and ditches.
For example, first dielectric film that is deposited can comprise by organosilicon precursor and contain the formed silicon oxide dielectric material of oxygen precursor.Organosilicon precursor can comprise one or more following compounds: dimethylsilane (dimethylsilane), trimethyl silane (trimethylsilane), tetramethylsilane (tetramethylsilane), diethylsilane (diethylsilane), trimethoxy silane (trimethoxysilane, TriMOS), positive esters of silicon acis (the tetramethylorthosilicate of tetramethyl, TMOS), triethoxysilane (triethoxysilane, TriEOS), tetraethyl orthosilicate ester (tetraethylorthosilicate, TEOS), prestox three silica (octamethyltrisiloxane, OMTS), prestox ring four silica (octamethylcyclotetrasiloxane, OMCTS), tetramethyl cyclotetrasiloxane silica (tetramethylcyclotetrasiloxane, TOMCATS), DMDMOS, DEMS, methyl triethoxysilane (methyl triethoxysilane, MTES), phenyl dimethylsilane (phenyldimethylsilane) and/or phenyl silane (phenylsilane).Contain the oxygen precursor and comprise elemental oxygen (atomic oxygen), it is produced by oxygenated species in long-range, and those oxygenated species are oxygen molecule (O for example
2), ozone (O
3), nitrogen dioxide (NO
2), nitrous oxide (N
2O is commonly called as laughing gas), peroxide (for example, hydrogen peroxide (H
2O
2)) and steam (H
2O) or other oxygenated species.Those precursors also can with other additional gas and usefulness, for example help to carry those precursors to the carrier gas of cvd reactive chamber (as, hydrogen, helium, nitrogen, argon gas), and steam, peroxide and/or preceding his hydroxyl species guide in the cvd reactive chamber.
In some example of method 200, the first film that is deposited can fill up those gaps fully, even continues to be deposited into final thickness and be higher than those gaps.In other example, this first film can partly be filled the gap, for example those gaps is filled 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80% or 90%.
Continue after deposition step 202, remove the top (step 204) of this first dielectric film.Can reach by the film that etching should newly deposit and remove action.For example, can use such as this film of fluorine atom isoreactivity etchant chemistry ground dry ecthing.Can in plasma, dissociate one or more such as nitrogen fluoride (NF
3) and/or fluorine-containing precursor such as organic fluoride produce active fluorine.Etchant also can comprise oxygen, ozone and/or hydrogen.In other example, can be by film being exposed in the plasmas such as helium, argon or nitrogen and this film of plasma etching, wherein can utilize remote plasma system or the microwave feeds device of position to produce those plasmas, or utilize the ICP of this reative cell inside or CCP generator to produce those plasmas in this reative cell inside in the reative cell outside.
In certain embodiments, the top portion that removes accounts for 10%, 20%, 30%, 40%, 50%, 60% etc. of film thickness.If this first film position of initial deposition is on the end face of gap or irrigation canals and ditches or when being higher than end face, this removes the removable enough materials of step 204, so that the horizontal plane of dielectric material is lower than the end face of those gap/irrigation canals and ditches.In other embodiments, remove the dielectric material of the removable a part of position of step 204, but the quantity not sufficient that is removed is to allow the horizontal plane of this dielectric material be lower than the end face of those gap/irrigation canals and ditches in this gap/irrigation canals and ditches top face.When this first film of initial deposition is lower than the end face of those gap/irrigation canals and ditches, remove the amount that step 204 can further reduce the first film in the irrigation canals and ditches.
In certain embodiments, can remove step 204 during or thereafter, handle this first film with sclerosis and improve the density of this film.This treatment step can comprise processing methods such as baking (that is, thermal annealing), radiation annealing, plasma cured, electronic beam curing and/or ultraviolet light polymerization film, or other processing method.For example, can be in 600 ℃ of Gao Yueda, for example under about 300 ℃ to 400 ℃ temperature, the about at the most 1 hour time section of baking (annealing) this film, for example stoving time was between about 1 minute to 1 hour.In the example of radiation annealing, film is exposed under the thermal radiation (for example far infrared) of being emitted from the thermolamp pipe, so that film temperature raises.The example of radiation annealing is as rapid thermal annealing (RTA).Plasma cured and electronic beam curing reaction then can be reached by film is exposed to respectively under plasma and the electron beam.This plasma can be in containing the reative cell of base material, produced induce coupling plasma (ICP) or capacitive coupling plasma (CCP).Ultraviolet light polymerization reaction can get off to reach by film being exposed to radiant light that frequency is mainly the ultraviolet light frequency.Can utilize laser and/or incandescent source to produce this radiant light.
After the step 204 that removes the first dielectric film top, and after the first dielectric film treatment step in certain embodiments, can on remaining the first film, deposit one second dielectric film.Same precursor and sedimentary condition used in the time of can using and deposit first dielectric film deposit second dielectric film.For example, first and second dielectric film can be to use identical organosilicon precursor and contain the oxygen precursor and deposit the silicon oxide film that forms.In other embodiments, second film can use precursor different with the first film and process conditions, and constituted by the dielectric material kind that is different from the first film, for example can use silicon nitride or silicon oxynitride to replace silicon oxide dielectric material and constitute second film.
Second dielectric film also is flowable dielectric material.When remaining the first film is lower than the end face of gap/irrigation canals and ditches, can fills all the other parts of those gap/irrigation canals and ditches by second film, and continue to fill up to exceeding those gap/irrigation canals and ditches one segment distances.Be lower than among the embodiment of gap/irrigation canals and ditches end face at the first film, the volume that second film is filled can be less than the total surplus volume in those gap/irrigation canals and ditches.In these embodiments, can carry out one or repeatedly extra deposition step to fill up those gap/irrigation canals and ditches fully.
Be similar to first dielectric film, can continue after embryo deposit, remove the top (removing step 208) of second dielectric film.Remove second film that step 208 removes and partly can be equal to first and remove partly, or remove that percentage that step 208 removes the film amount can be less than or more than in first amount that removes in the step 204 to be removed.In certain embodiments, can before second dielectric film is lower than the end face of those gap/irrigation canals and ditches, just stop second and remove step 208, perhaps in other embodiments, second to remove residue second dielectric film that step 208 remains be the end face that is lower than those gap/irrigation canals and ditches.
The residue of this first and second dielectric film is partly carried out annealing steps 210.Annealing steps 210 can be thermal annealing (that is, baking), plasma annealing, ultraviolet light annealing, infrared ray (IR) annealing (as RTA), electron beam annealing and/or microwave annealing, or other method for annealing.For example, annealing steps 210 can be thermal annealing, be base material temperature is adjusted between about 300 ℃ to 1000 ℃, for example between about 650 ℃ to about 950 ℃, and continue one section between about 1 minute to about 1 hour time section.Anneal environment (anneal atmosphere) is inert gas environment (as nitrogen, helium, neon, argon, hydrogen etc.) for example, and/or the environment of aerobic environment (for example nitrogen dioxide, nitrous oxide, water, hydrogen peroxide, oxygen, ozone etc.) or other kind.The pressure of anneal environment is between about 0.1 holder ear (Torr) restriction, 100 holder ears, for example approximately between 1 to 2 holder ear.Annealing steps 210 is normal can to improve the density of dielectric material of having annealed, and reduces the etch-rate of annealed material, and the wet etching speed that for example lowers annealed material is than (WERR).
Fig. 2 B shows the method 250 according to the one layer or more dielectric materials layer in embodiment of the invention deposition and etching base material gap or the irrigation canals and ditches.Method 250 comprises that deposition one dielectric layer is to base material gap/irrigation canals and ditches 252 and the top that removes institute's dielectric layer 254.Subsequently, judge this has deposited with etched dielectric material whether fill up this irrigation canals and ditches 256, judge just whether this dielectric film reaches this gap end face or be higher than this gap end face.If this dielectric material does not fill up this gap as yet fully, then continue deposition and the extra dielectric film of etching in this gap, and carry out another time determining step to judge whether this gap is filled up fully.
When through once, twice, three inferior deposition steps 252 be with the circulation that removes step 254 after making the gap fill up dielectric material fully, can be to this (a bit) dielectric film execution annealing steps 258.As mentioned above, annealing steps 258 can be thermal annealing (baking), plasma annealing, ultraviolet light annealing, infrared radiation annealing (RTA), electron beam annealing and/or microwave annealing, or the annealing of other kind.
Consult the flow chart of Fig. 3, its demonstration uses an elemental oxygen precursor to come the demonstration methods 300 of deposition of dielectric materials according to the embodiment of the invention.Method 300 comprises mixes an elemental oxygen precursor and the step 302 of a silicon precursor and the step 304 of reacting those precursors, with deposition one dielectric film in gap on the semiconductor base material or the irrigation canals and ditches.Elemental oxygen can be in this cvd reactive chamber original position produce, or in long-range generation and be delivered in this cvd reactive chamber.For example, oxygen, ozone, nitrogen dioxide, nitrous oxide etc. contain the oxygen precursor and form the elemental oxygen species can to use remote plasma generation system for example to dissociate, carry those elemental oxygen species subsequently to cvd reactive chamber, and mix with other precursor (for example containing the crack precursor) and react with deposition of dielectric materials (step 306).
Continue after the deposition step 306, in etching step 308, remove the top of this dielectric film.For example, be mainly silica (SiO when dielectric material
x) time, the film that is deposited is exposed in the active fluorine to remove the top of this sull, wherein open-assembly time is approximately between extremely about 1 minute 1 second, and can be by will be such as fluorine precursor delivery such as Nitrogen trifluorides to the base material place and (for example dissociate, plasma dissociates) and produce active fluorine, for example the flow velocity with 1500sccm is delivered to Nitrogen trifluoride in the reative cell and about 1 to the 2 holder ear of reative cell total pressure.Active fluorine and silica react and formation fluorinated silicon compound, for example silicon tetrafluoride (SiF
4), these fluorinated silicon compounds are volatilizable and remove from the dielectric material that is deposited.
After removing step 308, can carry out annealing steps 310 with density that improves this film and the etch-rate that reduces film to remaining dielectric material.Annealing steps 310 can be thermal annealing (baking), plasma annealing, ultraviolet light annealing, ir annealing (for example RTA), electron beam annealing and/or microwave annealing, or the method for annealing of other kind.
The flow chart of Fig. 4 shows according to the method 400 of embodiment of the invention deposition with the heating dielectric material.Method 400 comprises a multistage segmentation heating process, and it is before removing the top of this film, and first dielectric film that Schilling is deposited heats with three kinds of different temperatures in three phases.Method 400 starts from step 402, and step 402 is that deposition one dielectric film is on the base material with one or more gap and/or irrigation canals and ditches.This film can partly be filled or those gaps of complete filling.
Continue after the deposition step 402, in heating steps 404, this film is heated to first temperature (for example up to about 50 ℃) continues a very first time section (for example about 1 hour).Subsequently, in step 406, adjust this film to one second temperature (for example about 50 ℃ to about 100 ℃) and continue one second time section, for example about 30 minutes.In step 408, adjust this film to one the 3rd temperature (for example about 100 ℃ to about 600 ℃) afterwards again and continue one the 3rd time section, for example about 30 minutes to 1 hour.Also can carry out extra heating steps, but not be shown among the figure.
Behind multistage segmentation heating process, in removing step 410, remove the top of this first dielectric material.Can chemical wet or dry etching process finish this and remove step.Subsequently, in deposition step 412, one second dielectric film is deposited on remaining first dielectric film, and in step 414, removes the top of this second dielectric film.
Carry out subsequently annealing steps 416 anneal this first and second dielectric film residue partly, to improve the density of those films.Can be in the environment of dry and non-reacted (for example, nitrogen, helium or the like) carry out annealing steps 416 with higher temperature such as about 800 ℃ or for example about 850 ℃, 900 ℃, 950 ℃, 1000 ℃.
Consult the flow chart of Fig. 5 A and 5B, it shows according to the method 500 and 550 of embodiment of the invention deposition with the annealing dielectric material.Fig. 5 A display packing 500, this method 500 comprise the circulation of alternately carrying out deposition and annealing steps, filling up gap or the irrigation canals and ditches in the base material fully, or partly fill up those gaps or irrigation canals and ditches.Method 500 can comprise the deposition step 502 of deposition the first film in gap and/or irrigation canals and ditches, and the annealing steps 504 of this film of annealing.Subsequently, in deposition step 506, deposit second dielectric film on this first film, and carry out annealing steps 508 with this second dielectric film of annealing.The temperature (for example, approximately up to 600 ℃) of carrying out first annealing steps 504 is lower than the temperature (for example second temperature is approximately up to 1000 ℃) of this second annealing steps 508.Method 500 also can be included in the step that removes the top of this first film before or after the annealing steps 504, and the step that removed the top of this second film before or after annealing steps 508.
Fig. 5 B shows and alternately to carry out one or the another kind of method 550 of deposition and the circulation of etching dielectric material repeatedly, the sustainable execution of the circulation of this alternating deposit and etching dielectric material is filled up dielectric material fully in gap and/or irrigation canals and ditches till.Method 550 comprises the deposition step 552 in the irrigation canals and ditches of deposition one dielectric layer to the base material, and the annealing steps 554 of this dielectric layer of annealing.After first deposition and anneal cycles, carry out and judge the step 556 whether these irrigation canals and ditches have filled up dielectric medium.If irrigation canals and ditches are to fill up, then in step 558, finish the irrigation canals and ditches fill process, and no longer carry out deposition-anneal cycles.If irrigation canals and ditches do not fill up as yet, then carry out the circulation of at least once deposition step 552 and annealing steps 554, with further filled dielectric material in irrigation canals and ditches.
Fig. 6 A to 6D shows according to the embodiment of the invention and fills base material gap section figure behind the two layers of dielectric materials layer continuously.Fig. 6 A shows a part of base material 602, has formed gap 604a-c and irrigation canals and ditches 606 in this base material 602.As mentioned above, base material 602 can be by made such as semi-conducting materials such as silicon, and can be for example about 100,150,200,300, the 400 millimeters silicon wafer of diameter.First dielectric film 608 is filled those gaps 604a-c and irrigation canals and ditches 606 partially.Dielectric film 608 can be flowable dielectric material, for example the oxide of silica, nitride, carbon containing, nitrogen oxide or other dielectric material.
Fig. 6 B be presented at remove the film top after, remaining first dielectric film 608 in those gaps 604a-c and the irrigation canals and ditches 606.In this embodiment, remove step the film 608 that all exceed gap and irrigation canals and ditches end face is all eat-back, and make film towards those gaps and irrigation canals and ditches inner recess.After removing the film top, and before the deposition subsequent film, on this remaining film 608, carry out density and the hardness of a treatment step to improve this residue film 608.
Fig. 6 C shows second dielectric film 610 that is deposited on remaining first dielectric film 608.Second dielectric film 610 fills up those gaps 604a-c and irrigation canals and ditches 606 fully, and further extends above the end face of those gaps and irrigation canals and ditches.Second dielectric film 610 also can be formed by a flowable dielectric material, and its composition is identical with the composition of first dielectric film 608.
Remove the top of this second dielectric film 608, in those gaps 604a-c and irrigation canals and ditches 606, to form the smooth dielectric filler as shown in Fig. 6 D.The same quadrat method that can use and remove these the first film 608 tops removes the top of this second film 610.Can before or after the top that removes this second film 610, on this first and second film, carry out an annealing steps.Annealing steps can be thermal annealing (baking), plasma annealing, ultraviolet light annealing, ir annealing (for example RTA), electron beam annealing and/or microwave annealing, or the annealing way of other kind.
Consult Fig. 7 A to 7C, it shows the profile in several base material gaps, and the with good grounds embodiment of the invention deposits first dielectric film and second dielectric film on those gaps.In Fig. 7 A, first dielectric film 704 has filled up gap 706a-c and the irrigation canals and ditches 708 in the base material 702 fully.Remove the top of this first dielectric film as subsequently shown in Fig. 7 B.Then remaining first dielectric film is handled, for example carried out annealing in process.Afterwards, deposit second dielectric film 710 on this base material 702.
Second dielectric film 710 can be a flowable dielectric material, and it is to form in the condition deposit identical with deposition first dielectric film 704, perhaps can use different deposition processs to deposit this second dielectric film 710.For example, can utilize traditional subatmospheric chemical vapor deposition method to deposit second dielectric film 710, for example HARP, high density plasma chemical vapor deposition technology (HDP-CVD) or plasma enhanced chemical vapor deposition technology (PECVD), or other can be used to the technology of deposition of dielectric materials.Then, can carry out such as etching or chemical mechanical milling method with subsequent steps such as those dielectric film tops of planarization before or after, this first and second dielectric film of annealing.
Embodiment
Fig. 8 A and 8B show according to the base material gap behind embodiment of the invention deposition and the etching dielectric material and the electron microscopic image at base material ladder place.Fig. 8 A shows a succession of gap that has deposited the silicon oxide dielectric film that can flow in it.Fig. 8 B shows the ladder place that is covered by identical flowable sull in the base material.Shown in two figure, before this dielectric film is carried out annealing steps, if the dielectric film that first etching deposited, just can eliminate slight crack in the final film after the annealing.
Make elemental oxygen and TMOS reaction can form silicon oxide film.From oxygen molecule source (O
2) produce elemental oxygen, and with the flow velocity of 1400sccm elemental oxygen is delivered in the cvd reactive chamber that includes base material.It is indoor that TMOS is that the flow velocity with 1850mgm is supplied to deposition reaction, and the pressure of this cvd reactive chamber keeps about 1.5 holder ears in the deposition process.This is the low temperature oxide depositing operation, and the temperature of its wafer substrate remains on 50 ℃ approximately.
After deposition step, use active fluorine to carry out dry chemical and be etched with etching oxidation silicon.The precursor of active fluorine is Nitrogen trifluoride (NF
3), and with the flow velocity of 1500sccm it is delivered in the reative cell that includes base material.The total pressure of reative cell is kept about 1.6 holder ears, make Nitrogen trifluoride carry out plasma and dissociate, and base material is exposed in the active fluorine about 10 seconds.Containing under the environment of ozone subsequently, with this etched base material of 400 ℃ annealing temperatures.
Fig. 9 A and 9B show between the electron microscopic striograph 9A of comparative example of base material gap (Fig. 9 A) and base material ladder place (Fig. 9 B) and the 9B between silicon oxide dielectric material contained in the crack and Fig. 8 A and the 8B that silicon oxide dielectric material contained in the crack and ladder place is identical.Yet, in this comparative example, before annealing, the dielectric material that is deposited is not carried out etching.As shown in Fig. 9 A, the situation that dielectric material breaks takes place in those gaps.
Need be appreciated that, if in the literary composition when being loaded with number range, unless clear regulation is arranged in the literary composition in addition, otherwise each numerical value (unit is to the one digit number of the ten minutes of the unit of this lower limit numerical value) numerical value that is in the literary composition to be disclosed between two parties between this scope bound.And any two illustrating between the numerical value in scope described in the literary composition, two is between two parties between the numerical value or arbitrary numerical value and more also being encompassed in the scope of the invention between the numerical value between two parties be shown.These bounds more among a small circle can be included in this scope or this middle eliminating certainly.And comprise bound wherein one, both or do not contain upper lower limit value those more also belong to the scope of the invention, whether look closely has any given row to remove boundary value and decide in the shown scope.When shown scope comprises the wherein one or both of this two boundary value, the scope except those boundary values also belongs to the present invention.
When " one ", " and ", when term such as " being somebody's turn to do " is used in this paper and the claim, unless clear the appointment arranged in the literary composition in addition, otherwise those terms also comprise several meaning.Therefore, for example " technology " may comprise the meaning of several technologies, and " this precursor " also may refer to the equivalent known in one or more precursor and the known field thereof.
In addition, when using terms such as " comprising ", " comprising ", " containing ", " having " in specification and the claim, with be intended to list desire characteristic specified, integer, member or step, do not have extra one or more further feature, integer, member, step or group but do not get rid of.
Claims (54)
1. method that reduces film breaks in the dielectric layer, this method comprises:
Deposit first dielectric film on base material;
This film of etching is to remove the top of this first dielectric film;
Deposit second dielectric film on this etched first dielectric film;
Remove the top of this second dielectric film; And
This first and second dielectric film of annealing, to form this dielectric layer, wherein, the stress in this dielectric layer is reduced at the top that removes this first and second dielectric film.
2. the method for claim 1, the step that wherein deposits this first and second dielectric film comprises:
In cvd reactive chamber, mix organosilicon precursor and elemental oxygen; And
React those precursors, to form silicon oxide layer on this base material.
3. method as claimed in claim 2, wherein this elemental oxygen is to produce in that this deposition reaction is outdoor.
4. method as claimed in claim 2, wherein this elemental oxygen is to form through the following steps:
Form plasma by the admixture of gas that contains argon gas; And
The oxygen precursor is imported in this plasma, make this oxygen precursor formation elemental oxygen that dissociates.
5. method as claimed in claim 4, wherein this oxygen precursor is selected from by oxygen molecule, ozone, nitrogen dioxide (NO
2), nitrous oxide (N
2O) in the group that is constituted with water.
6. method as claimed in claim 2, wherein this elemental oxygen forms through the following steps:
Guiding oxygen precursor enters in the photodissociation reative cell; And
This oxygen precursor is exposed under the ultraviolet light, and wherein this ultraviolet light is dissociated into elemental oxygen with this oxygen precursor.
7. method as claimed in claim 2, wherein this organosilicon precursor comprises dimethylsilane, trimethyl silane, tetramethylsilane, diethylsilane, trimethoxy silane, tetramethoxy orthosilicate, triethoxysilane, tetraethyl orthosilicate ester, prestox three silica, prestox ring four silica, tetramethyl cyclotetrasiloxane silica, DMDMOS, DEMS, methyl triethoxysilane, phenyl dimethylsilane or phenyl silane.
8. the method for claim 1, wherein the step of this first dielectric film of etching is wet etching or dry ecthing.
9. the method for claim 1, wherein the step of this first dielectric film of etching is a dry etching steps, it is the etching gas that this first dielectric film is exposed to fluoride.
10. method as claimed in claim 9, wherein this etching gas comprises Nitrogen trifluoride or organic fluoride.
11. method as claimed in claim 10, wherein this organic fluoride comprises CF
4, C
2F
6Or C
3F
8
12. the method for claim 1, wherein the step of this first dielectric film of etching is a wet etching, and it is that this first dielectric film is exposed to acid solution.
13. method as claimed in claim 12, wherein this acid solution comprises hydrofluoric acid, hydrochloric acid, phosphoric acid, nitric acid or sulfuric acid.
14. method as claimed in claim 12, wherein this acid solution more comprises hydrogen peroxide.
15. the method for claim 1, wherein the step of this first dielectric film of etching is a wet etching, and it is that this first dielectric film is exposed to alkaline solution.
16. method as claimed in claim 15, wherein this alkaline solution comprises ammonium hydroxide.
17. method as claimed in claim 16, wherein this alkaline solution more comprises hydrogen peroxide.
18. method as claimed in claim 8, wherein this etching step is a wet etching, and the step that wherein deposits this first dielectric film and this first dielectric film of etching is to carry out in same reative cell.
19. method as claimed in claim 8, wherein this etching step is a wet etching, and this etching step is to carry out in the reative cell different with the reative cell that is used for depositing this first dielectric film.
20. the method for claim 1, wherein the original depth of this first dielectric film between about 1 nanometer between about 100 nanometers.
21. the method for claim 1, wherein this method is included in before the top that removes this first dielectric film, this first dielectric film of annealing.
22. the method for claim 1, wherein this method is included in before this second dielectric film of deposition, this first dielectric film of annealing.
23. fill the method for irrigation canals and ditches with a dielectric material for one kind, this method comprises:
Fill this irrigation canals and ditches with the film that this dielectric material was constituted, wherein this dielectric film is to form through the following steps:
Mix the first fluid and second fluid, this first fluid comprises elemental oxygen, and this second fluid comprises and contains silicon precursor;
React this elemental oxygen and this and contain silicon precursor in these irrigation canals and ditches, to form this dielectric film;
Remove the top of this dielectric film by this dielectric film of etching; And
This etched dielectric film of annealing.
24. method as claimed in claim 23, wherein this dielectric film of initial deposition extends beyond the end face of these irrigation canals and ditches.
25. method as claimed in claim 24, wherein this dielectric film is etched back to the end face that is lower than these irrigation canals and ditches.
26. method as claimed in claim 25, wherein cover cap is deposited upon on this dielectric film that has eat-back.
27. method as claimed in claim 26, wherein this cover cap layer comprises the dielectric material identical with this dielectric film.
28. method as claimed in claim 23, wherein the step of this film of etching is carried out with wet etching or dry ecthing.
29. method as claimed in claim 23, wherein the step of this film of etching is dry ecthing, and it is the etching gas that this film is exposed to fluoride.
30. a method that reduces film breaks in the dielectric layer, this method comprises:
Deposit first dielectric film on base material;
On this first dielectric film, carry out first annealing;
On this first dielectric film, carry out first etching, to remove the top of this first dielectric film of having annealed;
Deposit second dielectric film on this etched first dielectric film;
On this second dielectric film, carry out second etching, to remove the top of this second dielectric film; And
This first and second dielectric film is carried out second annealing and formed this dielectric layer, and the stress in this dielectric layer is reduced at the top that wherein removes this first and second dielectric film.
31. method as claimed in claim 30, wherein this first annealing comprises that this first dielectric film of heating is to the highest about 600 ℃ temperature
32. method as claimed in claim 30, wherein this first annealing is a multistage segmentation annealing, and it comprises following phases:
To heat this first dielectric film very first time section up to the first about 50 ℃ temperature;
To heat second time of this first dielectric film section to the second about 100 ℃ temperature between about 50 ℃; And
Heat the 3rd time of this first dielectric film section to be higher than about 100 ℃ to the 3rd about 600 ℃ temperature.
33. method as claimed in claim 32 wherein should comprise about 1 hour by very first time section, and this second time section comprises about 30 minutes.
34. method as claimed in claim 32, wherein the 3rd time section comprises about 30 minutes to about 1 hour.
35. method as claimed in claim 30, wherein this first annealing comprises: with this first film of UV-irradiation.
36. method as claimed in claim 30, wherein this first annealing comprises: this first film is exposed in the inertia plasma.
37. method as claimed in claim 30, wherein this first annealing comprises: this first film is exposed to electron beam.
38. method as claimed in claim 30, wherein this second annealing comprises: this first and second film of heating is to about 800 ℃ or higher temperature in the non-reactive gas environment of drying.
39. method as claimed in claim 38, non-reactive gas that wherein should drying comprises nitrogen.
40. method as claimed in claim 30, wherein this first etching is carried out with wet etching or dry ecthing.
41. method as claimed in claim 30, wherein this second etching is carried out with wet etching or dry ecthing.
42. method as claimed in claim 30, wherein this method more comprises:
Deposit the 3rd dielectric film on this first and second film; And
Remove the top of the 3rd dielectric film.
43. method as claimed in claim 42, wherein this method more comprises: anneal this first, second and the 3rd dielectric film to form this dielectric layer, wherein remove this first, second and the top of the 3rd dielectric film can reduce stress in this dielectric layer.
44. a multistage segmentation deposition process, to utilize a gap that contains on the semiconductor substrate that dielectric material fills, this method comprises:
Deposit the bottom of first dielectric film in this gap;
This first dielectric film of annealing in first annealing;
Deposit one second dielectric film on this first dielectric film of having annealed; And
This second dielectric film of annealing in second annealing.
45. multistage segmentation deposition process as claimed in claim 44, wherein this method comprises:
Deposit the 3rd dielectric film on this second dielectric film of having annealed; And
Annealing the 3rd dielectric film in the 3rd annealing.
46. multistage segmentation deposition process as claimed in claim 44, wherein this first annealing comprises thermal annealing, electron beam annealing, ultraviolet light annealing or plasma annealing.
47. multistage segmentation deposition process as claimed in claim 44, wherein this second annealing comprises thermal annealing, electron beam annealing, ultraviolet light annealing or plasma annealing.
48. multistage segmentation deposition process as claimed in claim 44, the temperature of wherein carrying out this first annealing is lower than the temperature of second annealing.
49. multistage segmentation deposition process as claimed in claim 48, wherein this first annealing is to carry out under the temperature of 600 ℃ of Gao Yueda, and this second annealing is to carry out under the temperature of 1000 ℃ of Gao Yueda.
50. multistage segmentation deposition process as claimed in claim 44, wherein this method comprises: before this second dielectric film of deposition, this first dielectric film of having annealed is carried out first etching.
51. multistage segmentation deposition process as claimed in claim 50, wherein this etching removes the top of this first dielectric film.
52. multistage segmentation deposition process as claimed in claim 50, wherein this etching comprises dry ecthing or wet etching.
53. multistage segmentation deposition process as claimed in claim 50, wherein this etching comprises: this film is exposed in the etching gas that contains fluoride.
54. multistage segmentation deposition process as claimed in claim 44, wherein this method comprises: this second dielectric film is carried out second etching.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US80557306P | 2006-06-22 | 2006-06-22 | |
| US60/805,573 | 2006-06-22 | ||
| US11/765,944 | 2007-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101473426A true CN101473426A (en) | 2009-07-01 |
Family
ID=40829570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007800231733A Pending CN101473426A (en) | 2006-06-22 | 2007-06-21 | Dielectric deposition and etch back processes for bottom up gapfill |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101473426A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103348776A (en) * | 2011-02-15 | 2013-10-09 | 应用材料公司 | Method and apparatus for multizone plasma generation |
| CN104425343A (en) * | 2013-08-28 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench isolation structure |
| CN104517891A (en) * | 2013-10-04 | 2015-04-15 | 台湾积体电路制造股份有限公司 | Method for forming trench structure |
| CN105899711A (en) * | 2014-01-24 | 2016-08-24 | 应用材料公司 | Deposition of silicon and oxygen-containing films without an oxidizer |
| CN107039264A (en) * | 2015-12-18 | 2017-08-11 | 朗姆研究公司 | Orientated deposition on pattern structure |
| CN109599361A (en) * | 2017-09-29 | 2019-04-09 | 台湾积体电路制造股份有限公司 | The manufacturing method of semiconductor structure |
| CN111133561A (en) * | 2017-09-22 | 2020-05-08 | 应用材料公司 | Method for reducing pore diameter using atomic layer deposition and etching |
| US12165878B2 (en) | 2019-02-27 | 2024-12-10 | Lam Research Corporation | Semiconductor mask reshaping using a sacrificial layer |
| US12261044B2 (en) | 2020-02-28 | 2025-03-25 | Lam Research Corporation | Multi-layer hardmask for defect reduction in EUV patterning |
-
2007
- 2007-06-21 CN CNA2007800231733A patent/CN101473426A/en active Pending
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9809881B2 (en) | 2011-02-15 | 2017-11-07 | Applied Materials, Inc. | Method and apparatus for multizone plasma generation |
| CN103348776A (en) * | 2011-02-15 | 2013-10-09 | 应用材料公司 | Method and apparatus for multizone plasma generation |
| CN103348776B (en) * | 2011-02-15 | 2017-06-09 | 应用材料公司 | The method and apparatus of multi-region plasma generation |
| CN104425343A (en) * | 2013-08-28 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench isolation structure |
| CN104517891A (en) * | 2013-10-04 | 2015-04-15 | 台湾积体电路制造股份有限公司 | Method for forming trench structure |
| CN105899711B (en) * | 2014-01-24 | 2020-01-07 | 应用材料公司 | Deposition of silicon and oxygen containing films in the absence of oxidizing agents |
| CN105899711A (en) * | 2014-01-24 | 2016-08-24 | 应用材料公司 | Deposition of silicon and oxygen-containing films without an oxidizer |
| US10790139B2 (en) | 2014-01-24 | 2020-09-29 | Applied Materials, Inc. | Deposition of silicon and oxygen-containing films without an oxidizer |
| CN107039264A (en) * | 2015-12-18 | 2017-08-11 | 朗姆研究公司 | Orientated deposition on pattern structure |
| CN111133561A (en) * | 2017-09-22 | 2020-05-08 | 应用材料公司 | Method for reducing pore diameter using atomic layer deposition and etching |
| US10994991B2 (en) | 2017-09-22 | 2021-05-04 | Applied Materials, Inc. | Method to reduce pore diameter using atomic layer deposition and etching |
| CN109599361A (en) * | 2017-09-29 | 2019-04-09 | 台湾积体电路制造股份有限公司 | The manufacturing method of semiconductor structure |
| CN109599361B (en) * | 2017-09-29 | 2021-04-09 | 台湾积体电路制造股份有限公司 | Manufacturing method of semiconductor structure |
| US11289343B2 (en) | 2017-09-29 | 2022-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of gap filling using conformal deposition-annealing-etching cycle for reducing seam void and bending |
| US11605543B2 (en) | 2017-09-29 | 2023-03-14 | Taiwan Semiconductor Manufacturing Company. Ltd. | Method of gap filling using conformal deposition-annealing-etching cycle for reducing seam void and bending |
| US12183590B2 (en) | 2017-09-29 | 2024-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of performing gap filling including filling trenches between dummy gate stacks on semiconductor fins/strips with semiconductor material |
| US12165878B2 (en) | 2019-02-27 | 2024-12-10 | Lam Research Corporation | Semiconductor mask reshaping using a sacrificial layer |
| US12261044B2 (en) | 2020-02-28 | 2025-03-25 | Lam Research Corporation | Multi-layer hardmask for defect reduction in EUV patterning |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI400755B (en) | Dielectric deposition and etch back processes for bottom up gapfill | |
| US7033945B2 (en) | Gap filling with a composite layer | |
| US7888273B1 (en) | Density gradient-free gap fill | |
| CN101473426A (en) | Dielectric deposition and etch back processes for bottom up gapfill | |
| US7947551B1 (en) | Method of forming a shallow trench isolation structure | |
| KR101758944B1 (en) | Novel gap fill integration | |
| KR101698595B1 (en) | Pecvd flowable dielectric gap fill | |
| KR100579017B1 (en) | Low k pre-metal dielectric semiconductor structures | |
| US7335609B2 (en) | Gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials | |
| US9390914B2 (en) | Wet oxidation process performed on a dielectric material formed from a flowable CVD process | |
| JP5225268B2 (en) | A novel deposition plasma hardening cycle process to enhance silicon dioxide film quality | |
| KR101615814B1 (en) | Method of forming a shallow trench isolation structure | |
| US20130260564A1 (en) | Insensitive dry removal process for semiconductor integration | |
| JP2009152551A (en) | Method and system for improving dielectric film quality for void free gap filling | |
| US20070087522A1 (en) | Dielectric Gap Fill With Oxide Selectively Deposited Over Silicon Liner | |
| US9786542B2 (en) | Mechanisms for forming semiconductor device having isolation structure | |
| JP2009135450A (en) | Method for forming a dielectric layer in a trench | |
| CN104517891A (en) | Method for forming trench structure | |
| CN102171796A (en) | Methods for forming silicon nitride based film or silicon carbon based film | |
| CN103415914A (en) | Post-planarization densification | |
| CN102668061A (en) | Post-planarization densification | |
| US9312167B1 (en) | Air-gap structure formation with ultra low-k dielectric layer on PECVD low-k chamber | |
| US6589854B2 (en) | Method of forming shallow trench isolation | |
| KR20090002973A (en) | Method of forming insulating film, insulating film formed by this method and gap-fill method of semiconductor element using this method | |
| KR100908821B1 (en) | Method of forming insulating film of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C53 | Correction of patent for invention or patent application | ||
| CB02 | Change of applicant information |
Address after: American California Applicant after: Applied Materials Inc. Address before: American California Applicant before: Applied Materials Inc. |
|
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20090701 |