CN101399538B - An FPGA chip - Google Patents

Abstract

The invention relates to a FPGA chip which comprises a plurality of logic units. The logic units comprise a plurality of MRAMs which are based on a MTJ and form a logic array. The data in the MTJ is stored in a magnetic state and does not leak like charge as time goes on; therefore, in the power-down condition, the magnetization direction does not change, the data can be kept. Moreover, when electricity is supplied, the state of the stored data is induced by measuring the MTJ resistance, the state before the power-down can be quickly restored, and the FPGA restarts normal operation, which shortens starting time.

Description

An FPGA chip

technical field

The invention relates to the technical field of integrated circuits, in particular to a field programmable gate array chip based on a magnetic tunnel junction.

Background technique

FPGA field programmable gate array is a programmable device that designers can use software tools to quickly develop, simulate and test. FPGA provides high logic density and rich features, and is widely used in data processing and storage, as well as instrumentation, telecommunications and digital signal processing, etc., and has the advantages of short development cycle and high reliability.

At present, the traditional SRAM-based FPGA is the most commonly used variety on the market. The basic structure of FPGA based on SRAM memory is shown in Figure 1, which includes 3×3 logic unit CLB, data channel, and input module. By controlling the connection mode and working state of the logic unit CLB, the distribution of the overall working performance of the FPGA is completed. . Every time it works, the data in the SRAM memory is read into the CLB through the input module in the FPGA. Since SRAM is used as the storage element, data needs to be read externally every time the power is turned on. When there is power supply, SRAM can save the stored content, but once the power is turned off, the content stored in SRAM will automatically disappear.

Therefore, when the FPGA restarts after being powered off, it is necessary to re-read the storage content of the SRAM from the external interface. Only when the writing state in the SRAM is completed, the state of the internal state register in the FPGA can be determined and restored to the last time. The state before the power failure, and then the FPGA can resume normal operation, so the startup time is relatively long.

Below, the technical terms and abbreviations used in the present invention:

MTJ: Magnetic Tunnel Junction magnetic tunnel junction device;

MRAM: Magnetoresistive Random Access Memory magnetoresistive random access memory;

FPGA: Field Programmable Gate Array Field Programmable Gate Array, a programmable chip;

SRAM: Static RAM static random access memory;

CLB: Configurable Logic Block programmable logic unit.

Contents of the invention

In view of the existing problems in the above-mentioned prior art, the object of the present invention is to provide a FPGA chip based on MRAM, the MTJ in the MRAM can memorize the data state before power failure, so that the restart speed of FPGA is fast.

The purpose of the present invention is achieved through the following technical solutions:

A kind of FPGA chip, it comprises a plurality of logic unit, and this logic unit comprises MRAM memory, and a plurality of MRAM memory constitute logic array, and this MRAM memory comprises MTJ and the MOS field effect transistor that is connected with it, and this MTJ has fixed magnetic layer, thin Insulating tunnel isolation layer and free magnetic layer, the MTJ is connected to the positive input of an operational amplifier, the negative input of the operational amplifier is connected to a reference resistor, the resistance of the reference resistor is between the high and low resistance of the MTJ value between.

Wherein, the low resistance of the MTJ is the resistance of the MTJ when the magnetic moment direction of the free magnetic layer of the MTJ is parallel to the magnetic moment direction of the fixed magnetic layer.

Wherein, the high resistance of the MTJ is the resistance of the MTJ when the magnetic moment direction of the free magnetic layer is antiparallel to the magnetic moment direction of the fixed magnetic layer.

It can be seen from the technical solution provided by the present invention above that the present invention is an FPGA chip based on MRAM, and the data in the MTJ is stored in a magnetic state, which will not leak over time like electric charges, so in the case of power failure When the magnetization direction does not change, the data can be kept; and when the power is turned on, the stored data state is sensed by measuring the MTJ resistance, and the state is automatically "remembered", and the FPGA quickly restores the state before the last power failure. Get into normal work with reduced start-up time.

Description of drawings

Fig. 1 is the FPGA device structure schematic diagram based on SRAM of prior art;

Fig. 2 is the schematic diagram of the cross-sectional structure of the basic type MRAM memory of the present invention;

Fig. 3 is the structural representation of FPGA chip of the present invention;

Fig. 4 is the connection structure schematic diagram of MRAM and operational amplifier in the FPGA chip of the present invention;

Fig. 5 is the structural representation of operational amplifier in Fig. 4;

FIG. 6 is a schematic diagram of pin allocation of the inventive FPGA chip.

Detailed ways

As shown in Figure 3, an FPGA chip includes a controller, an input/output unit, a logic array composed of multiple logic units, and a data channel. By controlling the connection mode and working status of the logic units, the overall performance of the FPGA can be adjusted. distribute. The logic unit includes MTJ-based MRAM, and multiple MRAMs form a cross-arranged logic array (the number of logic units in the figure is only schematic and should not be interpreted as limiting), and the bit lines and digit lines span multiple logic units. , the intersection structure of the bit line and the digital line can make each logic unit can be easily accessed. The logic unit of the FPGA chip is realized by the MTJ device, and its logic function is realized by controlling the resistance value of the MTJ, so as to complete the distribution of the overall working performance of the FPGA.

As shown in FIG. 2 , the MTJ-based MRAM is fabricated by processing an MTJ and an N-channel MOS field effect transistor on a chip using an integrated circuit process. That is, this MRAM is a basic type. The MTJ has a fixed magnetic layer 1, a thin insulating tunnel isolation layer 2 and a free magnetic layer 3; the free magnetic layer 1 of the MTJ is connected to a metal bit line BL1; the fixed magnetic layer 3 of the MTJ is connected to a MOS field effect transistor 4 (MOSFET) The MOS field effect transistor 4 includes two highly doped source diffusion regions N+ and drain diffusion regions N+ made on a P-type silicon substrate, and the source S (Source) and the drain D (Drain) are drawn out respectively, And metal 6, metal 7, oxide SiO2; the gate of the MOS field effect transistor 4 is connected to the word line WL1; the digit line DL1 is arranged under the MTJ; the word line WL1 and the digit line DL1 are arranged in a column; the The bit lines BL1 are arranged in a row; the MTJ and the digit line DL1 are electrically isolated by the SiO layer of the MOS field effect transistor 4 .

It can be seen from Figure 2 that the bit line DL1 is used in the process of reading data and writing data in the MTJ memory, and the magnetization of the free magnetic layer 3 in the MTJ is jointly controlled by the current pulses in the mutually perpendicular bit line BL1 and digit line DL1. to decide. During the magnetization process, as shown by the spiral arrow in the figure, one wire provides the magnetic field in the direction of easy magnetization of MTJ, and the other wire provides the magnetic field in the direction of hard magnetization of MTJ. A peak value of the magnetic field is generated at the intersection of the two wires. This peak will exceed the switching threshold of the MTJ free magnetic layer 3 , so that the magnetization of the MTJ free magnetic layer 3 is reversed, and a reversal occurs. The magnetic moment direction of the fixed magnetic layer 1 is fixed. When the magnetic moment direction of the MTJ free magnetic layer 3 is antiparallel to the magnetic moment direction of the fixed magnetic layer 1, the MTJ has a high resistance (logic value 1). When the MTJ free When the magnetic moment direction of the magnetic layer 3 is parallel to that of the fixed magnetic layer 1, the MTJ has a low resistance (logic value 0).

When data is written into the MTJ, the word line WL1 controls the drain S and the source D of the MOS field effect transistor 4 to be cut off, and the bit line BL1 and the digit line DL1 have current flowing at the same time, and the current passes through the mutually perpendicular bit line BL1 and the digit line DLI generates two orthogonal magnetic fields at each intersection to write data.

When reading data, the word line WL1 controls the conduction between the drain D and the source S of the MOS field effect transistor 4, the current flows from the bit line BL1 and passes through the MTJ and the MOS field effect transistor 4, and the magnitude of the current pulse depends on the resistance of the MTJ Therefore, the data stored in the bit is determined by the size of the MTJ resistance.

Referring to Fig. 4, Fig. 5, FPGA chip of the present invention, its logic unit also comprises operational amplifier, the free magnetic layer of MTJ connects the positive input terminal V+ of operational amplifier, the negative input terminal V- of operational amplifier connects a reference resistance R _ref , the source S of the MOS field effect transistor is connected to the power supply, and the resistance value of the reference resistor R _ref is between the high and low resistance values of the MTJ. The three input terminals A, B, and C ₀ (bit line, digit line, and word line) of the MTJ device control the direction of the magnetic vector in its free magnetic layer, so that the equivalent resistance R corresponding to the MTJ can be obtained. Comparing, determining whether the resistance state is low or high and therefore the stored data, completes the realization of its logic function.

The MTJ-based FPGA chip of the present invention not only realizes its logic unit by MTJ devices, but also when the MTJ is powered off, the MTJ magnetization direction does not change, and the data can be kept. When the power is turned on, the MTJ resistance is sensed. The stored data state automatically "memorizes" the state, enabling the FPGA to quickly restore the state before the last power failure and enter normal work, shortening the start-up time. The present invention uses an operational amplifier, but does not exclude other devices known by those skilled in the art that can measure MTJ voltage and resistance. The operational amplifier is a relatively mature technology, so I won’t go into details, and its parameters are shown in the table below:

parameter value supply voltage 3.3V load capacitance 2pF A_DC ≥60dB UGBW ≥20MHz PM ≥70 SR ≥20V/μs Maximum output voltage swing V_DD-0.45V≥Vout≥0.45V

Referring to Figure 6, the MTJ-based FPGA chip has abundant I/O pins. The present invention is based on the MTJ FPGA chip, and the MRAM can be a basic type formed by processing an MTJ and a MOS field effect transistor in Fig. 3, or an existing improved MRAM, without limitation.

The FPGA chip is a semi-custom circuit in the field of application-specific integrated circuits, which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates. The FPGA chip based on MTJ solves the defect that the FPGA becomes white and the internal logic relationship disappears after the FPGA is powered off, and realizes that the FPGA can be restarted quickly.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present invention can easily think of changes or Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (3)

1. A kind of FPGA chip, it comprises a plurality of logic units, it is characterized in that, this logic unit comprises MRAM memory, and a plurality of MRAM memory forms logic array, and this MRAM memory comprises MTJ and the MOS field effect transistor that is connected with it, and this MTJ With a fixed magnetic layer, a thin insulating tunnel isolation layer, and a free magnetic layer, the MTJ is connected to the positive input of an operational amplifier whose negative input is connected to a reference resistor with a value between the Between the high and low resistance values of the MTJ, the equivalent resistance corresponding to the MTJ is obtained by controlling the signals input by the bit line, the digital line and the word line, and the operational amplifier compares the equivalent resistance corresponding to the MTJ with the reference resistance to realize the Logical function of a logical unit. 2. FPGA chip according to claim 1, is characterized in that, the low resistance of this MTJ is the resistance that MTJ has when the magnetic moment direction of MTJ free magnetic layer is parallel to the magnetic moment direction of fixed magnetic layer. 3. The FPGA chip according to claim 1, wherein the high resistance of the MTJ is the resistance of the MTJ when the direction of the magnetic moment of the free magnetic layer is antiparallel to the direction of the magnetic moment of the fixed magnetic layer.

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