CN101221960A - pixel structure - Google Patents

Abstract

The invention discloses a pixel structure, which is arranged on a substrate and electrically connected with a scanning line and a data line. The pixel structure includes a semiconductor pattern and a pixel electrode. The semiconductor pattern includes at least two channel regions, at least one doped region, and a source region and a drain region. The channel area is located below the scan line, wherein the channel area has different width-to-length ratios. The doped region is connected between the channel regions. The pixel electrode is electrically connected to the drain region, wherein the source region is connected between one channel region and the data line, and the drain region is connected between the other channel region and the pixel electrode. The scan lines have different widths above different channel areas, and a length of each channel area is equal to the width of the scan lines.

Description

pixel structure

technical field

The present invention relates to a pixel structure, and in particular to a pixel structure with a multi-channel area.

Background technique

Thin Film Transistor Liquid Crystal Display (TFT-LCD) has become the mainstream of many flat-panel displays. According to the choice of channel layer material, TFT-LCDs can be divided into two types: amorphous silicon TFT-LCDs and low-temperature polysilicon thin-film transistors (Low-Temperature PolySilicon Thin FilmTransistor, LTPS-TFT) LCDs.

Since the electron mobility of the low-temperature polysilicon thin film transistor can reach more than 200cm ² /V-sec, the area occupied by the thin film transistor element can be made smaller to meet the requirements of high aperture ratio (aperture), thereby increasing the display brightness of the display and reducing the overall power consumption problem. But relatively speaking, the low-temperature polysilicon thin film transistor also has a relatively high leakage current (about 10 ^-9 microampere), and it is easy to induce a hot carrier effect (hot carrier effect) at the drain (drain), and then cause component degradation. Therefore, nowadays, a light doped drain (LDD for short) is added between the channel region and the source/drain of the low-temperature polysilicon thin film transistor or the design of multiple channel regions is used to avoid the above-mentioned problems.

FIG. 1 is a pixel structure of a polysilicon thin film transistor liquid crystal display in the prior art. Referring to FIG. 1 , the pixel structure 100 includes a scan line 110 , a data line 120 , a polysilicon layer 130 and a transparent pixel electrode 140 . The scan line 110 has at least one L-shaped branch 112 , and the polysilicon layer 130 intersects the L-shaped branch 112 to form a first channel region 132 and a second channel region 134 . In addition, there are source regions 136 and drain regions 138 at both ends of the low temperature polysilicon layer 130 to form a multi-channel polysilicon thin film transistor 150 . The data line 120 is electrically connected to the source region 136 , and the transparent pixel electrode 140 is electrically connected to the drain region 138 . In addition, the overlapping portion of the polysilicon layer 130 and the pixel electrode 140 further forms a storage capacitor 152 . Due to the multi-channel design, the low temperature polysilicon thin film transistor 150 has a lower leakage current in the off state, which helps to improve the quality of the pixel structure 100 . However, the configuration of the L-shaped branch 112 will affect the location of the storage capacitor 152 and reduce the display aperture ratio of the pixel structure 100 .

Contents of the invention

The technical problem to be solved by the present invention is to provide a pixel structure to solve the problem that the display aperture ratio of the pixel structure is limited by multi-channel designed polysilicon thin film transistors.

To achieve the above object, the present invention provides a pixel structure, which is disposed on a substrate and electrically connected to a scan line and a data line. The pixel structure includes a semiconductor pattern and a pixel electrode. The semiconductor pattern includes at least two channel regions, at least one doped region, and a source region and a drain region. The channel area is located below the scan line, wherein the channel area has different width-to-length ratios. The doped region is connected between the channel regions. The pixel electrode is electrically connected to the drain region, wherein the source region is connected between one channel region and the data line, and the drain region is connected between the other channel region and the pixel electrode. The scan lines have different widths above different channel areas, and a length of each channel area is equal to the width of the scan lines.

In an embodiment of the present invention, the above-mentioned scan lines have different widths above different channel regions, and a length of each channel region is equal to the width of the scan lines.

In an embodiment of the present invention, the above scan line has a branch, and the branch is perpendicular to the scan line. At least one channel area is located below the branch, and the length of the channel area located below the branch is the same as the width of the branch.

In an embodiment of the present invention, the above-mentioned semiconductor pattern includes a polysilicon pattern.

In an embodiment of the present invention, the above-mentioned semiconductor pattern further includes a capacitor electrode electrically connected to the drain region and the pixel electrode, wherein the capacitor electrode is located below the pixel electrode. In addition, the pixel structure further includes a shared electrode disposed between the capacitor electrode and the pixel electrode.

In an embodiment of the present invention, the shape of the above-mentioned doped region includes L-shape or U-shape.

In an embodiment of the present invention, a part of the scan lines below the channel region, the source region and the drain region constitute a polysilicon thin film transistor.

Moreover, in order to achieve the above object, the present invention further provides a pixel structure including a scan line, a data line, a semiconductor pattern and a pixel electrode. The scanning lines and the data lines are arranged alternately, and have a branch, and the branch is located below the data lines. The semiconductor pattern includes at least two channel regions, at least one doped region, and a source region and a drain region. The channel area is located below the scan line, wherein the channel area has different width-to-length ratios. The doped region is connected between the channel regions. The pixel electrode is electrically connected to the drain region, wherein the source region is connected between one channel region and the data line, and the drain region is connected between the other channel region and the pixel electrode.

In an embodiment of the present invention, the above-mentioned channel region below the branch has the same length as the width of the branch.

In an embodiment of the present invention, the above-mentioned semiconductor pattern includes a polysilicon pattern.

In an embodiment of the present invention, the above-mentioned semiconductor pattern further includes a capacitor electrode electrically connected to the drain region and the pixel electrode, wherein the capacitor electrode is located under the pixel electrode. In addition, the pixel structure further includes a shared electrode disposed between the capacitor electrode and the pixel electrode.

In an embodiment of the present invention, the above-mentioned capacitive electrodes and branches are respectively located on two sides of the scan line.

In an embodiment of the present invention, the above-mentioned shape of the doped region includes an L shape.

In an embodiment of the present invention, the above-mentioned semiconductor pattern extends from the first side of the data line to the second side of the data line.

In an embodiment of the present invention, a part of the scan lines below the channel region, the source region and the drain region constitute a polysilicon thin film transistor.

The invention utilizes the change of the semiconductor pattern to make the semiconductor pattern intersect with the scanning line in at least two regions, thereby helping to reduce the leakage current of the polysilicon thin film transistor. In addition, the present invention arranges the branch of the scanning line below the data line, which can further prevent the display aperture ratio of the pixel structure from being affected. Overall, the pixel structure provided by the present invention has a high display aperture ratio and the polysilicon thin film transistor in the pixel structure has good electrical properties.

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

1 is a schematic diagram of a pixel structure of a polysilicon thin film transistor liquid crystal display in the prior art;

FIG. 2 is a schematic diagram of a pixel structure according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a pixel structure according to another embodiment of the present invention;

FIG. 4 is a schematic diagram of a pixel structure according to yet another embodiment of the present invention;

5A and 5B are schematic diagrams of two pixel structures according to another embodiment of the present invention;

FIG. 6 is a schematic diagram of a pixel structure according to yet another embodiment of the present invention.

Among them, reference signs:

100, 200, 300, 400, 500, 600: pixel structure

110, 210, 410, 510: scan lines

112, 412, 512: branches

120, 220, 520: data line

130: polysilicon layer

132, 134, 232A, 232B, 332A, 332B, 332C, 432, 532A, 532B, 632A, 632B, 632C: access area

136, 236, 336, 536: source region

138, 238, 538: drain area

140, 240, 540: pixel electrodes

150, 250, 350, 450, 550, 650: polysilicon thin film transistor

152: storage capacitor

230, 330, 530, 630: semiconductor patterns

234, 334A, 334B, 434A, 434B, 534, 634A, 634B: doped regions

252, 552: capacitance electrodes

560: shared electrode

L, L1, L2: Length

Td, Ts: contact window

D, D1, D2, D3: Width

Detailed ways

FIG. 2 is a pixel structure of an embodiment of the present invention. Referring to FIG. 2 , the pixel structure 200 is electrically connected to a scan line 210 and a data line 220 , wherein the scan line 210 and the data line 220 are arranged alternately. The pixel structure 200, the scan lines 210 and the data lines 220 are, for example, disposed on a substrate (not shown). The pixel structure 200 includes a semiconductor pattern 230 and a pixel electrode 240 . The semiconductor pattern 230 includes at least two channel regions 232A, 232B, at least one doped region 234 , and a source region 236 and a drain region 238 . The channel regions 232A and 232B are located under the scan line 210 , wherein the channel region 232A and the channel region 232B have different width-to-length ratios. The doped region 234 is connected between the channel region 232A and the channel region 232B. The pixel electrode 240 is electrically connected to the drain region 238 , wherein the source region 236 is connected between the channel region 232A and the data line 220 , and the drain region 238 is connected between the channel region 232B and the pixel electrode 240 .

Part of the scan lines 210 located under the channel region 232A and the channel region 232B can be regarded as a gate in the pixel structure 200 to control the on and off of the pixel structure 200 . In addition, the semiconductor pattern 230 is made of, for example, polysilicon material, that is to say, the semiconductor pattern 230 is a polysilicon pattern. Therefore, a part of the scan line 210 below the channel region 232A and the channel region 232B, the source region 236 and the drain region 238 together form a polysilicon thin film transistor 250 . When the polysilicon thin film transistor 250 is turned off, the grain interface of the polysilicon pattern in the channel regions 232A, 232B may cause leakage current, which affects the quality of the pixel structure 200 . In order to solve the problem of leakage current that may be caused when the polysilicon thin film transistor 250 is turned off, the concept of multi-channel design is proposed. However, it is known from the prior art that setting the branches extended from the scan line 210 for the multi-channel design will affect the display aperture ratio of the pixel structure 200 . Therefore, the present invention proposes to utilize the bent structure of the semiconductor pattern 230 to achieve a multi-channel design.

The semiconductor pattern 230 of this embodiment has, for example, a multi-fold structure, and overlaps with the scan lines 210 in multiple regions to form multiple channels. The semiconductor pattern 230 is a transparent pattern, so the display aperture ratio of the pixel structure 200 will not be affected by the multi-channel design of this embodiment. That is to say, the pixel structure 200 of this embodiment is less prone to leakage current, and can maintain a good display aperture ratio.

The semiconductor pattern 230 has, for example, a U-shaped doped region 234 , and the semiconductor pattern 230 connecting two ends of the U-shaped doped region 234 intersects the scan line 210 to form a channel region 232A and a channel region 232B. Through such a design, the polysilicon thin film transistor 250 has a plurality of channel regions 232A and 232B, so as to improve the electrical characteristics of the polysilicon thin film transistor 250 .

In detail, when the polysilicon thin film transistor 250 is turned on, the transmission direction of the current in the channel regions 232A and 232B is, for example, perpendicular to the extending direction of the scan line 210 . Therefore, the widths D1 and D2 of the scan lines 210 will affect the lengths L1 and L2 of the channel regions 232A and 232B. In general, the longer the lengths L1 and L2 of the channel regions 232A and 232B are, the longer the leakage current of the polysilicon thin film transistor 250 will be reduced. Therefore, in order to increase the length L2 of the channel area 232B, the width D2 of the scan line 210 in the channel area 232B is, for example, greater than the width D1 of the scan line 210 in other areas. Certainly, in other embodiments, in order to increase the length L1 of the channel area 232A, the width of the scan line 210 in the channel area 202A may also be widened.

The semiconductor pattern 230 further includes a capacitor electrode 252 electrically connected to the drain region 238 and the pixel electrode 240 , and the capacitor electrode 252 is located under the pixel electrode 240 . Actually, in this embodiment, the doped region 234 , the source region 236 , the drain region 238 and the capacitor electrode 252 are made of doped polysilicon material. In other embodiments, the pixel structure 200 may further include a shared electrode (not shown), disposed between the capacitor electrode 252 and the pixel electrode 240 . In addition, the drain region 238 is electrically connected to the pixel electrode 240 through the contact window Td, and the source region 236 is electrically connected to the data line 220 through the contact window Ts. In this embodiment, the contact window Td and the contact window Ts are located on the same side of the scan line 210 , and the semiconductor pattern 230 is roughly bent into a U shape to intersect the scan line 210 in the channel region 232A and the channel region 232B.

Certainly, the contact window Td and the contact window Ts may also be located on opposite sides of the scan line 210 . FIG. 3 illustrates a pixel structure of another embodiment of the present invention. Referring to FIG. 3 , the design of the pixel structure 300 is similar to that of the pixel structure 200 , wherein the contact window Td and the contact window Ts of the pixel structure 300 are located on opposite sides of the scan line 210 . In addition, the semiconductor pattern 330 of the pixel structure 300 has three channel regions 332A, 332B, 332C and two U-shaped doped regions 334A, 334B. At this time, part of the scan lines 210 below the channel regions 332A, 332B, 332C, the source region 236 and the drain region 238 jointly form a polysilicon thin film transistor 350 .

In this embodiment, the intersections of the scan lines 210 and the semiconductor patterns 330 have different widths D1 , D2 and D3 respectively. Therefore, the channel region 332A, the channel region 332B and the channel region 332C may have different width-to-length ratios. Practically, the widths D1 , D2 , D3 of the scan line 210 corresponding to the channel regions 332A, 332B, 332C may be greater than the widths of the scan line 210 in other regions, so that the polysilicon thin film transistor 350 has better electrical properties. In addition, the semiconductor pattern 330 is made of, for example, polysilicon material, and the polysilicon material has the characteristic of light transmission. Therefore, the structure of the meandering semiconductor pattern 330 in this embodiment can achieve the design of multiple channels, and at the same time make the pixel structure 300 have a good display aperture ratio.

FIG. 4 shows a pixel structure according to yet another embodiment of the present invention. 4, the pixel structure 400 is similar to the pixel structure 200 in FIG. The intersection of the semiconductor pattern 230 and the branch 412 constitutes the channel region 432 , and the doped regions 434A and 434B are respectively located between the channel region 232A and the channel region 432 , and between the channel region 232B and the channel region 432 . In practice, the semiconductor pattern 230 of this embodiment is the same as the semiconductor pattern 230 in FIG. 2 , and the pixel structure 400 has three channel regions 232A, 232B and 432 due to the design of the branch 412 . In addition, the shapes of the doped regions 434A and 434B are also changed from U-type to two L-types.

The pixel structure 400 utilizes the same semiconductor pattern 230 as the pixel structure 200 to form three channel regions 232A, 232B and 432, and the part of the scanning line 410, the source region 236 and the drain region 238 below the channel regions 232A, 232B and 432 Together they form a polysilicon thin film transistor 450 . Due to the multi-channel design, the polysilicon thin film transistor 450 is not prone to leakage current in the off state.

In addition, the branch 412 is a rectangular pattern. Compared with the L-shaped branch 112 in the prior art, the design of this embodiment helps to maintain a good display aperture ratio of the pixel structure 400 . The branch 412 and the capacitive electrode 252 are respectively located on two sides of the scan line 410 , so the location and area of the capacitive electrode 252 will not be affected by the branch 142 . That is to say, according to different design requirements, the capacitive electrode 252 can be disposed at any position in the area surrounded by the scan line 410 and the data line 220 . In addition, the extension direction of the branch 412 is perpendicular to the extension direction of the scan line 410 , and the length of the channel region 432 below the branch 412 is the same as the width D of the branch 412 . Therefore, the variation of the line width of the scan line 410 and the branch 412 can make the channel regions 232A, 232B and 432 have different length-to-width ratios. In this embodiment, the pixel structure 400 has more than two channel regions 232A, 232B and 432 by using the same design as the semiconductor pattern 230 to improve the quality of the pixel structure.

5A and 5B are two pixel structures according to another embodiment of the present invention. Referring to FIG. 5 , the pixel structure 500 includes a scan line 510 , a data line 520 , a semiconductor pattern 530 and a pixel electrode 540 . The scan lines 510 and the data lines 520 are arranged alternately and the scan lines 510 have a branch 512 , and the branch 512 is located below the data lines 520 . The semiconductor pattern 530 includes at least two channel regions 532A, 532B, at least one doped region 534 , and a source region 536 and a drain region 538 .

The channel regions 532A, 532B are located below the scan line 510 , wherein the channel regions 532A, 532B have different width-to-length ratios. The doped region 534 is connected between the channel regions 532A and 532B. The pixel electrode 540 is electrically connected to the drain region 538 , and the source region 536 is connected between the channel region 532A and the data line 520 . In addition, the drain region 538 is connected between the channel region 532B and the pixel electrode 540 . Furthermore, the doped region 534 of this embodiment has an L-shaped shape, wherein the doped region 534 is connected between the channel region 532A and the channel region 532B. The channel region 532A and a part of the scan line 510 below the channel region 532B, the source region 536 and the drain region 538 together form a polysilicon thin film transistor 550 .

In this embodiment, the semiconductor pattern 530 extends from the first side of the data line 520 to the second side of the data line 520 . The source region 536 of the semiconductor pattern 530 is electrically connected to the data line 520 through the contact window Ts, and the drain region 538 is electrically connected to the pixel electrode 540 through the contact window Td. In the pixel structure 500 , the contact window Ts and the contact window Td are located on opposite sides of the scan line 510 . Therefore, the bent structure of the semiconductor pattern 530 in this embodiment crosses both sides of the data line 520 , the scan line 510 and the branch 512 to overlap the scan line 510 and the branch 512 in multiple regions. Therefore, the pixel structure 500 has a plurality of channel regions 532A and 532B to help reduce the leakage current of the polysilicon thin film transistor 550 in the off state. In short, the pixel structure 500 is of good quality. In addition, the branch 512 of the scan line 510 is located below the data line 520 , which can further prevent the display aperture ratio of the pixel structure 500 from being affected.

The extension direction of the branch 512 is perpendicular to the extension direction of the scan line 510 , and the length L2 of the channel region 532B under the branch 512 is the same as the width D1 of the branch 512 . Therefore, in this embodiment, the lengths L2 and L1 of the channel regions 532A and 532B are related to the width of the scan line 510 and the widths D1 and D2 of the branches 512 respectively. If the widths D1 and D2 of the scan line 510 and the branches 512 are wider, the leakage current of the polysilicon thin film transistor 550 can be effectively reduced.

In addition, in order to stabilize the display voltage when the pixel structure 500 is displaying, the semiconductor pattern 530 may further include a capacitor electrode 552 located under the pixel electrode 540 , which is electrically connected to the drain region 538 and the pixel electrode 540 . Furthermore, referring to FIG. 5B , the pixel structure 500 may also be configured with a shared electrode 560 between the pixel electrode 540 and the capacitor electrode 552 . Since the branch 512 of the scan line 510 is located below the data line 520, the positions of the shared electrode 560 and the capacitive electrode 552 will not be affected by the configuration of the branch 512, which further makes the design of the shared electrode 560 and the capacitive electrode 552 more flexible.

FIG. 6 shows a pixel structure according to yet another embodiment of the present invention. Please refer to FIG. 6 , the pixel structure 600 is similar to the pixel structure 500 , the difference lies in the shape of the semiconductor pattern 630 and the semiconductor pattern 530 are different. The semiconductor pattern 630 of the pixel structure 600 includes three-channel regions 632A, 632B, 632C and two-doped regions 634A, 634B. In addition, the doped regions 634A, 634B are connected between the channel regions 632A, 632B and 632C. The source region 538 is connected between the channel region 632A and the data line 520 , and the drain region 638 is connected between the channel region 632C and the pixel electrode 540 . In addition, the capacitive electrode 552 and the branch 512 are respectively located on two sides of the scan line 510 .

In this embodiment, the extension direction of the branch 512 of the scan line 510 is perpendicular to the extension direction of the scan line 510 , and the length L of the channel region 632B under the branch 512 is the same as the width D of the branch 512 . Therefore, when the width D2 of the scan line 510 and its branches 51 is wider, the channel regions 632A, 632B, and 632C can have longer channel lengths, so as to improve the electrical characteristics of the polysilicon thin film transistor 650 .

The branch 512 is located below the data line 520 , so in the design of the pixel structure 600 , only the main circuit part of the scan line 510 and the data line 520 is a light-shielding film layer. Therefore, the pixel structure 600 has a high display aperture ratio. In addition, the semiconductor pattern 630 extends from the first side to the second side of the data line 520 to intersect the scan line 510 and its branches 512 in a plurality of regions, that is, the channel regions 632A, 632B and 632C. The three channel regions 632A, 632B and 632C of the semiconductor pattern 630 are connected by L-shaped doped regions 634A and 634B. The source region 536 , the drain region 538 and a part of the scan line 510 below the channel regions 632A, 632B and 632C together form a polysilicon thin film transistor 650 . Under such a design, the polysilicon thin film transistor 650 has multiple channels, so the phenomenon of leakage current is less likely to occur in the off state, which helps to make the pixel structure 600 have good quality.

To sum up, the present invention uses different semiconductor pattern designs to have multiple channel regions in the pixel structure, and at the same time, the branch of the scan line is arranged under the data line. Therefore, the display aperture ratio of the pixel structure is not limited by the branches of the scan lines. That is, the pixel structure of the present invention has a high display aperture ratio. In addition, in the pixel structure of the present invention, the semiconductor pattern and the scanning line overlap in multiple regions to form multiple channel regions, which helps to reduce the leakage current of the polysilicon thin film transistor in the off state in the pixel structure. On the whole, the pixel structure of the present invention has a high display aperture ratio and also has good quality.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (17)

1. A pixel structure configured on a substrate and electrically connected to a scan line and a data line, characterized in that the pixel structure comprises: A semiconductor pattern, the semiconductor pattern includes: At least two channel regions are located below the scan line, wherein the channel regions have different width-to-length ratios; at least one doped region connected between the channel regions; a source region and a drain region; and a pixel electrode electrically connected to the drain region, wherein the source region is connected between one of the channel regions and the data line, and the drain region is connected between the other channel region and the pixel electrode; Wherein, the scanning line has different widths above different channel regions, and a length of each channel region is equal to a width of the scanning line. 2. The pixel structure according to claim 1, wherein the scan line has a branch, and the branch is perpendicular to the scan line. 3 . The pixel structure according to claim 2 , wherein at least one channel region is located below the branch, and the length of the channel region below the branch is the same as the width of the branch. 4 . 4. The pixel structure according to claim 1, wherein the semiconductor pattern comprises a polysilicon pattern. 5. The pixel structure according to claim 4, wherein the semiconductor pattern further comprises a capacitor electrode electrically connected to the drain region and the pixel electrode, and the capacitor electrode is located below the pixel electrode. 6. The pixel structure according to claim 5, further comprising a shared electrode disposed between the capacitor electrode and the pixel electrode. 7. The pixel structure according to claim 1, wherein the shape of the doped region includes L-shape or U-shape. 8. The pixel structure according to claim 1, wherein a part of the scan line below the channel region, the source region and the drain region form a polysilicon thin film transistor. 9. A pixel structure, characterized in that it comprises: a scan line with a branch; a data line, arranged alternately with the scan line, the branch is located below the data line; A semiconductor pattern, the semiconductor pattern includes: At least two channel areas are located below the scan line; at least one doped region connected between the channel regions; a source region and a drain region; and A pixel electrode is electrically connected with the drain region, the source region is connected between one channel region and the data line, and the drain region is connected between the other channel region and the pixel electrode. 10 . The pixel structure according to claim 9 , wherein at least one channel region is located below the branch, and the length of the channel region below the branch is the same as the width of the branch. 11 . 11. The pixel structure according to claim 9, wherein the semiconductor pattern comprises a polysilicon pattern. 12 . The pixel structure according to claim 11 , wherein the semiconductor pattern further comprises a capacitor electrode electrically connected to the drain region and the pixel electrode, and the capacitor electrode is located below the pixel electrode. 13 . 13. The pixel structure according to claim 12, further comprising a common electrode disposed between the capacitor electrode and the pixel electrode. 14. The pixel structure according to claim 13, wherein the capacitive electrode and the branch are respectively located on two sides of the scan line. 15. The pixel structure according to claim 9, wherein the shape of the doped region comprises an L shape. 16. The pixel structure according to claim 9, wherein the semiconductor pattern extends from a first side of the data line to a second side of the data line. 17. The pixel structure according to claim 9, wherein a part of the scan line below the channel region, the source region and the drain region form a polysilicon thin film transistor.

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