CN101192379A - Active element array substrate with electrostatic discharge protection capability - Google Patents

Abstract

The present invention discloses an active component array substrate with electrostatic discharge protection capability, including a plurality of pixel units, a plurality of scan lines, a plurality of data lines, a plurality of electrostatic protection elements, a guard ring, and an electrostatic bias generating unit. Each pixel unit is electrically connected to the corresponding scan line and data line, and each electrostatic protection element has a first connection end, a second connection end, and a third connection end, wherein the first connection end is electrically connected to one of the corresponding scan line and data line, and the second connection end is electrically connected to the guard ring, and the third connection end is electrically connected to the electrostatic bias generating unit. When electrostatic discharge occurs, the electrostatic bias generating unit senses static electricity and provides a voltage divider to these electrostatic protection elements to turn on the electrostatic protection elements, so that the electrostatic current can be quickly conducted to the lowest potential of the substrate through the guard ring, thereby preventing the pixel units inside the substrate from being damaged by electrostatic discharge.

Description

Active element array substrate with electrostatic discharge protection capability

technical field

The present invention relates to an active element array substrate, and in particular to an active element array substrate with an electrostatic discharge (Electrostatic Discharge, ESD) protection circuit.

Background technique

With the advancement of modern video technology, liquid crystal display devices have been widely used in display screens of consumer electronic products such as mobile phones, notebook computers, personal computers and personal digital assistants. Generally speaking, a liquid crystal display device includes an active element array substrate, a color filter substrate, and a liquid crystal layer, wherein the active element array substrate is assembled opposite to the color filter substrate, and the liquid crystal layer is located between the active element array substrate and the color filter substrate. between. By adjusting the direction of the liquid crystal molecules in the liquid crystal layer through each active element in the active element array substrate, the intensity of the light beam can be adjusted to display images.

However, in the process of manufacturing the liquid crystal display device, many static charges may be accumulated by the manufacturing equipment, operators and the active element array substrate itself. Therefore, when the active element array substrate is in contact with manufacturing equipment, operators or other objects during the manufacturing process, it is very likely to cause electrostatic discharge. Since the circuits and components on the active device array substrate are very fine, as long as a slight electrostatic discharge occurs, the entire liquid crystal display device will easily be scrapped. In order to solve the problem of damage to the liquid crystal display device caused by electrostatic discharge, an electrostatic discharge protection circuit is generally designed on the active element array substrate.

FIG. 1 is a schematic diagram of a conventional active device array substrate. 1, the existing active device array substrate 100 includes a plurality of pixel units 110, a plurality of scanning lines 120, a plurality of data lines 130, a plurality of pads (pad) 140, a plurality of back-connected diodes (back- to-back diode) 150 and a protection ring (shortring) 160. Each pixel unit 110 includes an active device 112 and a pixel electrode 114 , and these pixel units 110 arranged in an array are electrically connected to corresponding scan lines 120 and data lines 130 respectively. One end of each scan line 120 or data line 130 is electrically connected to the corresponding pad 140 , and these pads 140 are electrically connected to the guard ring 160 via the corresponding back-connection diode 150 .

The turn-on voltage (turn-on voltage) of this back connection diode 150 is approximately the forward-biased voltage (forward-biased voltage) of a diode plus the reverse bias voltage (reveries-biased voltage) of a diode, so when electrostatic discharge When an event occurs on the active device array substrate 100, usually the electrostatic discharge voltage will be greater than the turn-on voltage of the back-connection diode 150, so that the back-connection diode 150 as an ESD protection element (ESD protection element) is turned on. In this way, the electrostatic discharge charges can pass through the back connection diode 150 and quickly conduct to the lowest potential part on the active device array substrate 100 through the guard ring 160, and neutralize these electrostatic discharge charges, so as to avoid the pixel unit inside the panel 110 suffers damage from electrostatic discharge. On the other hand, under the test condition of lighting the active device array substrate 100, since the operating voltage of the active device array substrate 100 will not exceed the turn-on voltage of the back-connected diode 150, the gap between the pad 140 and the guard ring 160 is visible. It is an open state, that is, the operation signals between the scan line 120 and the data line 130 will not affect each other, so the pixel unit 110 can display relative color potentials, and the active device array substrate 100 works normally.

In order to prevent the back-connected diode 150 from generating too much leakage current, thereby affecting the operation signal between the scan line 120 and the data line 130, it is necessary to make the turn-on voltage of the back-connected diode 150 as large as possible to reduce the impact on active components. influence on the normal operation of the array substrate 100 . However, if it is designed to increase the turn-on voltage of the back-connection diode 150, it also means that when the active device array substrate 100 is subjected to an external or internal electrostatic discharge event, the back-connection diode 150 as an electrostatic discharge protection element has not yet been turned on for conduction. Electrostatic discharge charges, these electrostatic discharge charges have already caused damage to the pixel unit 110 . So how to design the turn-on voltage of the back-connected diode 150 is a matter of knowledge.

After the process of the active device array substrate 100 is completed, sometimes in order to save power, the protective ring 160 between each pad 140 and the pixel unit 110 is cut off for subsequent product assembly. However, during the subsequent assembly process, the active device array substrate 100 will still be damaged by external or internal electrostatic discharge, so it is not appropriate to cut off the protection ring 160 before the active device array substrate 100 is assembled.

FIG. 2 is a schematic diagram of another conventional active device array substrate. Please refer to FIG. 2, the existing active device array substrate 200 includes a plurality of pixel units 210, a plurality of scanning lines 220, a plurality of data lines 230, a plurality of pads 240, and a plurality of bi-forward diodes. 250 , a first guard ring 260 , a second guard ring 270 and a power control circuit (power control circuit) 280 . The pixel units 210 arranged in an array are electrically connected to corresponding scan lines 220 and data lines 230 , and one end of each scan line 220 or data line 230 is electrically connected to a corresponding pad 240 . In addition, each bidirectional forward diode 250 includes two diodes 250a, 250b, and these pads 240 are electrically connected to the first guard ring 260 via the corresponding diode 250a, and electrically connected to the first guard ring 260 via the corresponding diode 250b. The second guard ring 270 . In addition, the power control circuit 280 is electrically connected to the first guard ring 260 and the second guard ring 270 .

When the electrostatic discharge event occurs, the three voltage levels of the power supply 290 are all 0V. When the electrostatic discharge charges injected from the outside or accumulated inside can be conducted to the first guard ring 260 through the diode 250a or 250b, and then quickly conducted to the active element array substrate 200 through the power control circuit 280 and the second guard ring 270 The lowest potential position, and neutralize these electrostatic discharge charges, so as to avoid the pixel unit 210 inside the active device array substrate 200 from being damaged by electrostatic discharge. On the other hand, under the test condition of lighting the active device array substrate 200, that is, when the power supply 290 of the active device array substrate 200 is connected to a high voltage potential Vdd, a middle voltage potential Vm and a low voltage potential Vss to operate , wherein the power control circuit 280 is also connected to these three voltage potentials, so that the first guard ring 260 is kept at the high voltage potential Vdd, and the second guard ring 270 is kept at the low voltage potential Vss. Since the potentials of the input voltage signals from the active device array substrate 200 are between the high voltage potential Vdd and the low voltage potential Vss, each diode 250a and 250b is in a state of reverse bias, so that each pad 240 The connection between the first and second guard rings 260, 270 can be regarded as an open state, that is, the operation signals between the scan line 220 and the data line 230 will not affect each other, so that the pixel unit 210 can display the relative Color potential, the active element array substrate 200 works normally.

In this prior art, the first and second guard rings 260, 270 will also be cut off during the subsequent assembly process, so the active element array substrate 200 will still be damaged by external or internal electrostatic discharge, so It is inappropriate to cut off the first and second guard rings 260 and 270 before the active device array substrate 200 is assembled.

Contents of the invention

In view of this, the object of the present invention is to provide an active device array substrate with electrostatic discharge protection capability, which has a better electrostatic discharge protection effect than traditional active device array substrates.

In order to achieve the above or other purposes, the present invention proposes an active element array substrate with electrostatic discharge protection capability, which includes a pixel unit, a scan line, a data line, and an electrostatic discharge protection element (ESD protection element), protection ring (short ring) and electrostatic bias voltage generating unit (ESD biased generator). Each pixel unit is electrically connected to the corresponding scanning line and data line, and each electrostatic discharge protection element has a first connected terminal (first connected terminal), a second connected terminal and a third connected terminal, or a selection There is a fourth connection end. Wherein the first connection end is electrically connected to one of the corresponding scanning lines or data lines, the second connection end is electrically connected to the guard ring, and the third or fourth connection end is electrically connected to the electrostatic bias. pressure generating unit. When an electrostatic discharge event (ESDevent) occurs, the electrostatic bias generating unit will sense the electrostatic discharge event and provide a voltage level to turn on these electrostatic discharge protection components, so that the accumulation inside the panel or the external injection Electrostatic charges (ESD charges) can be quickly conducted to the lowest potential of the panel through the guidance of these electrostatic discharge protection components and protective rings, and neutralize these static electricity, so as to avoid the pixel units inside the panel from being damaged by electrostatic discharge.

In an embodiment of the present invention, the above-mentioned electrostatic discharge protection element is an element having three connection terminals, and the electrostatic bias generating unit may include a voltage division control element (level controller), and the voltage division control element has a node end, And the node end is connected with the third connection end of each ESD protection element.

In an embodiment of the present invention, the electrostatic discharge protection element is an element with four connection terminals, and the electrostatic bias generating unit may include a level controller and an inverter. The voltage division control element has a node end, and the node end is electrically connected with the third connection end of each ESD protection element and the input end of the inverter, and the output end of the inverter is connected with each ESD protection element. The fourth connection end of the element is electrically connected.

In an embodiment of the present invention, the above-mentioned voltage division control element may include at least one diode connected in series in the forward direction and a resistor connected in series with the diode.

In an embodiment of the present invention, the above-mentioned voltage division control element may include at least one transistor and a resistor electrically connected to it, and the source of the transistor is electrically connected to the drain of an adjacent transistor, and the gate of the transistor It is electrically connected to one of the source and the drain.

In an embodiment of the present invention, the above-mentioned voltage division control element may include at least one resistor connected in series.

In an embodiment of the present invention, the above-mentioned electrostatic protection element may include an N-type transistor. In addition, the electrostatic protection component may further include two resistors, and the two resistors are respectively electrically connected between the first connection end and the third connection end and between the second connection end and the third connection end. In addition, the electrostatic protection element may further include two capacitors, and the two capacitors are respectively electrically connected between the first connection end and the third connection end and between the second connection end and the third connection end.

In an embodiment of the present invention, the above-mentioned electrostatic protection element may include a P-type transistor, and the electrostatic bias generating unit further includes an inverter, wherein the inverter is electrically connected to the node end and each electrostatic protection device Between the third connection ends of the components. In addition, the electrostatic protection component may further include two resistors, and the two resistors are respectively electrically connected between the first connection end and the third connection end and between the second connection end and the third connection end. In addition, the electrostatic protection element may further include two capacitors, and the two capacitors are respectively electrically connected between the first connection end and the third connection end and between the second connection end and the third connection end.

In summary, in the active device array substrate of the present invention, when an electrostatic discharge event (ESD event) occurs, the electrostatic bias generating unit will sense the electrostatic discharge event and provide a voltage level to turn on these electrostatic discharge events. Discharge protection components, so that the electrostatic charges (ESD charges) accumulated inside the panel or injected from the outside can be quickly conducted to the lowest potential of the active component array substrate and neutralize these static charges through the guidance of these electrostatic discharge protection components and protective rings. In order to prevent the pixel units inside the active device array substrate from being damaged by electrostatic discharge.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are exemplified below and described in detail with accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a conventional active element array substrate.

FIG. 2 is a schematic diagram of another conventional active device array substrate.

FIG. 3 is a schematic diagram of an active device array substrate according to an embodiment of the invention.

FIG. 4 is a schematic diagram of an active device array substrate according to another embodiment of the present invention.

5A to 5C are schematic diagrams of an electrostatic bias generating unit.

6A to 6C are schematic diagrams of the connection between one of the pads on the active device array substrate and the electrostatic protection device.

FIG. 7 is a schematic diagram of the connection between two pads on the active device array substrate and the electrostatic protection device.

8A-8D are schematic diagrams of different types of electrostatic protection components of the present invention.

9A to 9D are schematic diagrams of different types of voltage division control elements of the present invention, respectively.

FIG. 10 is a schematic diagram of a partial equivalent circuit of the active device array substrate of FIG. 4 .

Detailed ways

FIG. 3 is a schematic diagram of an active device array substrate according to an embodiment of the invention. Please refer to FIG. 3, the active device array substrate 300 of the present invention includes a plurality of pixel units 310, a plurality of scanning lines 320, a plurality of data lines 330, a plurality of electrostatic protection components 340, a guard ring 350 and an electrostatic bias generating unit 360. The pixel units 310 are arranged in an array, and are electrically connected to corresponding scan lines 320 and data lines 330 . Each ESD protection element 340 has a first connection end 342, a second connection end 344 and a third connection end 346, wherein the first connection end 342 is electrically connected to the corresponding scanning line 320 and data line 330. One, and the second connection end 344 is electrically connected to the protection ring 350 , and the third connection end 346 is electrically connected to the electrostatic bias generating unit 360 . In detail, the third connection end 346 of each ESD protection component 340 is electrically connected to a wire 360 a, and the wire 360 a is electrically connected to the electrostatic bias generating unit 360 .

In addition, the active device array substrate 300 may further include a plurality of pads 370 , and one end of each scan line 320 or data line 330 is electrically connected to the corresponding pad 370 . In this way, any two pads 370 can be electrically connected together through the two ESD protection components 340 and the guard ring 350, and when the ESD protection component 340 is turned on, the charge on any pad 370 can be It is quickly conducted to the guard ring 350 or other pads 370 to keep the potential balance. In addition, each pad 370 can be electrically connected to the electrostatic bias generating unit 360 through an electrostatic protection element (not shown), for example.

According to another embodiment of the present invention, the electrostatic protection element on the active element array substrate may also be an element with four connection terminals, please refer to FIG. 4, the structure of FIG. 4 is substantially similar to that of FIG. The protection element 440 has a first connection end 442 , a second connection end 444 , a third connection end 446 and a fourth connection end 448 . The ESD protection element 440 is a transmission gate transistor composed of an N-type transistor and a P-type transistor.

FIG. 5A is a schematic diagram of an electrostatic bias generating unit that can be used in FIG. 3 . Please refer to FIG. 5A, the electrostatic bias generating unit 360 has a plurality of terminals, which are respectively connected to the high voltage terminal H, the low voltage terminal L and a node (Node) X, and the electrostatic bias generating unit 360 also includes a Voltage division control element 362 . The electrostatic bias generating unit 360 is also connected to a diode 363a and a diode 363b. Each pad 370 in the active device array substrate of FIG. 3 is connected to one of the diodes 363a or 363b. When an electrostatic discharge event occurs and during normal operation, the electrostatic bias generating unit 360 can generate different voltage levels VESD and VOFF on the node X respectively. The diodes 363 a and 363 b are, for example, PIN diodes, PPN diodes, diode-connected N-type thin film transistors or diode-connected P-type thin film transistors.

In another embodiment, please refer to FIG. 5B, the electrostatic bias generating unit 360 has a plurality of terminals, which are respectively connected to the high voltage terminal H, the low voltage terminal L and a node terminal (Node) Y, and the electrostatic bias voltage The generating unit 360 also includes a voltage division control element 362 and an inverter 366 . The electrostatic bias generating unit 360 is also connected to a diode 363a and a diode 363b. When an electrostatic discharge event occurs and during normal operation, the electrostatic bias generating unit 360 can generate different voltage potentials VESD' and VOFF' on the node terminal Y respectively.

If the electrostatic protection element on the active element array substrate of the present invention is an element with four connection terminals, then the electrostatic bias generating unit adopts the structure shown in FIG. 5C . Please refer to FIG. 5C, the electrostatic bias generating unit 460 has a plurality of terminals, which are respectively connected to the high voltage terminal H, the low voltage terminal L, a node terminal X and a node terminal Y, and the electrostatic bias generating unit 460 It also includes a voltage division control element 362 and an inverter 366 . The electrostatic bias generating unit 360 is also connected to a diode 363a, a diode 363b. When an electrostatic discharge event occurs and during normal operation, the electrostatic bias generating unit 460 can generate different voltage potentials VESD and VOFF on the node terminal X, and generate different voltage potentials VESD' and VOFF' on the node terminal on Y.

In addition, referring to FIGS. 6A and 6B , any pad 370 on the active device array substrate shown in FIG. 3 is connected to three elements, including a diode 363a, a diode 363b, and an ESD protection element 340a or 340b. In one embodiment, please refer to FIG. 6A , the ESD protection element 340 a is connected to the node terminal X of the electrostatic bias generating unit 360 ( FIG. 5A ). In another embodiment, please refer to FIG. 6B , the ESD protection element 340b is connected to the node terminal Y of the electrostatic bias generating unit 360 ( FIG. 5B ). And the ESD protection element 340 a or 340 b is also connected to the guard ring 350 . Here, the diodes 363a, 363b will provide a small current to the static electricity to conduct electricity to the high voltage terminal H and the low voltage terminal L, so that the electrostatic bias generating unit works, and through the potential of the node terminal X or the node terminal Y ( VESD and VESD') to enable ESD protection components to conduct most of the electrostatic current.

Similarly, if the active element array substrate is an ESD protection element using four connection points, then please refer to FIG. 6C, any pad 370 on the active element array substrate shown in FIG. 4 will be connected to three elements, where It includes a diode 363a, a diode 363b and an ESD protection element 440, which is composed of ESD protection elements 340a and 340b. Two of the connection ends of the ESD protection element 440 are connected to the node X and the node Y, and the other connection end of the ESD protection element 440 is connected to the guard ring 350 . Similarly, the diodes 363a, 363b will provide a small current to the static electricity and conduct electricity to the high voltage terminal H and the low voltage terminal L, so that the electrostatic bias voltage generation unit works, and through the potential of the node terminal X or the node terminal Y ( VESD and VESD') to enable ESD protection components to conduct most of the electrostatic current.

For a more detailed description, please refer to FIG. 7 , which uses an ESD protection device with four connection points as an example for illustration. Any two pads 370 on the active device array substrate are connected together by the guard ring 350 through the ESD protection element 440 (consisting of the ESD protection elements 340 a and 340 b ). That is, when an electrostatic discharge event occurs, through the action of the diode 363a or 363b and the electrostatic bias generating unit, a voltage will be generated on the node terminal X and the node terminal Y, thereby turning on the electrostatic discharge protection element 340a, 340b, Therefore, the ESD energy can be released through the connection of the protection ring 350 .

In addition, the electrostatic protection device of the present invention can be composed of only N-type transistors, P-type transistors, or a combination thereof. Of course, the electrostatic discharge protection device of the present invention can also be in other forms. The following will illustrate other types with illustrations. Static protection components. 8A-8D are schematic diagrams of different types of electrostatic protection components of the present invention. Please refer to FIG. 8A. In addition to the N-type transistor 340', the ESD protection element 340a1 may also include two resistors 340a, and the two resistors 340a are respectively electrically connected between the first connection terminal 342 and the third connection terminal 346. And between the second connection terminal 344 and the third connection terminal 346, that is, the two resistors 340a are respectively electrically connected between the gate of the N-type transistor 340' and the source/drain of the N-type transistor 340'.

Please refer to FIG. 8B , similar to the above, in addition to the N-type transistor 340 ′, the ESD protection element 340a2 also includes two capacitors 340b, and the two capacitors 340b are electrically connected to the first connection terminal 342 and the third connection terminal 346 respectively. between the second connection end 344 and the third connection end 346 . In addition, please refer to FIG. 8C, in addition to the P-type transistor 340", the ESD protection element 340b1 may also include two resistors 340c, and the two resistors 340c are electrically connected to the first connection terminal 342 and the third connection terminal 346 respectively. between the second connection terminal 344 and the third connection terminal 346, that is, the two resistors 340c are respectively electrically connected to the gate of the P-type transistor 340″ and the source/drain of the P-type transistor 340″ In addition, please refer to FIG. 8D, similar to the above, the ESD protection element 340b2 includes two capacitors 340d in addition to the P-type transistor 340", and the two capacitors 340d are electrically connected to the first connection terminal 342 and the second terminal respectively. Between the three connection ends 346 and between the second connection end 344 and the third connection end 346 .

In addition, the following will describe in detail the aforementioned voltage division control element. 9A to 9D are schematic diagrams of different types of voltage division control elements of the present invention, respectively. Please refer to FIG. 9A first. In this embodiment, the voltage division control element 362 may include a plurality of diodes 362a connected in series in the forward direction and a resistor 362b connected in series with these diodes 362a, and the connection between the diode 362a and the resistor 362b may be connected to Node terminal X. When an electrostatic discharge event occurs and during normal operation, the voltage division control element 362 can generate different voltage levels VESD and VOFF on the node X respectively.

It should be noted that the spirit of the voltage division control element 362 of the present invention lies in the concept of voltage division, and the foregoing embodiments are not intended to limit the composition of the voltage division control element 362 of the present invention. Next, the detailed composition of other voltage division control elements 362 will be listed in conjunction with the figures, so as to further embody the spirit of the present invention. Please refer to FIG. 9B. In this embodiment, the voltage division control element 362 may include a plurality of N-type transistors 362c and a resistor 362d electrically connected to one of these N-type transistors 362c, and between the N-type transistors 362c and the resistor 362d is connected in series to branch out the node end X. In addition, the source of each N-type transistor 362c is electrically connected to the drain of the adjacent N-type transistor 362c, and the gate of each N-type transistor 362c is electrically connected to the source.

Please refer to FIG. 9C, similar to the above, the voltage division control element 362 may include a plurality of P-type transistors 362e and a resistor 362f electrically connected to one of these P-type transistors 362e, and divide the P-type transistor 362e in series with the resistor 362f Exit node X. In addition, the source of each P-type transistor 362e is electrically connected to the drain of an adjacent P-type transistor 362e, and the gate of each P-type transistor 362e is electrically connected to the drain. Please refer to FIG. 9D , in this embodiment, the voltage division control element 362 may also only include a plurality of resistors 362g connected in series, and a node terminal X is branched out at a place where two resistors 362g are connected in series.

The ESD protection architecture of the complete active device array substrate will be fully described below. Generally speaking, when an electrostatic discharge event occurs, there is always one place on the active device array substrate with the highest electrostatic potential and one place with the lowest electrostatic potential, and the path of electrostatic discharge always discharges from the highest potential to the lowest potential. If the active device array substrate does not have an electrostatic discharge protection structure, the instantaneous high-energy static electricity will cause damage to the pixel units inside the active device array substrate. Please refer to FIG. 10 . FIG. 10 is a schematic diagram of a partial equivalent circuit of the active device array substrate in FIG. 4 . Due to the existence of the electrostatic discharge protection structure, when the electrostatic discharge accumulates to a certain amount of energy, when an electrostatic discharge event occurs on one of the contact pads 370, some current will be released first and passed through the diode 363a to the voltage divider control element 362 to generate When the voltage is divided, a potential VESD is generated at the node X, which is greater than the threshold voltage of the N-TFT in the ESD protection device 440 . At the same time, a potential VESD' is generated at the node terminal Y via the inverter 366, which is greater than the threshold voltage of the P-TFT in the ESD protection device 440. In this way, the N-TFT and the P-TFT of the electrostatic discharge protection element 440 can be turned on, and then the static electricity can be conducted to the lowest potential of the electrostatic potential on the active element array substrate for discharge. In addition, when the active element array substrate is in normal operation, that is, when the active element array substrate is operated with an external potential applied, a potential is also applied to the high voltage terminal H and the low voltage terminal L on the electrostatic bias generating unit, and after dividing The voltage division of the voltage control element 362 will generate a potential VOFF at the node terminal X, which is much lower than the critical voltage of the N-TFT, and at the same time generate a potential VOFF' at the node terminal Y through an inverter 366, which is lower than the P-TFT critical voltage. In this way, the N-TFT and P-TFT in the ESD protection element 440 can be turned off. At this time, the path between the two pads 370 is disconnected, so when the active device array substrate is in normal operation, no leakage current will be generated between the two pads 370 .

In summary, the active element array substrate of the present invention has at least the following advantages:

1. When an electrostatic discharge event occurs, the electrostatic bias generating unit will sense the electrostatic discharge event and provide a voltage potential to turn on these electrostatic discharge protection components, so that the electrostatic charge accumulated inside the panel or injected from the outside can pass through Under the guidance of these electrostatic discharge protection elements and protective rings, they are quickly conducted to the lowest potential of the active element array substrate and neutralize the static electricity, so as to prevent the pixel units inside the active element array substrate from being damaged by electrostatic discharge.

2. When operating the active device array substrate, the voltage difference between the applied voltages can be adjusted to reduce the leakage current, so that the energy consumed by the leakage current can be reduced, thereby improving the quality of the active device array substrate.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The protection scope of the invention should be defined by the claims.

Claims (17)

1. An active element array substrate, comprising: Multiple scan lines and multiple data lines; a plurality of pixel units, which are respectively electrically connected to the corresponding scanning lines and the corresponding data lines; A plurality of electrostatic protection components, each of the electrostatic protection components has a first connection end, a second connection end and a third connection end, and the first connection end is electrically connected to the corresponding scanning line and the corresponding One of the data lines; a guard ring, the second connection end of each of the ESD protection components is electrically connected to the guard ring; and an electrostatic bias generating unit, which is electrically connected to the third connection end of each of the electrostatic protection components; Wherein, when the electrostatic discharge occurs, the electrostatic bias generating unit will sense static electricity and provide a partial voltage to the electrostatic protection elements to turn on the electrostatic protection elements and conduct the electrostatic current to the protection ring. 2. The active device array substrate according to claim 1, wherein the electrostatic bias generating unit comprises a voltage division control element, and the voltage division control element has a node end, and the node end is connected to each The third connection ends of the static protection components are electrically connected. 3 . The active device array substrate as claimed in claim 2 , wherein the voltage division control element comprises at least one diode connected in series in forward direction and a resistor connected in series with the diode. 4 . 4. The active device array substrate according to claim 2, wherein the voltage division control element comprises at least one transistor and a resistor electrically connected to one of the transistors, and the source of the transistor is electrically connected connected to the drain of an adjacent transistor, and the gate of the transistor is electrically connected to one of the source and the drain. 5. The active device array substrate as claimed in claim 2, wherein the voltage division control element comprises at least one resistor connected in series. 6. The active device array substrate as claimed in claim 2, wherein the electrostatic protection device comprises an N-type transistor, a P-type transistor or a combination thereof. 7. The active device array substrate according to claim 6, wherein the ESD protection component further comprises two resistors, and the two resistors are respectively electrically connected to the first connection terminal and the third connection terminal between the second connection end and the third connection end. 8. The active device array substrate according to claim 6, wherein the electrostatic protection device further comprises two capacitors, and the two capacitors are respectively electrically connected to the first connection end and the third connection end between the second connection end and the third connection end. 9. The active device array substrate according to claim 2, wherein the electrostatic protection element comprises a P-type transistor, an N-type transistor or a combination thereof, and the electrostatic bias generating unit further comprises an inverter, It is electrically connected between the node end and the third connection end of each of the electrostatic protection components. 10. The active device array substrate according to claim 9, wherein the ESD protection component further comprises two resistors, and the two resistors are respectively electrically connected to the first connection terminal and the third connection terminal between the second connection end and the third connection end. 11. The active device array substrate according to claim 9, wherein the electrostatic protection device further comprises two capacitors, and the two capacitors are electrically connected to the first connection end and the third connection end respectively between the second connection end and the third connection end. 12 . The active device array substrate as claimed in claim 9 , wherein each of the electrostatic protection components further comprises a fourth connection terminal electrically connected to the electrostatic bias generating unit. 13 . 13. The active device array substrate according to claim 12, wherein the electrostatic bias generating unit comprises a voltage division control element and an inverter, and the voltage division control element has a node terminal, the junction The point end will be electrically connected with the third connection end of each of the ESD protection components and the input end of the inverter, and the output end of the inverter will be connected with the fourth connection end of each of the ESD protection components electrical connection. 14. The active device array substrate as claimed in claim 13, wherein the voltage division control element comprises at least one diode connected in series in forward direction and a resistor connected in series with the diode. 15. The active device array substrate according to claim 13, wherein the voltage division control element comprises at least one transistor and a resistor electrically connected to the transistor, and the source of the transistor is electrically connected to the phase adjacent to the drain of the transistor, and the gate of the transistor is electrically connected to one of the source and the drain. 16. The active device array substrate as claimed in claim 13, wherein the voltage division control element comprises at least one resistor connected in series. 17. The active device array substrate as claimed in claim 12, wherein the electrostatic protection device comprises a transfer gate transistor.

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