CN100407143C - Method for checking software edition in programmable logic element - Google Patents
Method for checking software edition in programmable logic element Download PDFInfo
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- CN100407143C CN100407143C CN2005100343229A CN200510034322A CN100407143C CN 100407143 C CN100407143 C CN 100407143C CN 2005100343229 A CN2005100343229 A CN 2005100343229A CN 200510034322 A CN200510034322 A CN 200510034322A CN 100407143 C CN100407143 C CN 100407143C
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Abstract
The present invention provides a method for checking software versions in programmable logic devices (PLDs), which comprises the following steps: 1) starting up a JTAG controller and sampling the software versions in the system PLDs via the sampling function of the controller, 2) judging whether or not the software versions in the PLDs have correct matching relations between system software or other modular software versions for communication function; 3) starting up the rest part of the system if the PLD software versions are checked to be correct; otherwise, upgrading the software versions in the PLDs to correct versions via the JTAG controller. The software versions in the programmable logic devices of the present invention are checked before the system is started, so that version check and the loading process are independent from single boards or modules to be loaded, so the method reduces dependency relations between other parts in the check process, and enhances checking reliability.
Description
Technical field
The present invention relates to the measuring technology of the electronics or the communications field, particularly a kind of method that the software version of programmable logic device (PLD) (PLD:Programmable Logic Device) is tested.
Background technology
Along with function in electronics or the communication system is more and more, for realizing described function, the structure of circuit also becomes increasingly complex in electronics or the communication system, multiple-plate design is more and more general, in described design, can use the programmable logic device (PLD) of a large amount of cards shown, the part that described programmable logic device (PLD) has, the specific function of realization veneer on the different veneers of the system that then is distributed in that has as control system.
Because programmable logic device (PLD) can realize its function by programming, so when veneer in electronics or the communication system need increase new function or original function changed, just need the software of the realization function in the described programmable logic device (PLD) is carried out edition upgrading, and the version of a software of realizing function often has Matching Relationship with the functional software version of system software or other modules, it is unusual that the version that does not match may make system can not start or start the back system works, therefore be the operate as normal of assurance system, the reliability of raising system is necessary to consider before system start-up the software version of the realization function of the programmable logic device (PLD) of system is carried out verification.
Prior art is to allow after the system start-up, read the register of the software version of the realization function in the programmable logic device (PLD) by control system, whether the control system verification is desired version, will upgrade to the software of realizing function if not control section then.Not starting if control system is normal, might be that the version of the software of certain realization function of system does not match or other physical causes so, and this needs the position fixing process of a complexity.
But but there is following problem in the prior art scheme:
At first, to read the version register of the software of realizing function by control system, just must guarantee that operate as normal, the control channel circuit of control system are normal, in addition, exectorial management channels and software are also all wanted operate as normal, as seen, the module that this scheme involves is more, a certain partial fault all can influence the version verification of the software of realizing function, particularly control system is too relied on, so its verification reliability is not high relatively;
Secondly, if having with the startup software of CPU, the version of the software of the interior institute of programmable logic device (PLD) realization of loading function conflicts, the CPU of control system can not be started, the verification of the version of the software of all realization functions all can not be carried out like this, can not carry out thereby cause starting relevant verification with CPU;
At last,, then can not read to realize the version register of the software of function, so also just can't carry out the version verification if certain programmable logic device (PLD) does not have the CPU control interface in the system.
Summary of the invention
The invention provides the method for software version in a kind of verification programmable logic device (PLD), problem lower and that software version can not verification in some cases with the reliability that solves the PLD software version verification of system in the prior art.
For solving the problems of the technologies described above, the method for software version comprises the steps: in a kind of verification programmable logic device (PLD) provided by the invention
1) starts jtag controller and utilize its sampling function that software version among each PLD of system is sampled;
2) judge that whether software version among each PLD has correct Matching Relationship with the software version in order to realize communication function of system software or other modules, comprising:
Utilize jtag controller that the desired software version information content of software version among the PLD and system is compared;
3) if the software version verification of PLD is correct, other parts of start-up system then; Otherwise, correct version is arrived in software release upgrade among the PLD by jtag controller.
The sampling of described step 1) is to finish by reading among the PLD content of registers of software version.
Described step 2) jtag controller that utilizes in the detailed process that the desired software version information content of software version among the PLD and system compares is: be to utilize jtag controller that the desired software version information content of content of registers and system of software version among the PLD is compared.
Described jtag controller has jtag bus, and described PLD has jtag interface, and described jtag bus is connected with described jtag interface.
At least one I/O port of described PLD is corresponding with the version number of software version register among the described PLD, and described I/O port is defined as exporting the I/O port when PLD programmes, and described jtag controller is sampled to the version I/O of described PLD.
Described jtag controller also comprises the IC with jtag interface, by described jtag bus described IC is connected to PLD, and the control of the jtag interface by this IC IC simulates the read operation sequential to the software version register of PLD.
The invention has the advantages that, method provided by the present invention is before system start-up, realize the version verification by boundary scan, its can by jtag controller system by the verification single board starting before the software version of programmable logic device (PLD) is carried out verification, and under the inconsistent situation of version to software release upgrade, also can make simultaneously the version verification independent mutually with veneer that is loaded or module with loading procedure, reduced the dependence of checking procedure, improved the verification reliability other parts.In addition, whether the software version that can also carry out being loaded in the programmable logic device (PLD) has the verification that conflicts with the startup software of CPU, simultaneously, also can realize software version verification and upgrading for the system that does not have CPU.
Description of drawings
Fig. 1 is a jtag boundary scanning work schematic diagram;
Fig. 2 is the annexation figure of JTAG and PLD in the system;
Fig. 3 realizes programmable logic device (PLD) software version method of calibration process flow diagram for the present invention utilizes the jtag boundary scanning technique;
Fig. 4 is the specific I/O realization version verification synoptic diagram of jtag controller by jtag bus direct sample PLD;
Fig. 5 realizes version verification synoptic diagram for jtag controller by the version that the IC with jtag interface reads PLD.
Embodiment
Boundary-scan test technology is based on as JTAG (JTAG) interface that solves PCB physical access problem and grows up, and such problem is that new encapsulation technology causes circuit board to assemble crowded day by day causing.1988, some companies of North America united JTAG (JTAG:Joint Test Action Group), the initial boundary scan that standardized (Boundary Scan) technology set up.Nineteen ninety, IEEE (Institute of Electrical andElectronic Engineers) accepts this standard becomes standard 1149.1.Boundary scan embeds test circuit on the chip-scale level, to form comprehensive circuit board level test protocol.Utilize boundary scan industrial standard IEEE 1149.1 to test, to debug and to programme, and diagnose out hardware problem the assembling of complexity at system equipment.By visit, can eliminate or greatly reduce needs physical testing point on the circuit board to scanning pattern I/O.Except can carrying out the circuit board testing, boundary scan testing allows after the PCB paster, on circuit board the PLD of nearly all type and flash memory is programmed and scans.IEEE 1149.1 standard codes one four line serial line interface, this interface is called test access port (TAP), is used to visit complicated integrated circuit (IC), for example microprocessor, programmable logic device (PLD) etc.Built-in chip type functional mode register or software version register with jtag interface, the release status of the software of the realization function by boundary scan passage calibrating chip or make chip be in certain specific functional mode.
Boundary scan testing has two big advantages: one is the localization of fault that makes things convenient for chip, improves testing efficiency; Another is, has the built-in chip type functional mode register or the logic state register of jtag interface, the logic state by boundary scan passage calibrating chip or make chip be in certain specific functional mode.Current programmable logic device (PLD) nearly all has jtag interface and the function that meets IEEE 1149.1, therefore, can carry out verification to the software version of programmable logic device (PLD) by the jtag boundary scanning technique.
As shown in Figure 1, boundary scan technique is controlled the pin of the device of support boundary scan completely by software, be provided with or read its state, wherein, logical block (Logic) is the inner logic function module originally of programmable logic device (PLD), the corresponding boundary scan cell of each pin of programmable logic device (PLD), these inside, unit connect into chain.When the programmable logic device (PLD) operate as normal, boundary-scan function is not opened, and boundary scan cell is " transparent ", can normal running programmable logic device (PLD) internal logic function by device pin; Select test access port (TAP) the controller opens boundary-scan function of (TMS) control programmable logic device (PLD) internal proprietary when use test clock (TCK), test pattern after, then can read or be provided with the state of each pin arbitrarily by the inner boundary scan chain.Like this, the cooperation special software just can be finished the test to programmable logic device (PLD) inside or external circuit.
As shown in Figure 3, the present invention utilizes the jtag boundary scanning technique to realize that the concrete steps of software version method of calibration of programmable logic device (PLD) are as follows:
1) at first starts jtag controller;
As shown in Figure 2, in a system, the line of JTAG and PLD comprises control panel and the other types veneer that has jtag controller, each veneer all has the PLD device (for little system, has only a veneer probably), usually have only the jtag controller (being placed on the control panel) of a main usefulness, it links up the PLD of each veneer (comprising control panel itself) by jtag bus.After control panel powers on, at first start jtag controller, make the JTAG of system work, each will do the PLD software version of version verification by JTAG scanning total system, after the version verification is correct, restart other parts of system, if the version verification is incorrect, then will be by the upgrading of JTAG realization to the PLD version, successfully back other parts of start-up system of upgrading.
2) utilize the sampling function of JTAG that software version among each PLD of system is sampled;
The prerequisite of PLD version verification is that the PLD logic loads, and version identifier (register, I/O pin etc.) is arranged.Circuit sampling is the critical function that boundary scan provides, it can be sampled to the I/O pin relevant with boundary scan cell, the present invention utilizes the sampling function of JTAG to realize the version sampling of programming device, and the content of the software version register by reading programmable logic device (PLD) is finished.
The present invention utilizes sampling (SAMPLE) the instruction gating boundary scan register between test data input (TDI) and test data output (TDO) connected in series of JTAG, and this process is to the not influence of normal logic operation of chip.The sampling function of JTAG is taken a sample to the level state of its pin when the device operate as normal, and the data of these samplings can be by the output of boundary scan register serial-shift.Its principle of work is to utilize scan chain at first to preset sampling (Preload/Sample) instruction, catch the operation of data (Capture-DR) and shifted data (Shift-DR) then, the data of sampling can be preserved by data shift, so that carry out data analysis.
3) judge that whether software version among each PLD has correct Matching Relationship with the software version in order to realize communication function of system software or other modules;
In this example, judgement is to utilize jtag controller that the desired software version information content of content and system of the software version register of programmable logic device (PLD) is compared to finish, and the desired version information content stores of described system is in the register of CPU periphery.
4) if the software version verification of PLD is correct, other parts of start-up system then;
5), then correct version is arrived in software release upgrade among the PLD, successfully back other parts of start-up system of upgrading by JTAG if the software version verification of PLD is incorrect.
Realize that by JTAG the verification of PLD version has two kinds of situations, a kind of situation is not to be with jtag interface on the IC, the jtag bus of jtag controller can be directly connected on the PLD, by local bus visit PLD, is used to indicate the I/O port of version by the sampling instruction sampling of JTAG; Another kind of situation is that PLD has local bus to be connected to have on the IC of jtag interface, the read operation that simulates local bus by JTAG control IC has access to the internal register of PLD, simulate read operation sequential by the JTAG of this IC control IC to the software version register of PLD, in this case, PLD also can be in the JTAG chain.
As shown in Figure 4, for the PLD edition correcting method of above-mentioned first kind of situation, PLD reserves several I/O pin, and this I/O pin is corresponding with the version number of software version register, when PLD programmes these I/O is defined as output simultaneously.After jtag controller starts, the version I/O of the sampling instruction sampling programmable logic device (PLD) by jtag boundary scanning, the content of reading software version register, thereby acquisition software version information, compare with the correct software version information that is stored in the system requirements in the CPU peripheral registers, if the software version of programmable logic device (PLD) is incorrect, the JTAT controller is by the software release upgrade of jtag interface realization to programmable logic device (PLD).Because the sampling of JTAG instruction does not influence the normal logic function of programmable logic device (PLD), therefore in the version checking procedure, any influence can not arranged to the logic function of programmable logic device (PLD).
For second kind of situation, as shown in Figure 5, jtag controller makes the IC that connects PLD simulate the local bus that is connected with PLD by boundary scan, by the local bus of simulation the value of the software version register of PLD is read up, and, compare with the version that requires by JTAG output.This method can be saved definition version I/O, the I/O resource of having saved PLD.
Claims (6)
1. the method for software version in the verification programmable logic device (PLD) is characterized in that, comprises the steps:
1) starts jtag controller and utilize its sampling function that software version among each PLD of system is sampled;
2) judge that whether software version among each PLD has correct Matching Relationship with the software version in order to realize communication function of system software or other modules, comprising:
Utilize jtag controller that the desired software version information content of software version among the PLD and system is compared;
3) if the software version verification of PLD is correct, other parts of start-up system then; Otherwise, correct version is arrived in software release upgrade among the PLD by jtag controller.
2. method according to claim 1 is characterized in that: the sampling of described step 1) is to finish by reading among the PLD content of registers of software version.
3. method according to claim 1 is characterized in that: utilize jtag controller that the desired software version information content of software version among the PLD and system is compared detailed process to be described step 2): be to utilize jtag controller that the desired software version information content of content of registers and system of software version among the PLD is compared.
4. method according to claim 1 is characterized in that: described jtag controller has jtag bus, and described PLD has jtag interface, and described jtag bus is connected with described jtag interface.
5. method according to claim 4, it is characterized in that: at least one I/O port of described PLD is corresponding with the version number of software version register among the described PLD, described I/O port is defined as exporting the I/O port when PLD programmes, described jtag controller is sampled to the version I/O of described PLD.
6. method according to claim 4, it is characterized in that: described jtag controller also comprises the IC with jtag interface, by described jtag bus described IC is connected to PLD, and the control of the jtag interface by this IC IC simulates the read operation sequential to the software version register of PLD.
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| CN104572442A (en) * | 2014-12-10 | 2015-04-29 | 黑龙江真美广播通讯器材有限公司 | In-chip program checking system for programmable logic chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030023793A1 (en) * | 2001-07-30 | 2003-01-30 | Mantey Paul J. | Method and apparatus for in-system programming through a common connection point of programmable logic devices on multiple circuit boards of a system |
| KR20040064474A (en) * | 2003-01-13 | 2004-07-19 | 삼성전자주식회사 | Programmable Logic device upgrade apparatus and method |
| CN1168019C (en) * | 2002-08-30 | 2004-09-22 | 清华大学 | Field Programmable Gate Array Program Online Updating System and Its Implementation Method |
| CN1545036A (en) * | 2003-11-17 | 2004-11-10 | 中兴通讯股份有限公司 | FPGA logic program download device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20030023793A1 (en) * | 2001-07-30 | 2003-01-30 | Mantey Paul J. | Method and apparatus for in-system programming through a common connection point of programmable logic devices on multiple circuit boards of a system |
| CN1168019C (en) * | 2002-08-30 | 2004-09-22 | 清华大学 | Field Programmable Gate Array Program Online Updating System and Its Implementation Method |
| KR20040064474A (en) * | 2003-01-13 | 2004-07-19 | 삼성전자주식회사 | Programmable Logic device upgrade apparatus and method |
| CN1545036A (en) * | 2003-11-17 | 2004-11-10 | 中兴通讯股份有限公司 | FPGA logic program download device |
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