CN100380629C - Method for manufacturing pixel structure - Google Patents
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Abstract
Description
技术领域 technical field
本发明是有关于一种半导体组件的制造方法,且特别是有关于一种像素结构(pixel structure)的制造方法。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a pixel structure.
背景技术 Background technique
随着现代视频信息技术的进步,各式显示器已被大量地使用于手机、笔记本型计算机数字相机及个人数字助理(Personal Digital Assistant,PDA)等消费性电子产品的显示屏幕上。在这些显示器中,由于液晶显示器(LiquidCrystal Display,LCD)及有机电激发光显示器(Organic Light EmittingDiode,OLED)具有重量轻、体积小及耗电量低等优点,使得其成为市场上的主流。无论是液晶显示器或是有机电激发光显示器,其制作过程均包括以半导体工艺于基板上形成像素数组。对应调整画素数组中各个像素所显示的颜色,显示器即可产生影像。With the advancement of modern video information technology, various displays have been widely used on the display screens of consumer electronic products such as mobile phones, notebook computer digital cameras and personal digital assistants (Personal Digital Assistant, PDA). Among these displays, liquid crystal displays (Liquid Crystal Display, LCD) and organic electroluminescent displays (Organic Light Emitting Diode, OLED) have the advantages of light weight, small size and low power consumption, making them the mainstream in the market. Whether it is a liquid crystal display or an organic electroluminescent display, the manufacturing process includes forming a pixel array on a substrate by semiconductor technology. By correspondingly adjusting the colors displayed by each pixel in the pixel array, the display can generate an image.
图1A~1E为公知的一种像素结构的形成过程的剖面示意图。请参考图1A,首先利用一第一掩模(photo mask)210于一基板50上形成一源极(source)110/漏极(drain)120。请参考图1B,接着利用一第二掩模220于基板50及部分源极110/漏极120上形成一沟道层(channel)130。请参考图1C,之后于基板50上形成一第一介电层(dielectric layer)140以覆盖源极110/漏极120及沟道层130,并利用一第三掩模230于第一介电层140上形成一栅极(gate)150。请参考图1D,再来于第一介电层140与栅极150上形成一第二介电层160,并利用一第四掩模240于第一介电层140及第二介电层160中形成一接触窗开口(contact window)170以暴露出部分漏极120。请参考图1E,最后利用一第五掩模250于第二介电层160上形成一透明导电层180,其中部分透明导电层180是填入接触窗开口170,以使透明导电层180电性连接于漏极120。至此步骤即完成像素结构100的制作。1A-1E are schematic cross-sectional views of a known formation process of a pixel structure. Please refer to FIG. 1A , first a
承接上述,制造像素结构100的主要成本之一乃为掩模的制造费用,而公知技艺必须要使用到五个不同的掩模始能形成像素结构100,因此像素结构100的制造成本无法降低。特别的是,随着基板尺寸的增大,必须使用面积更大的掩模以制造像素结构100,如此更增加像素结构100的制作成本。Following the above, one of the main costs of manufacturing the
发明内容 Contents of the invention
本发明的目的是提供一种像素结构的制作方法,可以降低像素结构的制作成本。The purpose of the present invention is to provide a method for manufacturing a pixel structure, which can reduce the manufacturing cost of the pixel structure.
为达上述或是其它目的,本发明提出一种像素结构的制作方法,其步骤包括利用一第一掩模于一基板上形成一源极/漏极;利用一第二掩模于基板上分别形成一透明导电层及一沟道层,其中透明导电层覆盖部分源极/漏极,并电性连接于源极/漏极,且透明导电层的图案与沟道层的图案成互补;在基板上形成一介电层,以覆盖透明导电层与沟道层;利用一第三掩模于介电层上形成一栅极。To achieve the above or other purposes, the present invention proposes a method for manufacturing a pixel structure, the steps of which include forming a source/drain on a substrate using a first mask; forming a transparent conductive layer and a channel layer, wherein the transparent conductive layer covers part of the source/drain and is electrically connected to the source/drain, and the pattern of the transparent conductive layer is complementary to the pattern of the channel layer; A dielectric layer is formed on the substrate to cover the transparent conductive layer and the channel layer; a grid is formed on the dielectric layer by using a third mask.
在本发明的一实施例中,上述形成透明导电层及沟道层的步骤包括在基板上形成一透明导电材料层,以覆盖源极/漏极;使用第二掩模在透明导电材料层上形成一第一型图案化光刻胶层;以第一型图案化光刻胶层为掩模移除部分透明导电材料层,以形成透明导电层;移除第一型图案化光刻胶层。在基板上形成一沟道材料层;使用第二掩模在沟道材料层上形成一第二型图案化光刻胶层,其中第二型图案化光刻胶层与第一型图案化光刻胶层的型态不同;以第二型图案化光刻胶层为掩模移除部分沟道材料层,以形成沟道层;移除第二型图案化光刻胶层。In one embodiment of the present invention, the step of forming the transparent conductive layer and the channel layer includes forming a transparent conductive material layer on the substrate to cover the source/drain electrodes; forming a first-type patterned photoresist layer; using the first-type patterned photoresist layer as a mask to remove part of the transparent conductive material layer to form a transparent conductive layer; removing the first-type patterned photoresist layer . Form a channel material layer on the substrate; use a second mask to form a second-type patterned photoresist layer on the channel material layer, wherein the second-type patterned photoresist layer and the first-type patterned photoresist layer The types of the resist layer are different; using the second-type patterned photoresist layer as a mask to remove part of the channel material layer to form a channel layer; removing the second-type patterned photoresist layer.
在本发明的一实施例中,上述的第一型图案化光刻胶层的型态为正型光刻胶,且第二型图案化光刻胶层的型态为负型光刻胶。In an embodiment of the present invention, the above-mentioned first-type patterned photoresist layer is a positive-type photoresist, and the second-type patterned photoresist layer is a negative-type photoresist.
在本发明的一实施例中,上述的第一型图案化光刻胶层的型态为负型光刻胶,且第二型图案化光刻胶层的型态为正型光刻胶。In an embodiment of the present invention, the above-mentioned first-type patterned photoresist layer is a negative-type photoresist, and the second-type patterned photoresist layer is a positive-type photoresist.
在本发明的一实施例中,上述形成透明导电层及沟道层的步骤包括在基板上形成一沟道材料层,以覆盖源极/漏极;使用第二掩模在沟道材料层上形成一第二型图案化光刻胶层;以第二型图案化光刻胶层为掩模移除部分沟道材料层,以形成沟道层;移除第二型图案化光刻胶层。在基板上形成一透明导电材料层;使用第二掩模在透明导电层上形成一第一型图案化光刻胶层,其中第一型图案化光刻胶层与第二型图案化光刻胶层的型态不同;以第一型图案化光刻胶层为掩模移除部分透明导电材料层,以形成透明导电层;移除第一型图案化光刻胶层。In one embodiment of the present invention, the step of forming the transparent conductive layer and the channel layer includes forming a channel material layer on the substrate to cover the source/drain electrodes; forming a second-type patterned photoresist layer; using the second-type patterned photoresist layer as a mask to remove part of the channel material layer to form a channel layer; removing the second-type patterned photoresist layer . Form a transparent conductive material layer on the substrate; use a second mask to form a first-type patterned photoresist layer on the transparent conductive layer, wherein the first-type patterned photoresist layer and the second-type patterned photoresist layer The types of the adhesive layer are different; using the first-type patterned photoresist layer as a mask to remove part of the transparent conductive material layer to form a transparent conductive layer; removing the first-type patterned photoresist layer.
在本发明的一实施例中,上述的第一型图案化光刻胶层的型态为正型光刻胶,且第二型图案化光刻胶层的型态为负型光刻胶。In an embodiment of the present invention, the above-mentioned first-type patterned photoresist layer is a positive-type photoresist, and the second-type patterned photoresist layer is a negative-type photoresist.
在本发明的一实施例中,上述第一型图案化光刻胶层为负型光刻胶,且第二型图案化光刻胶层为正型光刻胶。In an embodiment of the present invention, the above-mentioned first-type patterned photoresist layer is a negative-type photoresist, and the second-type patterned photoresist layer is a positive-type photoresist.
在本发明的一实施例中,上述形成源极/漏极的步骤之后还包括利用第一掩模于源极/漏极上形成一欧姆接触层(ohmic contact layer)。In an embodiment of the present invention, the step of forming the source/drain further includes forming an ohmic contact layer on the source/drain by using the first mask.
在本发明的一实施例中,上述形成栅极的步骤之后,还包括使用第一掩模在介电层与栅极上形成一图案化光刻胶层;以图案化光刻胶层为掩模移除部分介电层,以形成一图案化介电层,其中图案化介电层暴露出部分透明导电层;移除图案化光刻胶层。In an embodiment of the present invention, after the above step of forming the gate, it further includes forming a patterned photoresist layer on the dielectric layer and the gate using the first mask; using the patterned photoresist layer as a mask removing part of the dielectric layer to form a patterned dielectric layer, wherein the patterned dielectric layer exposes part of the transparent conductive layer; removing the patterned photoresist layer.
在本发明的一实施例中,上述形成栅极的步骤之后,还包括在介电层与栅极上形成一光刻胶层,其中栅极与源极/漏极有部分重叠;以源极/漏极与栅极作为掩模对光刻胶层进行图案化工艺,以形成一图案化光刻胶层;以图案化光刻胶层为掩模移除部分介电层,以形成一图案化介电层,其中图案化介电层暴露出部分透明导电层;移除图案化光刻胶层。In an embodiment of the present invention, after the above step of forming the gate, it further includes forming a photoresist layer on the dielectric layer and the gate, wherein the gate and the source/drain partially overlap; /Drain and gate are used as a mask to pattern the photoresist layer to form a patterned photoresist layer; use the patterned photoresist layer as a mask to remove part of the dielectric layer to form a pattern patterning the dielectric layer, wherein the patterned dielectric layer exposes part of the transparent conductive layer; removing the patterned photoresist layer.
综上所述,相较于公知技艺必须使用五个掩模始能制作像素结构而言,本发明仅使用三个掩模即完成制作像素结构,因此像素结构的制作成本可以降低。To sum up, compared with the prior art that requires five masks to fabricate the pixel structure, the present invention only uses three masks to complete the fabrication of the pixel structure, so the fabrication cost of the pixel structure can be reduced.
附图说明 Description of drawings
图1A~1E为公知的一种像素结构的形成过程的剖面示意图。1A-1E are schematic cross-sectional views of a known formation process of a pixel structure.
图2A~2M为依照本发明一实施例的像素结构的形成过程的剖面示意图。2A-2M are schematic cross-sectional views of the formation process of the pixel structure according to an embodiment of the present invention.
图3A~3C为依照本发明一实施例的移除介电层过程的剖面示意图。3A-3C are schematic cross-sectional views of a process for removing a dielectric layer according to an embodiment of the present invention.
图4A~4D为依照本发明另一实施例的移除介电层过程的剖面示意图。4A-4D are schematic cross-sectional views of a process of removing a dielectric layer according to another embodiment of the present invention.
图5A为依照本发明一实施例的端子结构的示意图。FIG. 5A is a schematic diagram of a terminal structure according to an embodiment of the invention.
图5B为图5A中沿A-A’线的剖面示意图。Fig. 5B is a schematic cross-sectional view along line A-A' in Fig. 5A.
符号说明:Symbol Description:
50、60:基板50, 60: Substrate
100:像素结构100: pixel structure
110:源极 210:第一掩模110: source 210: first mask
120:漏极 220:第二掩模120: drain 220: second mask
130:沟道层 230:第三掩模130: channel layer 230: third mask
140:第一介电层 240:第四掩模140: the first dielectric layer 240: the fourth mask
150:栅极 250:第五掩模150: gate 250: fifth mask
160:第二介电层160: second dielectric layer
170:接触窗开口170: contact window opening
180:透明导电层180: transparent conductive layer
300、300a、300b:像素结构300, 300a, 300b: pixel structure
310:源极 410:第一掩模310: source 410: first mask
320:漏极 420:第二掩模320: drain 420: second mask
330:欧姆接触层 430:第三掩模330: ohmic contact layer 430: third mask
340:透明导电层340: transparent conductive layer
350:沟道层350: channel layer
360:介电层360: dielectric layer
362、364:图案化介电层362, 364: patterned dielectric layer
370:栅极370: Gate
510:导电层 520、580:光刻胶层510:
522、570、582:图案化光刻胶层522, 570, 582: patterned photoresist layer
530:透明导电材料层 540:第一型图案化光刻胶层530: transparent conductive material layer 540: first type patterned photoresist layer
550:沟道材料层 560:第二型图案化光刻胶层550: channel material layer 560: second type patterned photoresist layer
600:端子结构 610:导线600: Terminal structure 610: Wire
620:透明导线 630:非晶质硅层620: transparent wire 630: amorphous silicon layer
θ:角度θ: angle
具体实施方式 Detailed ways
为让本发明的上述和其它目的、特征和优点能更明显易懂,下文特举较佳实施例,并配合所附图式,作详细说明如下。In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.
图2A~2M为依照本发明一实施例的像素结构的形成过程的剖面示意图。请参考图2A,首先在一基板60上形成一导电层510,其中导电层510的材质可以选自铝(Al)、钼(Mo)、氮化钼(MoN)、钛(Ti)、氮化钛(TiN)、铬(Cr)、氮化铬(CrN)或其组合。在本实施例中,导电层510可以为钛/铝/氮化钛三层堆栈的结构,其中铝的较佳厚度是介于500~2000之间,且钛或氮化钛的较佳厚度是介于300~1000之间。再来形成一光刻胶层520于导电层510上,并利用一第一掩模410作为屏蔽对光刻胶层520进行曝光工艺。2A-2M are schematic cross-sectional views of the formation process of the pixel structure according to an embodiment of the present invention. Please refer to FIG. 2A. First, a
请参考图2B,接着对光刻胶层520进行显影工艺以形成一图案化光刻胶层522。在本实施例中,光刻胶层520的型态可以为负型光刻胶(negativephotoresist),其中有受到曝光的部分光刻胶层520则不会被显影掉而形成图案化光刻胶层522。请参考图2C,接着以图案化光刻胶层522为掩模进行蚀刻工艺,以移除部分导电层510而形成源极310/漏极320。请参考图2D,接着进行剥膜(stripper)工艺以移除图案化光刻胶层522即完成以第一掩模410于基板60上形成源极310/漏极320的制作过程(如图2A~2D所示)。请参考图2E,为使源极310/漏极320能具有更佳的电特性,本发明例如以第一掩模410于源极310/漏极320上形成一欧姆接触层330,其中详细制作过程均类似前述步骤,于此不再赘述。在本实施例中,欧姆接触层330的材质可以为重掺杂的非晶质硅(n+ amorphous silicon,n+α-Si),且其较佳厚度是介于500~4000之间。且本发明亦可以其它过程形成欧姆接触层330。举例而言,在形成导电层510之后(如图2A所示),可以接着形成欧姆接触材料层(未绘示)于导电层510上,再来才形成光刻胶层520于欧姆接触材料层上。对光刻胶层520进行曝光工艺与显影工艺以形成图案化光刻胶层522。之后,进行蚀刻工艺移除部分欧姆接触材料层而形成欧姆接触层330,并移除部分导电层510而形成源极310/漏极320。最后进行剥膜工艺以移除图案化光刻胶层522(如图2E所示)。Referring to FIG. 2B , the
请参考图2F,接着在基板60上形成一透明导电材料层530以覆盖源极310/漏极320,其中透明导电材料层530的材质可以为氧化铟锡(Indium TinOxide,ITO)或氧化铟锌(Indium Zinc Oxide,IZO),且其较佳厚度是介于500~3000之间。接着使用一第二掩模420在透明导电材料层530上形成第一型图案化光刻胶层540,其中第一型图案化光刻胶层540的型态可以为正型光刻胶(positive photoresist)。请参考图2G,接着以第一型图案化光刻胶层540为掩模移除部分透明导电材料层530以形成一透明导电层340,其中透明导电层340覆盖部分源极310/漏极320,并电性连接至源极310/漏极320。请参考图2H,接着进行剥膜工艺以移除第一型图案化光刻胶层540即完成以第二掩模420于基板60上形成透明导电层340的制作过程(如图2F~2H所示)。Please refer to FIG. 2F, and then form a transparent conductive material layer 530 on the
请参考图2I,接着在基板60上形成一沟道材料层550以覆盖源极/漏极310、320及透明导电层340,其中沟道材料层550的材质可以为非晶质硅(amorphous silicon,α-Si),且其较佳厚度是介于500~4000之间。接着使用第二掩模420在沟道材料层550上形成第二型图案化光刻胶层560,其中第二型图案化光刻胶层560的型态可以为负型光刻胶。请参考图2J,接着以第二型图案化光刻胶层560为掩模移除部分沟道材料层550以形成一沟道层350,其中沟道层350覆盖部分源极310与部分漏极320,且沟道层350的图案与透明导电层340的图案成互补。请参考图2K,接着进行剥膜工艺以移除第二型图案化光刻胶层560即完成以第二掩模420于基板60上形成沟道层350的制作过程(如图2I~2K所示)。Please refer to FIG. 2I, then a
本发明并不限定形成透明导电层340与沟道层350的先后顺序。亦即本发明可以先完成如图2I~2K所示的制作过程以形成沟道层350,接着再完成如图2F~2H所示的制作过程以形成透明导电层340。此外,本发明可以交换第一型图案化光刻胶层540及第二型图案化光刻胶层560的型态,亦即第一型图案化光刻胶层540的型态为负型光刻胶,而第二型图案化光刻胶层560的型态为正型光刻胶。当然,在此实施例中,本发明亦须对应调整第二掩模420的透光区域与不透光区域。熟悉此技艺者可轻易推得上述的各项情形,此处不再绘图示之。The present invention does not limit the sequence of forming the transparent
请参考图2L,接着在基板60上形成一介电层360,其中介电层360的材质可以为硅氮化物(SiNx)、硅氧化物(SiOx)或硅氧氮化物(SiOxNy)。此外,介电层360可以是利用等离子体增强式化学蒸气沉积法(PlasmaEnhanced Chemical Vapor Deposition,PECVD)形成,而其较佳的厚度是介于1500~4000之间,且其较佳的成长温度以不超过300℃为宜。Referring to FIG. 2L, a
请参考图2M,接着利用一第三掩模430于介电层360上形成一栅极370,其中详细制作过程均类似前述步骤(如图2A~2D所示的工艺步骤),于此不再赘述。此外,栅极370的材质可以选自铝、钼、氮化钼、钛、氮化钛、铬、氮化铬或其组合。在本实施例中,栅极370可以为氮化钛/铝/钛/氮化钛四层堆栈的结构,其中铝的较佳厚度是介于500~2000之间,且钛或氮化钛的较佳厚度是介于300~1000之间。Please refer to FIG. 2M, and then use a
承接上述,至此步骤即完成制作本发明的像素结构300。由于本发明只使用第一掩模410、第二掩模420及第三掩模430共三个掩模即完成制作像素结构300,因此可以降低像素结构300的制作成本。本发明是重复使用第二掩模420并搭配正、负光刻胶进行光微影(photolithography)工艺而分别形成透明导电层340及沟道层350,如此以减少掩模的使用数量。Following the above, the steps up to this point are to complete the fabrication of the
为使像素结构300具有更佳的透光效果,本发明可进一步移除部分透明导电层340上方的介电层360。图3A~3C为依照本发明一实施例的移除介电层过程的剖面示意图,其中图3A是接续图2M之后的流程。请参考图3A,首先使用第一掩模410在介电层360与栅极370上形成一图案化光刻胶层570。请参考图3B,接着以图案化光刻胶层570为掩模进行蚀刻工艺移除部分介电层360,以形成一图案化介电层362,其中图案化介电层362暴露出部分透明导电层340。In order to make the
承接上述,在本实施例中,蚀刻工艺可以选用高选择比的干蚀刻工艺,以避免栅极370在蚀刻过程中同时被移除。详细地而言,蚀刻气体可由氟化硫(SF6)/氟化硫(CF4)/氮(N2)/氧(O2)所组成,且当操作压力介于1~5毫托尔(mTorr)时,则介电层360对栅极370的蚀刻选择比会介于2.0~3.0之间,可确保在蚀刻过程中不会损坏栅极370的结构。请参考图3C,接着进行剥膜工艺以移除图案化光刻胶层570即完成具有图案化介电层362的像素结构300a的制作过程(如图3A~3C所示)。Following the above, in this embodiment, the etching process may be a dry etching process with a high selectivity ratio, so as to prevent the
在上述移除介电层360的过程中,是利用第一掩模410并搭配高选择比的蚀刻工艺所完成,因此不需再额外增设掩模数,故可以降低像素结构300a的制作成本。此外,本发明并不限定以上述方式移除部分透明导电层340上方的介电层360,以下将另举实施例作说明。The above-mentioned process of removing the
图4A~4C为依照本发明另一实施例的移除介电层过程的剖面示意图,其中图4A是接续图2M之后的流程。请参考图4A,首先在介电层360与栅极370上形成一光刻胶层580,并以源极310/漏极320与栅极370作为屏蔽从基板60下方对光刻胶层580进行曝光工艺,此即为俗称的背曝技术(Back lightexposure technology)。为提升曝光的品质与效果,在本实施例中,曝光光源的较佳波长是介于100~450nm之间,且对应的光刻胶层580是选用高感度的光刻胶。此外,源极/漏极310、320与栅极370结构中最底层的材质可为氮化钛,以作为抗反射之用,如此在曝光过程中可减少驻波现象而提升曝光效果。源极310/漏极320与栅极370可以有部分重叠,且其较佳的重叠范围为1.5μm。4A-4C are schematic cross-sectional views of a process for removing a dielectric layer according to another embodiment of the present invention, wherein FIG. 4A is a process following FIG. 2M . Please refer to FIG. 4A. First, a photoresist layer 580 is formed on the
请参考图4B,接着对光刻胶层580进行显影工艺以形成一图案化光刻胶层582。在本实施例中,光刻胶层580的型态为正型光刻胶,其中未受到曝光的部分光刻胶层580则不会被显影掉而形成图案化光刻胶层582。此外,图案化光刻胶层582的形成角度θ以介于45°与80°之间为较佳范围。请参考图4C,接着以图案化光刻胶层582为掩模进行蚀刻工艺移除部分介电层360,以形成一图案化介电层364,其中图案化介电层364暴露出部分透明导电层340。请参考图4D,接着进行剥膜工艺以移除图案化光刻胶层582即完成具有图案化介电层364的像素结构300b的制作过程(如图4A~4D所示)。Referring to FIG. 4B , the photoresist layer 580 is then developed to form a patterned
在上述移除介电层360的过程中,是以源极310/漏极320与栅极370作为屏蔽进行背曝工艺所完成,因此不需再额外增设掩模数,故可以降低像素结构300b的制作成本。此外,本发明仅利用三个掩模的工艺方法亦可以形成端子结构,以下将配合图标说明。In the above-mentioned process of removing the
图5A为依照本发明一实施例的端子结构的示意图,而图5B为图5A中沿A-A’线的剖面示意图。请同时参考图5A及图5B,本发明的端子结构600主要是由一导线610、一透明导线620及一非晶质硅层630所组成,其中导线610与透明导线620电性连接,并适于传递电讯号。导线610可由形成源极310/漏极320的过程中(如图2A~2D所示)同时形成,而透明导线620可由形成透明导电层340的过程中(如图2F~2H所示)同时形成,且非晶质硅层630可由形成沟道层350的过程中(如图2I~2K所示)同时形成。FIG. 5A is a schematic diagram of a terminal structure according to an embodiment of the present invention, and FIG. 5B is a schematic cross-sectional view along line A-A' in FIG. 5A. Please refer to FIG. 5A and FIG. 5B at the same time. The
综上所述,本发明的像素结构的制作方法至少具有下列优点:In summary, the manufacturing method of the pixel structure of the present invention has at least the following advantages:
一、相较于公知技艺必须使用五个掩模始能制作像素结构而言,本发明仅需使用三个掩模即完成制作像素结构,因此像素结构的制作成本可以降低。1. Compared with the prior art that needs to use five masks to fabricate the pixel structure, the present invention only needs to use three masks to complete the fabrication of the pixel structure, so the fabrication cost of the pixel structure can be reduced.
二、本发明的像素结构的制作方法与现有的工艺兼容,因此无须增加额外的工艺设备。2. The manufacturing method of the pixel structure of the present invention is compatible with the existing process, so no additional process equipment is needed.
虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,任何熟习此技艺者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视申请专利范围所界定者为准。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of an invention shall be determined by the scope of the patent application.
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US20050140841A1 (en) * | 2003-12-29 | 2005-06-30 | Lg.Philips Lcd Co.Ltd. | Liquid crystal display device and fabricating method thereof |
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US20050140841A1 (en) * | 2003-12-29 | 2005-06-30 | Lg.Philips Lcd Co.Ltd. | Liquid crystal display device and fabricating method thereof |
CN1677208A (en) * | 2004-03-29 | 2005-10-05 | 广辉电子日本株式会社 | Liquid crystal display device and manufacturing method thereof |
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