CN100377104C - Device for capturing memory access information in real time and method for capturing memory access information - Google Patents

Abstract

The invention discloses a real-time capture device for memory access information and a method for capturing memory access information. The device includes a memory signal capture logic unit, a data buffer unit, a high-speed data interface unit, an embedded processor unit, and a configuration buffer unit. The logic unit utilizes high-speed IO, large-capacity RAM and an embedded processor to realize a high-speed memory interface and a data transmission interface, and preprocess the data, and the real-time capture device for memory access information receives a memory controller signal. Since the parallel DDR memory interface is used as the capture interface, high-speed FIFO and high-speed IO are used for data storage and transmission, and it is realized by operating system patches and tool software. The device provided by the invention can realize real-time and high-speed memory access information capture without modifying the original system hardware and having little impact on system performance.

Description

Device for capturing memory access information in real time and method for capturing memory access information

technical field

The invention relates to the field of high-performance computing, in particular to a device for capturing memory access information in real time and a method for capturing memory access information.

Background technique

Tracing and acquisition (profikling) of memory access information is traditionally used for program compilation and optimization to improve program performance. At the same time, in the research and implementation of high-performance computers, remote distributed storage is an important way, especially the use of optical interconnection, which can pull the local memory to the remote end and realize the loose coupling of memory and processor. In order to hide remote memory latency, prefetching is an important and effective way, but an efficient prefetching strategy requires an understanding of memory access patterns as a basis.

Existing memory access information capture and tracking (profiling) methods can be classified into software methods, hardware methods and methods combining hardware and software.

Most profiling methods are software methods, which have great flexibility to obtain information by inserting specific instructions or modules where needed in the code. But what is obtained is the information seen by the processor, not the targeted physical memory access information, that is, the real mode seen by the physical memory side. If want to obtain them, must have hardware support, so pure software method can't accomplish the goal of the present invention. Moreover, the software method has high overhead, poor real-time performance, and has a great impact on system performance, and the application needs to be recompiled.

The profiling technology supported by hardware can overcome the impact of the overhead problem to a certain extent. Modern processors such as the Pentium have internal registers for performance statistics that can be read by software tools. However, these registers only provide cumulative statistical results, such as the number of cache misses, etc., and cannot provide detailed process records and distributions. In addition, special instructions or interrupts are required to obtain information, which has a great impact on system performance. Methods such as logic analyzers can collect real-time information, but the ease of use is poor and the cost is high.

Contents of the invention

The technical problem to be solved by the present invention is to provide a real-time, high-speed, low-overhead real-time capture device for memory access information without modifying the original system hardware and with little impact on system performance. The device uses parallel DDR As a capture interface, the memory interface uses high-speed FIFO and high-speed IO for data storage and transmission, supported by operating system patches and tool software; and provides a method for using the device to capture memory access information in real time; at the same time, the system performance The impact and modification of software and hardware are small, and the ease of use is high.

In order to solve the above technical problems, the present invention provides a real-time capture device for memory access information, including a memory signal capture logic unit 10, a data buffer unit 20, a high-speed data interface unit 30, an embedded processor unit 40 and a configuration buffer unit 50 , these logic units utilize high-speed IO, large-capacity RAM and embedded processor, realize high-speed memory interface and data transmission interface, and carry out preprocessing to data, described memory access information real-time capturing device receives memory controller signal;

Wherein, the memory signal capture logic unit 10 implements a subset of the JEDEC DDR RAM specification, parses the commands of the DDR memory, and identifies and captures addresses and data;

The data buffer unit 20 includes a high-speed FIFO buffer and related control logic, and the memory signal capture logic unit 10 writes the captured information into the FIFO; the FIFO provides empty, full, counters, etc., for use in flow control;

The high-speed data interface unit 30 is used to send data to the host, or receive control and configuration commands from the host and pass them to the configuration buffer unit 50;

The configuration buffer unit 50 receives capture rules through the memory signal capture logic unit 10 to filter information, and transmits the filtered information to the memory signal capture logic unit 10 .

In the above solution, among the several DDR memory slots controlled by the memory controller, except for the chip select signal line, other signal lines are shared in the form of a bus, and the memory access information of the processor is obtained by monitoring the memory bus.

In the above solution, the real-time capture device for memory access information uses a USB2.0 interface or a multi-channel Xilinx dedicated high-speed IO channel to transmit captured data.

In the above scheme, the configuration buffer unit 50 is configured dynamically.

In the above solution, the memory signal capture logic unit 10 is controlled by the rules in the configuration buffer unit 50 .

The present invention also provides a method for capturing memory access information, comprising the following steps:

a) The memory access information real-time capture device receives the memory access signal sent by the processor through the DDR slot of the motherboard;

b) the memory signal capture logic unit 10 captures the memory access information;

c) configure the buffer unit 50 to capture the capture rules received by the memory signal capture logic unit 10, filter the memory access information, and pass the filtered information to the memory signal capture logic unit 10;

d) the memory signal capture logic unit 10 stores the filtered memory access information into the data buffer unit 20;

E) the embedded processor unit 40 processes the data in the data buffer unit 20;

f) the processed data is sent into the high-speed data interface unit 30 by the data buffer unit 20;

g) The embedded processor unit 40 controls the high-speed data interface unit 30 to send out the processed data.

As can be seen from the above, the present invention adopts the parallel DDR interface as the capture interface, carries out data storage and transmission with high-speed FIFO and high-speed IO, and is supported by operating system patches and tool software; the device provided by the present invention can be used without modifying the original In the case of system hardware and little impact on system performance, real-time and high-speed memory access information capture can be achieved, and full-spectrum memory access records including time and space distribution can be obtained.

Description of drawings

Fig. 1 is the working mode of the real-time capture device for memory access information of the present invention.

FIG. 2 is a structural diagram of a device for capturing memory access information in real time according to the present invention.

Fig. 3 is a flow chart of the method for capturing memory access information of the present invention.

Detailed ways

The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

As shown in Figure 1, the memory access information real-time capture device and common DDR memory are inserted in parallel on the DDR memory slot. The bold signal line is a shared bus, and the line with an arrow is a separate chip select signal line; between several DDR memory slots controlled by the memory controller, except for the chip select signal, other signal lines are shared in the form of a bus, through Monitor the memory bus to obtain memory access information from the processor. The capture device can receive the communication between the processor and the normal memory stick, but since the processor cannot access it, its chip select line will not be strobed.

As shown in FIG. 2 , the real-time capture device for memory access information includes a memory signal capture logic unit 10 , a data buffer unit 20 , a high-speed data interface unit 30 , an embedded processor unit 40 and a configuration buffer unit 50 . These units described are realized by VirtexII Pro FPGA of Xilinx Company. This type of FPGA is equipped with high-speed IO, large-capacity RAM and embedded processor, which can realize high-speed DDR memory interface, high-speed data transceiver interface and data preprocessing function, and can also reconstruct the functional logic according to different needs, thereby increasing system functions , reduce system cost.

Wherein, the memory signal capture logic unit 10 implements a subset of the JEDEC DDRRAM specification, and can analyze commands of the DDR memory, and identify and capture addresses and data.

The data buffer unit 20 includes a high-speed FIFO buffer, and the memory signal capture logic unit 10 writes the captured information into the FIFO. FIFO provides empty, full, counters, etc. for flow control.

The high-speed data interface unit 30 is used to send data to the host, or receive control and configuration commands from the host and transmit them to the configuration buffer unit 50 .

The configuration buffer unit 50 receives capture rules through the memory signal capture logic unit 10 to filter information, and transmits the filtered information to the memory signal capture logic unit 10 .

As shown in Figure 3, a memory access information capture method includes the following steps:

Step 10, the memory access information real-time capture device receives the memory access signal sent by the processor through the DDR slot of the motherboard;

Step 20, the memory signal capture logic unit 10 captures the memory access information;

Step 30, configure the buffer unit 50 to capture the capture rules received by the memory signal capture logic unit 10, filter the memory access information, and pass the filtered information to the memory signal capture logic unit 10;

Step 40, the memory signal capture logic unit 10 stores the filtered memory access information into the data buffer unit 20;

Step 50, the embedded processor unit 40 processes the data in the data buffer unit 20;

Step 60, the processed data is sent to the high-speed data interface unit 30 by the data buffer unit 20;

Step 70, the embedded processor unit 40 controls the high-speed data interface unit 30 to send the processed data.

The invention may also include operating system patches and software tools to support the card.

The operating system patch monitors the physical memory usage of the specified application through the user's settings, obtains its physical address space, and sets the configuration buffer of the real-time capture device for memory access information to target these specific physical addresses range to capture. The operating system patch can also map the physical memory space occupied by the capture device to the user space through the memory mapping system call (mmap) of the operating system, so as to access the configuration buffer unit. The software tool is the interface between the user and the operating system patch, and the user uses it to specify the application to be captured and set the capture rules.

The key point of the real-time capture device for memory access information is realized by the DDR (Double Data Rate) memory interface. Using the DDR interface has two advantages:

First of all, among the several DDR memory slots controlled by the memory controller, except for the chip select signal, other signal lines are shared in the form of a bus. Therefore, the memory access information of the processor can be obtained by monitoring the memory bus, which will not System performance is affected without modifying the original system hardware;

Secondly, directly using the DDR interface, there is enough bandwidth and processing power to capture and transmit the collected data, that is, the real-time performance can be satisfied. Through the tools and simulators, the relevant test programs of SPEC2000 are counted, and the order of magnitude of the access address information is obtained. In the case of a second-level cache miss and a large cache block, DDR200 and above have sufficient capacity to record and transmit these information.

The device for capturing memory access information in real time of the present invention is inserted into the idle DDR memory slot of the motherboard. The card implements the JEDEC DDR RAM specification and is able to recognize commands, addresses and data through the memory controller signals present on the memory bus.

Preventing capture cards from interfering with the memory bus is a key issue. In the DDR interface specification, except DQ, DQS and other signals are bidirectional, other signals are transmitted from the memory controller side to the slot side. In fact, when doing capture, it is enough to get one-way signals. Therefore, these signals are not transmitted to the controller during implementation, so there will be no interference with other memory modules and memory control rights.

The order of magnitude of the access information is very large, and in order to ensure real-time performance, some processing needs to be done separately. The capture of address information is the most important goal of the present invention. In the case of a cache miss and memory access operation, only the first address of the cache block needs to be recorded, so that the amount of data to be collected and transmitted can be greatly reduced.

In order to transmit real-time high-speed data, the logic provides high-speed data FIFO as a buffer. The other end sends data to the host through the high-speed data interface. The high-speed data interface must have a high-speed bandwidth that matches the real-time acquisition of data. For address capture, the bandwidth of USB2.0 can meet the requirements, and for data capture, higher bandwidth is required. The present invention uses a USB2.0 interface or a Xilinx dedicated high-speed IO channel to realize the transmission of captured data, and other types of high-speed data access interfaces are also applicable.

In the present invention, the device for real-time capture of memory access information can capture all memory access information. However, the user may only be interested in the fetching information of some specific applications. The invention provides an operating system patch, which can acquire the physical address space of different applications and set the address window of the capture card. Using the software tool, the user can set the target to be captured. The software tool also includes a receiver program for receiving data from the capture card.

The above are only some basic explanations under the technical conception of the present invention, and any equivalent transformation done according to the technical solution of the present invention should belong to the scope of protection of the present invention, for example, for SDRAM systems, memory slots are not used Instead, methods using the motherboard bus or memory controller output, etc., are protected objects.

Finally, it should be noted that: the above embodiments are only used to illustrate and not limit the technical solutions of the present invention, although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: the present invention can still be modified or Any modification or partial replacement without departing from the spirit and scope of the present invention shall fall within the scope of the claims of the present invention.

Claims (7)

1. internal storage access information captured in real time device, comprise internal memory signal capture logical block (10), unit, data buffer (20), high speed interface unit (30), flush bonding processor unit (40) and configuration buffer location (50), described internal memory signal capture logical block (10), unit, data buffer (20), high speed interface unit (30), flush bonding processor unit (40) and configuration buffer location (50) utilize High-speed I, high capacity RAM and flush bonding processor, realize high-speed internal memory interface and data transmit-receive interface, and data are carried out pre-service, described internal storage access information captured in real time device receives the Memory Controller Hub signal;

Wherein, internal memory signal capture logical block (10) has realized the subclass of JEDEC DDR RAM standard, and the order of DDR internal memory is resolved, and address and data are discerned and caught;

Unit, data buffer (20) comprises high speed FIFO buffer zone and relevant steering logic, and internal memory signal capture logical block (10) writes this FIFO with the information of catching; That FIFO provides is empty, full, counter etc., uses for flow control;

High speed interface unit (30) is used for that data are sent to main frame or receives control and the configuration order that main frame transmits passing to configuration buffer location (50);

Configuration buffer location (50) receives capture rule by internal memory signal capture logical block (10), and in order to information is filtered, and the information after will filtering is passed to internal memory signal capture logical block (10).

2. a kind of internal storage access information captured in real time device as claimed in claim 1 is characterized in that, the Memory Controller Hub signal of internal storage access information captured in real time device by occurring on the rambus, recognition command, address and data.

3. internal storage access information captured in real time device as claimed in claim 1 is characterized in that, internal storage access information captured in real time device uses USB2.0 interface or Xilinx specialized high-speed IO passage to realize catching the transmission of data.

4. internal storage access information captured in real time device as claimed in claim 1, it is characterized in that, high speed interface unit (30) sends to the packing data in unit, data buffer (20) main frame by USB interface or high-speed serial channel and stores and analyze; Unit, data buffer (20), high speed interface unit (30) and upper layer drivers cooperate jointly, carry out flow control.

5. internal storage access information captured in real time device as claimed in claim 1, it is characterized in that, described configuration buffer location (50) receives capture rule by internal memory signal capture logical block (10), in order to information is filtered, and the information after will filtering is passed to internal memory signal capture logical block (10).

6. internal storage access information captured in real time device as claimed in claim 1 is characterized in that, internal memory signal capture logical block (10) is by the control of the rule in the configuration buffer location (50).

7. an application rights requires 1 described internal storage access information captured in real time device to carry out the method for memory access information capture, may further comprise the steps:

A) the memory access signal sent by the DDR slot of motherboard of internal storage access information captured in real time device receiving processor;

B) internal memory signal capture logical block (10) captures memory access information;

C) capture rule that receives by internal memory signal capture logical block (10) of configuration buffer location (50), in order to information is filtered, and the information after will filtering is passed to internal memory signal capture logical block (10);

D) internal memory signal capture logical block (10) the memory access information that will cross filtration deposits unit, data buffer (20) in;

E) handle the data in the data buffer location (20) flush bonding processor unit (40);

F) data processed is sent into high speed interface unit (30) by unit, data buffer (20);

G) data processed is sent in flush bonding processor unit (40) control high speed interface unit (30).

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