We present a systematic study of the influence of the encapsulation temperature on dopant confine... more We present a systematic study of the influence of the encapsulation temperature on dopant confinement and electrical properties of Ge:P delta-doped layers. For increasing growth temperature we observe an enhancement of the electrical properties accompanied by an increased segregation of the phosphorous donors, resulting in a slight broadening of the delta-layer. We demonstrate that a step-flow growth achieved at 530 C provides the best compromise between high crystal quality and minimal dopant redistribution, with an electron mobility ~ 128 cm^2/Vs at a carrier density 1.3x10^14 cm-2, and a 4.2 K phase coherence length of ~ 180 nm.
Phosphorus (P) in germanium (Ge) δ-doped layers are fabricated in ultrahigh vacuum by adsorption ... more Phosphorus (P) in germanium (Ge) δ-doped layers are fabricated in ultrahigh vacuum by adsorption of phosphine molecules onto an atomically flat clean Ge(001) surface followed by thermal incorporation of P into the lattice and epitaxial Ge overgrowth by molecular beam epitaxy. Structural and electrical characterizations show that P atoms are confined, with minimal diffusion, into an ultranarrow 2-nm-wide layer with an electrically active sheet carrier concentration of 4×1013 cm-2 at 4.2 K. These results open up the possibility of ultranarrow source/drain regions with unprecedented carrier densities for Ge n-channel field effect transistors.
In this paper we demonstrate atomic-scale lithography on hydrogen terminated Ge(001). The lithogr... more In this paper we demonstrate atomic-scale lithography on hydrogen terminated Ge(001). The lithographic patterns were obtained by selectively desorbing hydrogen atoms from a H resist layer adsorbed on a clean, atomically flat Ge(001) surface with a scanning tunneling microscope tip operating in ultra-high vacuum. The influence of the tip-to-sample bias on the lithographic process have been investigated. Lithographic patterns with feature-sizes from 200 to 1.8 nm have been achieved by varying the tip-to-sample bias. These results open up the possibility of a scanning-probe lithography approach to the fabrication of future atomic-scale devices in germanium.
In this paper we demonstrate the fabrication of multiple, narrow, and closely spaced δ-doped P la... more In this paper we demonstrate the fabrication of multiple, narrow, and closely spaced δ-doped P layers in Ge. The P profiles are obtained by repeated phosphine adsorption onto atomically flat Ge(001) surfaces and subsequent thermal incorporation of P into the lattice. A dual-temperature epitaxial Ge overgrowth separates the layers, minimizing dopant redistribution and guaranteeing an atomically flat starting surface for each doping cycle. This technique allows P atomic layer doping in Ge and can be scaled up to an arbitrary number of doped layers maintaining atomic level control of the interface. Low sheet resistivities (280 \Omega /\square ) and high carrier densities (2 × 1014 cm - 2, corresponding to 7.4 × 1019 cm - 3) are demonstrated at 4.2 K.
We have developed a method to integrate a low thermal budget silicon dioxide dielectric in ultrah... more We have developed a method to integrate a low thermal budget silicon dioxide dielectric in ultrahigh vacuum to surface gate an in-plane gated phosphorus donor quantum dot in silicon. By combining in-plane and top-gate action, the resistance of the quantum dot tunnel barriers can be tuned to change the dot from open to closed where clear Coulomb blockade of the electron transport has been observed at 4 K. Additionally the scanning tunneling microscopy patterned in-plane gates can be used to independently tune the electron number on the dot. This enhanced tunability of donor based quantum dots bodes well for the fabrication of single donor architectures.
Physica E-low-dimensional Systems & Nanostructures, 2008
We study the low temperature electrical characteristics of planar, highly phosphorus-doped nanodo... more We study the low temperature electrical characteristics of planar, highly phosphorus-doped nanodots. The dots are defined by lithographically patterning an atomically flat, hydrogenated Si(100):H surface using a scanning-tunneling-microscope (STM), phosphorus δ-doping and low temperature molecular beam epitaxy in an ultra-high vacuum environment. Ohmic contacts and a surface gate structure are aligned ex-situ using electron beam lithography. We present electrical transport
In this paper we demonstrate atomic-scale lithography on hydrogen terminated Ge(001. The lithogra... more In this paper we demonstrate atomic-scale lithography on hydrogen terminated Ge(001. The lithographic patterns were obtained by selectively desorbing hydrogen atoms from a H resist layer adsorbed on a clean, atomically flat Ge(001) surface with a scanning tunneling microscope tip operating in ultra-high vacuum. The influence of the tip-to-sample bias on the lithographic process have been investigated. Lithographic patterns with feature-sizes from 200 nm to 1.8 nm have been achieved by varying the tip-to-sample bias. These results open up the possibility of a scanning-probe lithography approach to the fabrication of future atomic-scale devices in germanium.
An important driving force behind the microelectronics industry is the ability to pack ever more ... more An important driving force behind the microelectronics industry is the ability to pack ever more features onto a silicon chip, by continually miniaturising the individual components. However, after 2015 there is no known technological route to reduce devices below 10 nm. We demonstrate a complete fabrication strategy towards atomic-scale device fabrication in silicon using phosphorus as a dopant in combination with scanning probe lithography and high purity, low temperature crystal growth. A major advantage of this strategy is the ability to investigate the role of dopant placement and atomically controlled growth on electronic device operation.
Page 1. IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 2, MARCH 2007 213 Electrical Characteriz... more Page 1. IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 2, MARCH 2007 213 Electrical Characterization of Ordered Si:P Dopant Arrays Wilson Pok, Thilo CG Reusch, Giordano Scappucci, Frank J. Rueß, Alex R. Hamilton, and Michelle Y. Simmons ...
We demonstrate the preparation of a clean Ge(001) surface with minimal roughness (RMS ~ 0.6 Å), l... more We demonstrate the preparation of a clean Ge(001) surface with minimal roughness (RMS ~ 0.6 Å), low defect densities (~0.2% ML) and wide mono-atomic terraces (~80-100 nm). We use an ex situ wet chemical process combined with an in situ anneal treatment followed by a homoepitaxial buffer layer grown by molecular beam epitaxy and a subsequent final thermal anneal. Using scanning tunneling microscopy, we investigate the effect on the surface morphology of using different chemical reagents, concentrations as well as substrate temperature during growth. Such a high quality Ge(001) surface enables the formation of defect-free H-terminated Ge surfaces for subsequent patterning of atomic-scale devices by scanning tunneling lithography. We have achieved atomic-scale dangling bond wire structures 1.6 nm wide and 40 nm long as well as large, micron-size patterns with clear contrast of lithography in STM images.
Page 1. IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 2, MARCH 2007 213 Electrical Characteriz... more Page 1. IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 2, MARCH 2007 213 Electrical Characterization of Ordered Si:P Dopant Arrays Wilson Pok, Thilo CG Reusch, Giordano Scappucci, Frank J. Rueß, Alex R. Hamilton, and Michelle Y. Simmons ...
We present an ultrahigh vacuum technique for depositing SiO2 at room temperature using an atomic ... more We present an ultrahigh vacuum technique for depositing SiO2 at room temperature using an atomic oxygen source and Si coevaporation for ultimate use as a dielectric for gating Si devices with atomically precise dopant profiles. The resulting SiO2 layers were characterized in situ by scanning tunneling microscopy, ex situ by transmission electron microscopy and ellipsometry and integrated as the gate dielectric in a metal oxide semiconductor field effect transistor (MOSFET). The electrical characteristics of the MOSFETs were investigated at 4.2K, giving an interface trap density of ˜1011cm-2 from conductance and Hall effect measurements.
Low field magnetotransport revealing signatures of ballistic transport effects in strained Si/SiG... more Low field magnetotransport revealing signatures of ballistic transport effects in strained Si/SiGe cavities is investigated. We fabricated strained Si/SiGe cavities by confining a high mobility Si/SiGe 2DEG in a bended nanowire geometry defined by electron-beam lithography and reactive ion etching. The main features observed in the low temperature magnetoresistance curves are the presence of a zero-field magnetoresistance peak and of an oscillatory structure at low fields. By adopting a simple geometrical model we explain the oscillatory structure in terms of electron magnetic focusing. A detailed examination of the zero-field peak lineshape clearly shows deviations from the predictions of ballistic weak localization theory.
We report on the electrical transport of wire-based devices fabricated on modulation-doped Si/SiG... more We report on the electrical transport of wire-based devices fabricated on modulation-doped Si/SiGe two-dimensional electron gas. Two different geometries were investigated: straight and bended wires. In both cases, we found typical features of Coulomb blockade regime. Nevertheless, single electron transistor effects were found only on wires with bends. Reported data suggest that the insertion of bends is a suitable tool
We fabricated strongly confined Schottky-gated quantum point contacts by etching Si/SiGe heterost... more We fabricated strongly confined Schottky-gated quantum point contacts by etching Si/SiGe heterostructures and observed intriguing conductance quantization in units of approximately 1e2/h. Non-linear conductance measurements were performed depleting the quantum point contacts at fixed mode-energy separation. We report evidences of the formation of a half 1e2/h plateau, supporting the speculation that adiabatic transmission occurs through 1D modes with complete removal of valley and spin degeneracies.
We report the characterization of a single-electron transistor based on bended wires fabricated o... more We report the characterization of a single-electron transistor based on bended wires fabricated on modulation-doped SiGe two-dimensional electron gas. Electrical measurements show a diamond-shaped stability plot and a nonperiodic sequence of conductance peaks. The device behavior suggests the presence of disorder-induced multiple islands along the wire. Conductance oscillations remain well pronounced above liquid helium temperature.
We present a systematic study of the influence of the encapsulation temperature on dopant confine... more We present a systematic study of the influence of the encapsulation temperature on dopant confinement and electrical properties of Ge:P delta-doped layers. For increasing growth temperature we observe an enhancement of the electrical properties accompanied by an increased segregation of the phosphorous donors, resulting in a slight broadening of the delta-layer. We demonstrate that a step-flow growth achieved at 530 C provides the best compromise between high crystal quality and minimal dopant redistribution, with an electron mobility ~ 128 cm^2/Vs at a carrier density 1.3x10^14 cm-2, and a 4.2 K phase coherence length of ~ 180 nm.
Phosphorus (P) in germanium (Ge) δ-doped layers are fabricated in ultrahigh vacuum by adsorption ... more Phosphorus (P) in germanium (Ge) δ-doped layers are fabricated in ultrahigh vacuum by adsorption of phosphine molecules onto an atomically flat clean Ge(001) surface followed by thermal incorporation of P into the lattice and epitaxial Ge overgrowth by molecular beam epitaxy. Structural and electrical characterizations show that P atoms are confined, with minimal diffusion, into an ultranarrow 2-nm-wide layer with an electrically active sheet carrier concentration of 4×1013 cm-2 at 4.2 K. These results open up the possibility of ultranarrow source/drain regions with unprecedented carrier densities for Ge n-channel field effect transistors.
In this paper we demonstrate atomic-scale lithography on hydrogen terminated Ge(001). The lithogr... more In this paper we demonstrate atomic-scale lithography on hydrogen terminated Ge(001). The lithographic patterns were obtained by selectively desorbing hydrogen atoms from a H resist layer adsorbed on a clean, atomically flat Ge(001) surface with a scanning tunneling microscope tip operating in ultra-high vacuum. The influence of the tip-to-sample bias on the lithographic process have been investigated. Lithographic patterns with feature-sizes from 200 to 1.8 nm have been achieved by varying the tip-to-sample bias. These results open up the possibility of a scanning-probe lithography approach to the fabrication of future atomic-scale devices in germanium.
In this paper we demonstrate the fabrication of multiple, narrow, and closely spaced δ-doped P la... more In this paper we demonstrate the fabrication of multiple, narrow, and closely spaced δ-doped P layers in Ge. The P profiles are obtained by repeated phosphine adsorption onto atomically flat Ge(001) surfaces and subsequent thermal incorporation of P into the lattice. A dual-temperature epitaxial Ge overgrowth separates the layers, minimizing dopant redistribution and guaranteeing an atomically flat starting surface for each doping cycle. This technique allows P atomic layer doping in Ge and can be scaled up to an arbitrary number of doped layers maintaining atomic level control of the interface. Low sheet resistivities (280 \Omega /\square ) and high carrier densities (2 × 1014 cm - 2, corresponding to 7.4 × 1019 cm - 3) are demonstrated at 4.2 K.
We have developed a method to integrate a low thermal budget silicon dioxide dielectric in ultrah... more We have developed a method to integrate a low thermal budget silicon dioxide dielectric in ultrahigh vacuum to surface gate an in-plane gated phosphorus donor quantum dot in silicon. By combining in-plane and top-gate action, the resistance of the quantum dot tunnel barriers can be tuned to change the dot from open to closed where clear Coulomb blockade of the electron transport has been observed at 4 K. Additionally the scanning tunneling microscopy patterned in-plane gates can be used to independently tune the electron number on the dot. This enhanced tunability of donor based quantum dots bodes well for the fabrication of single donor architectures.
Physica E-low-dimensional Systems & Nanostructures, 2008
We study the low temperature electrical characteristics of planar, highly phosphorus-doped nanodo... more We study the low temperature electrical characteristics of planar, highly phosphorus-doped nanodots. The dots are defined by lithographically patterning an atomically flat, hydrogenated Si(100):H surface using a scanning-tunneling-microscope (STM), phosphorus δ-doping and low temperature molecular beam epitaxy in an ultra-high vacuum environment. Ohmic contacts and a surface gate structure are aligned ex-situ using electron beam lithography. We present electrical transport
In this paper we demonstrate atomic-scale lithography on hydrogen terminated Ge(001. The lithogra... more In this paper we demonstrate atomic-scale lithography on hydrogen terminated Ge(001. The lithographic patterns were obtained by selectively desorbing hydrogen atoms from a H resist layer adsorbed on a clean, atomically flat Ge(001) surface with a scanning tunneling microscope tip operating in ultra-high vacuum. The influence of the tip-to-sample bias on the lithographic process have been investigated. Lithographic patterns with feature-sizes from 200 nm to 1.8 nm have been achieved by varying the tip-to-sample bias. These results open up the possibility of a scanning-probe lithography approach to the fabrication of future atomic-scale devices in germanium.
An important driving force behind the microelectronics industry is the ability to pack ever more ... more An important driving force behind the microelectronics industry is the ability to pack ever more features onto a silicon chip, by continually miniaturising the individual components. However, after 2015 there is no known technological route to reduce devices below 10 nm. We demonstrate a complete fabrication strategy towards atomic-scale device fabrication in silicon using phosphorus as a dopant in combination with scanning probe lithography and high purity, low temperature crystal growth. A major advantage of this strategy is the ability to investigate the role of dopant placement and atomically controlled growth on electronic device operation.
Page 1. IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 2, MARCH 2007 213 Electrical Characteriz... more Page 1. IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 2, MARCH 2007 213 Electrical Characterization of Ordered Si:P Dopant Arrays Wilson Pok, Thilo CG Reusch, Giordano Scappucci, Frank J. Rueß, Alex R. Hamilton, and Michelle Y. Simmons ...
We demonstrate the preparation of a clean Ge(001) surface with minimal roughness (RMS ~ 0.6 Å), l... more We demonstrate the preparation of a clean Ge(001) surface with minimal roughness (RMS ~ 0.6 Å), low defect densities (~0.2% ML) and wide mono-atomic terraces (~80-100 nm). We use an ex situ wet chemical process combined with an in situ anneal treatment followed by a homoepitaxial buffer layer grown by molecular beam epitaxy and a subsequent final thermal anneal. Using scanning tunneling microscopy, we investigate the effect on the surface morphology of using different chemical reagents, concentrations as well as substrate temperature during growth. Such a high quality Ge(001) surface enables the formation of defect-free H-terminated Ge surfaces for subsequent patterning of atomic-scale devices by scanning tunneling lithography. We have achieved atomic-scale dangling bond wire structures 1.6 nm wide and 40 nm long as well as large, micron-size patterns with clear contrast of lithography in STM images.
Page 1. IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 2, MARCH 2007 213 Electrical Characteriz... more Page 1. IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 2, MARCH 2007 213 Electrical Characterization of Ordered Si:P Dopant Arrays Wilson Pok, Thilo CG Reusch, Giordano Scappucci, Frank J. Rueß, Alex R. Hamilton, and Michelle Y. Simmons ...
We present an ultrahigh vacuum technique for depositing SiO2 at room temperature using an atomic ... more We present an ultrahigh vacuum technique for depositing SiO2 at room temperature using an atomic oxygen source and Si coevaporation for ultimate use as a dielectric for gating Si devices with atomically precise dopant profiles. The resulting SiO2 layers were characterized in situ by scanning tunneling microscopy, ex situ by transmission electron microscopy and ellipsometry and integrated as the gate dielectric in a metal oxide semiconductor field effect transistor (MOSFET). The electrical characteristics of the MOSFETs were investigated at 4.2K, giving an interface trap density of ˜1011cm-2 from conductance and Hall effect measurements.
Low field magnetotransport revealing signatures of ballistic transport effects in strained Si/SiG... more Low field magnetotransport revealing signatures of ballistic transport effects in strained Si/SiGe cavities is investigated. We fabricated strained Si/SiGe cavities by confining a high mobility Si/SiGe 2DEG in a bended nanowire geometry defined by electron-beam lithography and reactive ion etching. The main features observed in the low temperature magnetoresistance curves are the presence of a zero-field magnetoresistance peak and of an oscillatory structure at low fields. By adopting a simple geometrical model we explain the oscillatory structure in terms of electron magnetic focusing. A detailed examination of the zero-field peak lineshape clearly shows deviations from the predictions of ballistic weak localization theory.
We report on the electrical transport of wire-based devices fabricated on modulation-doped Si/SiG... more We report on the electrical transport of wire-based devices fabricated on modulation-doped Si/SiGe two-dimensional electron gas. Two different geometries were investigated: straight and bended wires. In both cases, we found typical features of Coulomb blockade regime. Nevertheless, single electron transistor effects were found only on wires with bends. Reported data suggest that the insertion of bends is a suitable tool
We fabricated strongly confined Schottky-gated quantum point contacts by etching Si/SiGe heterost... more We fabricated strongly confined Schottky-gated quantum point contacts by etching Si/SiGe heterostructures and observed intriguing conductance quantization in units of approximately 1e2/h. Non-linear conductance measurements were performed depleting the quantum point contacts at fixed mode-energy separation. We report evidences of the formation of a half 1e2/h plateau, supporting the speculation that adiabatic transmission occurs through 1D modes with complete removal of valley and spin degeneracies.
We report the characterization of a single-electron transistor based on bended wires fabricated o... more We report the characterization of a single-electron transistor based on bended wires fabricated on modulation-doped SiGe two-dimensional electron gas. Electrical measurements show a diamond-shaped stability plot and a nonperiodic sequence of conductance peaks. The device behavior suggests the presence of disorder-induced multiple islands along the wire. Conductance oscillations remain well pronounced above liquid helium temperature.
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