The major portion of total power consumption in the integrated device is leakage power dissipatio... more The major portion of total power consumption in the integrated device is leakage power dissipation and is expected to grow exponentially in the next decade as per the International Technology Roadmap For Semiconductor(ITRS).In CMOS circuit, reduction of threshold voltage due to voltage scaling leads to increase in subthreshold leakage current and hence static power dissipation. Some leakage current reduction technique like Sleep Approach, Stack Approach, Lekage Feedback Approach, ZigZag Approach, Sleeper Keeper technique, Force Stack Technique and here we use proposed novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. The main advantage as compared to other techniques which involves the sleep transistor is that LECTOR technique does not require any additional control and monitoring circuitry, thereby limits the area increase and also the power dissipation in active state. Along wi...
In this paper, An ALU design and implementing using different foundries like 50nm, 70nm, 90nm and... more In this paper, An ALU design and implementing using different foundries like 50nm, 70nm, 90nm and 120nm. The performance of developed ALU analyzing and comparing in terms of area and power. The schematic of ALU circuit designing using DSCH 3.5 and its equivalent layout creating using Microwind tool.
In this paper we present high speed 8-bit Carry Skip Adder (CSA) compared with Ripple Carry Adder... more In this paper we present high speed 8-bit Carry Skip Adder (CSA) compared with Ripple Carry Adder (RAC) and conventional Carry Skip Adder (CSA). This is more efficient in terms of power consumption, area usage and speed. Instead to make multiplexer logic, the propose architecture made of AND-OR-Inverter (AIO) combination gate for carry skip adder. The propose architecture are evaluated by comparing their speed, power and area with those of other address using 180nm, 90nm and 45nm static CMOS technology.
as the size of ic's is becoming small, day by day the demand of high density vlsi circuits has be... more as the size of ic's is becoming small, day by day the demand of high density vlsi circuits has been increasing .the supply voltage reduction is necessary to reduce the active power. By lowering the supply voltage it is effective ways to suppress the energy consumption because reducing the supply voltage could reduce the dynamic power and leakage power respectively. In this paper, a technique called cluster technique has been proposed to reduce the active power requirement and the simulation has been done on 8x1 sram cell. In this work firstly the power dissipation of all the cells are connected to an without sleep is taken out then sleep transistor shared with two cells and after that all the four cells are connected to only sleep. Leakage reduction techniques for cmos based transistor level design and the techniques have been proposed like leakage lector technique transistor stack based low leakage approach, sleeper keeper technique for leakage reduction, multiple threshold transistor design technique, gated-clock based low power design etc. Various proposed techniques provide benefits with respect to specific design application. Therefore, result with cluster technique improved result than an individual sleep when connected to the sram cell. In this paper, sram cell without sleep transistor dissipates more power during different states as compared to sram cell with an individual transistor.asthe conventional design is simulated on different cmos fabrication technology using microwind tool. I. INTRODUCTION As with every generation of technology, the demand of handling the large amount of data in embedded memory has been increasing. To fulfill the requirement handling large data feature size of transistor is continuously reducing. With respect to high transistor density the problem of power consumption is becoming prominent issue to tackle. Static Random Access Memory is the first choice of designing semiconductor embedded memories because of low power dissipation. The low power feature for on chip SRAMs is becoming more important especially for battery operated portable applications .It is however one of the most significant challenges of high density VLSI circuit .The main aim of this paper is to estimate the effect of clustering technique on 6T SRAM cell and to investigate transistor sizing of the 6T SRAM cell for optimum power and delay. In this work , an average power dissipation of 6T SRAM Cell has been compared with SRAM cell using cluster technique.The cluster technique reduces the power dissipation of 6T SRAM cell in read, write , and hold operation .
As the size of IC's is becoming small, day by day the demand of high density VLSI circuits has be... more As the size of IC's is becoming small, day by day the demand of high density VLSI circuits has been increasing .The supply voltage reduction is necessary to reduce the active power. By lowering the supply voltage it is effective ways to suppress the energy consumption because reducing the supply voltage could reduce the dynamic power and leakage power respectively. In this paper, a technique called cluster technique has been proposed to reduce the active power requirement and the simulation has been done on 4X1 SRAM cell. In this work firstly the the power dissipation of all the cells are connected to an without sleep is taken out then sleep transistor shared with two cells and after that all the four cells are connected to only sleep. Leakage reduction techniques for CMOS based transistor level design and the techniques have been proposed like leakage lector technique transistor stack based low leakage approach , sleeper keeper technique for leakage reduction, Multiple Threshold Transistor Design Technique, Gated-Clock based low power design etc. Various proposed techniques provide benefits with respect to specific design application. Therefore, result with cluster technique improved result than an individual sleep when connected to the SRAM cell. In this paper, SRAM cell without sleep transistor dissipates more power during different states as compared to SRAM cell with an individual transistor. The conventional design is simulated on 90 nm CMOS fabrication technology using Microwind Tool.
The IEEE 802.22 WRAN is the first standard which is based on the cognitive radio network. WRAN ba... more The IEEE 802.22 WRAN is the first standard which is based on the cognitive radio network. WRAN basically uses unused or white spaces within the television bands between 54 and 862 MHz, especially within rural areas where usage may be lower. One of the major challenges for WRAN is how to efficiently schedule both the spectrum sensing and data transmission simultaneously. This problem for signal transmission is termed as coexistence. In this paper we give an overview of WRAN and discuss some techniques to reduce coexistence.
Patch Antenna is now very famous due to its compact size, good gain and. antenna is Rectangular M... more Patch Antenna is now very famous due to its compact size, good gain and. antenna is Rectangular Microstrip Patch Antenna(RMPA),basic property of the antenna like simulated design, Return loss, directivity, VSWR has been discussed ,but in this paper bandwidth of the antenna is very high, Satellite Communication there is a need of very compact antenna ,This paper presents the designs of Compact C-band antenna for communication at 4GHz,Radiation Pattern and bandwidth, vswr are discussed. The work shows that whenever we increase cut width from 14mm to 16mm its VSWR continuously decreases and reached about up to 1.00 and losses in 16mm cut width antenna reduces up to 100.972% that is very great achievement in Microstrip patch antenna for satellite communication.
Antennas is the essential part of the wireless communications. Most of them are Microstrip Patch ... more Antennas is the essential part of the wireless communications. Most of them are Microstrip Patch Antennas, Monopole antenna, and Folded Dipole Antennas. Each antenna is good in their own properties and usage. It can be said that antennas are the backbone and almost everything in the wireless communication without which the one cannot imagine wireless communication. This paper presents the designs of Rectangular microstrip patch antenna for 5.8 GHz communication. One of the antennas is Rectangular Microstrip Patch Antenna (RMPA) and Second Rectangular Microstrip Patch Antenna with defect ground structure. Basic property of both the antenna like simulated design, Return loss, directivity, Radiation Pattern and bandwidth are discussed. This work shows that bandwidth of Antenna in RMPA with DGS is increased about 39.57% which is great deal in antenna designing system, return losses of designed antenna is also decreased by 25.923%, gain and directivity of the proposed antenna is almost same. Rectangular Microstrip Patch Antenna with DGS also reduces the size of antenna which is always a basic need of Patch antenna design system.
The integrated circuits that have memories, a major share of total circuit power is required by t... more The integrated circuits that have memories, a major share of total circuit power is required by the memory architecture of the circuit. With the day-to-day changing circuit designs, the need to store increasing amount of processing data has resulted in the growing memory size in an integrated circuit. Most of the memory data remains un-altered during the memory data handling operation. The stored data is thus affected by the sub-threshold leakage power / current that leads to the degradation of data signal quality. The data integrity is maintained using a feedback path / architecture in SRAM memory architecture. Still, the amount of power loss due to leakage contributes a major part of the total power loss of the integrated circuit. This loss increases with the decrease in the physical feature size of the component / transistors. A low power system offers the benefits like device portability, long battery life, good performance criteria, etc. Today‘s increasing data handling require more random access memory to process the dynamic data and hence more power. Various SRAM architectures and its Design techniques are proposed in previous work. SRAM low power design using Sleepy Stack Transistor for is proposed by S.Lakshmi Narayan et al [1]. Dynamic Threshold and Stand-by Voltage leakage reduction technique is presented by Yashwant Singh and D. Boolchandani in [2].Power reduction using Power Gating is shown by AdreaCalimera et al [3]. Static Power Reduction Techniques for Asynchronous circuits is given by Carlos Ortega, Jonathan Tse and RajitManohar in [4]. These are some suggested techniques that can offer a solution towards low power in the design of SRAM architecture.In the present work, we have used leakage control transistor technique called LECTOR to modify the design of SRAM architecture to reduce the leakage current and hence the leakage power. The absence of requirement of control circuit for the operation of leakage control transistor in this technique is the major advantage of LECTOR technique over the other available leakage current reduction techniques. The proposed design is simulated on 90nm CMOS fabrication technology using Microwind Tool.
The major portion of total power consumption in the integrated device is leakage power dissipatio... more The major portion of total power consumption in the integrated device is leakage power dissipation and is expected to grow exponentially in the next decade as per the International Technology Roadmap For Semiconductor(ITRS).In CMOS circuit, reduction of threshold voltage due to voltage scaling leads to increase in subthreshold leakage current and hence static power dissipation. Some leakage current reduction technique like Sleep Approach, Stack Approach, Lekage Feedback Approach, ZigZag Approach, Sleeper Keeper technique, Force Stack Technique and here we use proposed novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. The main advantage as compared to other techniques which involves the sleep transistor is that LECTOR technique does not require any additional control and monitoring circuitry, thereby limits the area increase and also the power dissipation in active state. Along wi...
In this paper, An ALU design and implementing using different foundries like 50nm, 70nm, 90nm and... more In this paper, An ALU design and implementing using different foundries like 50nm, 70nm, 90nm and 120nm. The performance of developed ALU analyzing and comparing in terms of area and power. The schematic of ALU circuit designing using DSCH 3.5 and its equivalent layout creating using Microwind tool.
In this paper we present high speed 8-bit Carry Skip Adder (CSA) compared with Ripple Carry Adder... more In this paper we present high speed 8-bit Carry Skip Adder (CSA) compared with Ripple Carry Adder (RAC) and conventional Carry Skip Adder (CSA). This is more efficient in terms of power consumption, area usage and speed. Instead to make multiplexer logic, the propose architecture made of AND-OR-Inverter (AIO) combination gate for carry skip adder. The propose architecture are evaluated by comparing their speed, power and area with those of other address using 180nm, 90nm and 45nm static CMOS technology.
as the size of ic's is becoming small, day by day the demand of high density vlsi circuits has be... more as the size of ic's is becoming small, day by day the demand of high density vlsi circuits has been increasing .the supply voltage reduction is necessary to reduce the active power. By lowering the supply voltage it is effective ways to suppress the energy consumption because reducing the supply voltage could reduce the dynamic power and leakage power respectively. In this paper, a technique called cluster technique has been proposed to reduce the active power requirement and the simulation has been done on 8x1 sram cell. In this work firstly the power dissipation of all the cells are connected to an without sleep is taken out then sleep transistor shared with two cells and after that all the four cells are connected to only sleep. Leakage reduction techniques for cmos based transistor level design and the techniques have been proposed like leakage lector technique transistor stack based low leakage approach, sleeper keeper technique for leakage reduction, multiple threshold transistor design technique, gated-clock based low power design etc. Various proposed techniques provide benefits with respect to specific design application. Therefore, result with cluster technique improved result than an individual sleep when connected to the sram cell. In this paper, sram cell without sleep transistor dissipates more power during different states as compared to sram cell with an individual transistor.asthe conventional design is simulated on different cmos fabrication technology using microwind tool. I. INTRODUCTION As with every generation of technology, the demand of handling the large amount of data in embedded memory has been increasing. To fulfill the requirement handling large data feature size of transistor is continuously reducing. With respect to high transistor density the problem of power consumption is becoming prominent issue to tackle. Static Random Access Memory is the first choice of designing semiconductor embedded memories because of low power dissipation. The low power feature for on chip SRAMs is becoming more important especially for battery operated portable applications .It is however one of the most significant challenges of high density VLSI circuit .The main aim of this paper is to estimate the effect of clustering technique on 6T SRAM cell and to investigate transistor sizing of the 6T SRAM cell for optimum power and delay. In this work , an average power dissipation of 6T SRAM Cell has been compared with SRAM cell using cluster technique.The cluster technique reduces the power dissipation of 6T SRAM cell in read, write , and hold operation .
As the size of IC's is becoming small, day by day the demand of high density VLSI circuits has be... more As the size of IC's is becoming small, day by day the demand of high density VLSI circuits has been increasing .The supply voltage reduction is necessary to reduce the active power. By lowering the supply voltage it is effective ways to suppress the energy consumption because reducing the supply voltage could reduce the dynamic power and leakage power respectively. In this paper, a technique called cluster technique has been proposed to reduce the active power requirement and the simulation has been done on 4X1 SRAM cell. In this work firstly the the power dissipation of all the cells are connected to an without sleep is taken out then sleep transistor shared with two cells and after that all the four cells are connected to only sleep. Leakage reduction techniques for CMOS based transistor level design and the techniques have been proposed like leakage lector technique transistor stack based low leakage approach , sleeper keeper technique for leakage reduction, Multiple Threshold Transistor Design Technique, Gated-Clock based low power design etc. Various proposed techniques provide benefits with respect to specific design application. Therefore, result with cluster technique improved result than an individual sleep when connected to the SRAM cell. In this paper, SRAM cell without sleep transistor dissipates more power during different states as compared to SRAM cell with an individual transistor. The conventional design is simulated on 90 nm CMOS fabrication technology using Microwind Tool.
The IEEE 802.22 WRAN is the first standard which is based on the cognitive radio network. WRAN ba... more The IEEE 802.22 WRAN is the first standard which is based on the cognitive radio network. WRAN basically uses unused or white spaces within the television bands between 54 and 862 MHz, especially within rural areas where usage may be lower. One of the major challenges for WRAN is how to efficiently schedule both the spectrum sensing and data transmission simultaneously. This problem for signal transmission is termed as coexistence. In this paper we give an overview of WRAN and discuss some techniques to reduce coexistence.
Patch Antenna is now very famous due to its compact size, good gain and. antenna is Rectangular M... more Patch Antenna is now very famous due to its compact size, good gain and. antenna is Rectangular Microstrip Patch Antenna(RMPA),basic property of the antenna like simulated design, Return loss, directivity, VSWR has been discussed ,but in this paper bandwidth of the antenna is very high, Satellite Communication there is a need of very compact antenna ,This paper presents the designs of Compact C-band antenna for communication at 4GHz,Radiation Pattern and bandwidth, vswr are discussed. The work shows that whenever we increase cut width from 14mm to 16mm its VSWR continuously decreases and reached about up to 1.00 and losses in 16mm cut width antenna reduces up to 100.972% that is very great achievement in Microstrip patch antenna for satellite communication.
Antennas is the essential part of the wireless communications. Most of them are Microstrip Patch ... more Antennas is the essential part of the wireless communications. Most of them are Microstrip Patch Antennas, Monopole antenna, and Folded Dipole Antennas. Each antenna is good in their own properties and usage. It can be said that antennas are the backbone and almost everything in the wireless communication without which the one cannot imagine wireless communication. This paper presents the designs of Rectangular microstrip patch antenna for 5.8 GHz communication. One of the antennas is Rectangular Microstrip Patch Antenna (RMPA) and Second Rectangular Microstrip Patch Antenna with defect ground structure. Basic property of both the antenna like simulated design, Return loss, directivity, Radiation Pattern and bandwidth are discussed. This work shows that bandwidth of Antenna in RMPA with DGS is increased about 39.57% which is great deal in antenna designing system, return losses of designed antenna is also decreased by 25.923%, gain and directivity of the proposed antenna is almost same. Rectangular Microstrip Patch Antenna with DGS also reduces the size of antenna which is always a basic need of Patch antenna design system.
The integrated circuits that have memories, a major share of total circuit power is required by t... more The integrated circuits that have memories, a major share of total circuit power is required by the memory architecture of the circuit. With the day-to-day changing circuit designs, the need to store increasing amount of processing data has resulted in the growing memory size in an integrated circuit. Most of the memory data remains un-altered during the memory data handling operation. The stored data is thus affected by the sub-threshold leakage power / current that leads to the degradation of data signal quality. The data integrity is maintained using a feedback path / architecture in SRAM memory architecture. Still, the amount of power loss due to leakage contributes a major part of the total power loss of the integrated circuit. This loss increases with the decrease in the physical feature size of the component / transistors. A low power system offers the benefits like device portability, long battery life, good performance criteria, etc. Today‘s increasing data handling require more random access memory to process the dynamic data and hence more power. Various SRAM architectures and its Design techniques are proposed in previous work. SRAM low power design using Sleepy Stack Transistor for is proposed by S.Lakshmi Narayan et al [1]. Dynamic Threshold and Stand-by Voltage leakage reduction technique is presented by Yashwant Singh and D. Boolchandani in [2].Power reduction using Power Gating is shown by AdreaCalimera et al [3]. Static Power Reduction Techniques for Asynchronous circuits is given by Carlos Ortega, Jonathan Tse and RajitManohar in [4]. These are some suggested techniques that can offer a solution towards low power in the design of SRAM architecture.In the present work, we have used leakage control transistor technique called LECTOR to modify the design of SRAM architecture to reduce the leakage current and hence the leakage power. The absence of requirement of control circuit for the operation of leakage control transistor in this technique is the major advantage of LECTOR technique over the other available leakage current reduction techniques. The proposed design is simulated on 90nm CMOS fabrication technology using Microwind Tool.
Uploads
Papers