Statistical phase noise analysis and measurements are presented for a population of RF CMOS VCOs.... more Statistical phase noise analysis and measurements are presented for a population of RF CMOS VCOs. The measured mean values for phase noise at 1 kHz and 1 MHz offset frequencies are -46 dBc/Hz and -130 dBc/Hz respectively. However a large variation from the mean (+/-3 dBc/Hz) is observed for the close-in phase noise. This variation is attributed to the upconverted
2019 IEEE MTT-S International Microwave and RF Conference (IMARC)
A 6 GHz CMOS low-noise amplifier (LNA) with very low noise-figure (NF) of 0.92 dB is reported in ... more A 6 GHz CMOS low-noise amplifier (LNA) with very low noise-figure (NF) of 0.92 dB is reported in this paper. An inductively degenerated cascode topology is used for the LNA. The common source device is a floating body transistor for higher unity gain cut-off frequency and lower NFmin while the common gate device is a body contacted device with higher self gain. High resistivity (HR) silicon-on-insulator (SOI) technology renders higher quality factor (Q) values for inductors which results in reduced NF. The prototype LNA is fabricated (Fig. 1) and characterized using a 180 nm RF-SOI CMOS technology. Measurements show 15.9 dB of gain, 0.92 dB of NF, -1.1 dBm of input third-order intercept point (IIP3) for the LNA, with 12 mW dc power consumption.
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)
In this paper, significant improvement in cascode LNA performance is demonstrated by using a new ... more In this paper, significant improvement in cascode LNA performance is demonstrated by using a new high self gain (HSG) common gate (CG) transistor. Emphasis has been on making the output conductance $g_{ds}$ lower and flatter with drain bias. A prototype cascode LNA is designed and fabricated using the developed HSG device in state-of-the-art 0.13 RF SOI technology. Thanks to the HSG device, more than +5 dBm input inter-modulation product (IIP3) improvement is seen in measurements. Very high gain of 19.5 dB at 2.5 GHz with IIP3 value of +1.5 dBm are seen in measurements. Due to optimized transistor sizing, the designed LNA operates at low power of 6.25 mW where 5.2 mA of current is drawn from 1.2 V supply. With integrated high quality factor inductors on high resistivity SOI substrate, the LNA also demonstrates very low noise figure of 0.85 dB. Furthermore, excellent correlation between model simulations and measurements is demonstrated.
2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)
Over the last few decades, SiGe BiCMOS has survived the continued onslaught of RF-CMOS technologi... more Over the last few decades, SiGe BiCMOS has survived the continued onslaught of RF-CMOS technologies. SiGe HBT invented in late 1980's and later introduced as a BiCMOS technology served as a sweet spot in the emerging RF market, thanks to the SiGe HBT's higher power and better noise characteristics. It did not take very long for RFCMOS scaling roadmap to catch up to SiGe HBT performance levels and displace it from high-volume market segment like RF cellular transceivers. Now with the advent of 5G millimeter-wave (mmWave) applications demanding higher power and lower noise for the front-end, will SiGe BiCMOS once again come back to the forefront to address this market? In this paper we will take a closer look at some of the key aspects of a 130 / 90nm SiGe BiCMOS relative to a 28nm bulk RFCMOS technology for addressing mmWave front-end as well as potential opportunities that lie ahead with scaling.
This paper describes 0.18um CMOS silicon-on-insulator (SOI) technology and design techniques for ... more This paper describes 0.18um CMOS silicon-on-insulator (SOI) technology and design techniques for SOI RF switch designs for wireless applications. The measured results of SP4T (single pole four throw) and SP8T (single pole eight throw) switch reference designs are presented. It has been demonstrated that SOI RF switch performance, in terms of power handling, linearity, insertion loss and isolation, is very competitive with those utilizing GaAs pHEMT and silicon-on-sapphire (SOS) technologies, while maintaining a cost and manufacturing advantage.
2015 IEEE 15th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2015
Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology fo... more Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology for RF switches in RF front end modules for cell phones and WiFi. RF SOI technologies were created from silicon processes originally used for high speed logic applications, but the technology was modified to meet the performance needs of RF switches. The RF SOI technologies have been improved to follow the evolving system requirements for insertion loss, isolation, voltage tolerance, linearity, integration and cost. In this paper, the performance results of the latest generations of RF SOI switch technologies from IBM are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also discussed.
Proceedings International Test Conference 2001 (Cat. No.01CH37260), 2001
A robust RF board design methodology is critical to containing costs, maintaining schedules and p... more A robust RF board design methodology is critical to containing costs, maintaining schedules and providing RF IC customers' adequate RF test coverage in high volume production for a test development organization. In this paper, a new, robust methodology is described to allow an organization to consistently generate high quality RF test hardware solutions, which will work the first time. This
2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2011
Abstract The 4 th generation wireless standard is ushering an era of ubiquitous connectivity. The... more Abstract The 4 th generation wireless standard is ushering an era of ubiquitous connectivity. The convergence of data and voice to a portable media device is producing an explosive demand for high data rate communication. Such convergence requirements along with the ...
2009 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2009
This paper describes a 180 nm CMOS thin film SOI technology developed for RF switch applications.... more This paper describes a 180 nm CMOS thin film SOI technology developed for RF switch applications. For the first time we show that the well-known harmonic generation issue in HRES SOI technologies can be suppressed with one additional mask. Power handling, linearity, and Ron*Coff product are competitive with GaAs pHEMT and silicon-on-sapphire technologies.
2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2014
IBM first qualified a 0.35μm generation 1000 Ω-cm high resistivity substrate (HiRES) SiGe BiCMOS ... more IBM first qualified a 0.35μm generation 1000 Ω-cm high resistivity substrate (HiRES) SiGe BiCMOS technology in 2011. This technology was optimized for WiFi and cellular NPN power amplifier (PA), NPN low noise amplifier (LNA), and isolated CMOS NFET switch rf front-end-IC (FEIC) integration. It includes an optional through silicon via used as a low inductance ground path for NPN emitters. Data for 50 Ω-cm, 1st generation HiRES, and 2nd generation HiRES NPN PA, LNA, and CMOS NFET switch devices are reviewed.
2013 IEEE 10th International Conference on ASIC, 2013
ABSTRACT Silicon technologies have continued to usurp other exotic technologies, such as GaAs and... more ABSTRACT Silicon technologies have continued to usurp other exotic technologies, such as GaAs and Silicon-on-Sapphire (SOS), from the RF wireless communication system to provide a more cost-effective integration path. The integration of RF front-end (RFFE) electronics is a good example of this trend. RFFE components such as, transmit-receive switch, antenna tuners, low-noise amplifiers, and power amplifiers, are being integrated wherever possible. In this paper we discuss the high-resistivity silicon-on-insulator (HR-SOI) technology as a cost effective solution for the RFFE integration in a wireless mobile communication system.
The following paper describes a method to characterize wafer probes using a 3D EM simulator. Rath... more The following paper describes a method to characterize wafer probes using a 3D EM simulator. Rather than following the traditional method of building a custom test fixture for different probe setups and measuring the S-parameters, this 3D EM characterization method yields multi-port S-parameters of a specific probe structure by utilizing simulations. For a standard characterization, the S-parameters can be a
2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014
In this paper, we introduce an isolated RF LDMOS NFET is for RF Power Amplifier (PA) and power ma... more In this paper, we introduce an isolated RF LDMOS NFET is for RF Power Amplifier (PA) and power management applications. The RF LDMOS NFET has demonstrated a drain-source turn-on resistance (Rds,on) of 1.45ohm-mm, a cutoff frequency (Ft) greater than 40GHz and a drain-source breakdown down voltage (BV) in excess of 9V. For PA designs, the isolation layer is floating to reduce the parasitic and achieve high PAE/nonlinearity performance. RF power amplifier cores were fabricated and measured at 2.4GHz and 5.8GHz to demonstrate the RF LDMOS performance in PAs. Under CW loadpull and 3.3V supply, 18dB and 12dB gains (Gt) are achieved at 2.4GHz and 5.8GHz respectively, with 1dB compression point power density at 22dBm/mm gate width, and PAE > 63%, maximum PAE > 70%. Due to good model to hardware Pout correlation in a 5.8GHz PA cell, a fully matched PA last stage with the load-pull fundamental and harmonic impedances showed a less than 4° AM-PM phase distortion, meeting the 802.11n spectral mask requirement with 20MHz 64QAM modulated signal at 19dBm Pout.
Statistical phase noise analysis and measurements are presented for a population of RF CMOS VCOs.... more Statistical phase noise analysis and measurements are presented for a population of RF CMOS VCOs. The measured mean values for phase noise at 1 kHz and 1 MHz offset frequencies are -46 dBc/Hz and -130 dBc/Hz respectively. However a large variation from the mean (+/-3 dBc/Hz) is observed for the close-in phase noise. This variation is attributed to the upconverted
2019 IEEE MTT-S International Microwave and RF Conference (IMARC)
A 6 GHz CMOS low-noise amplifier (LNA) with very low noise-figure (NF) of 0.92 dB is reported in ... more A 6 GHz CMOS low-noise amplifier (LNA) with very low noise-figure (NF) of 0.92 dB is reported in this paper. An inductively degenerated cascode topology is used for the LNA. The common source device is a floating body transistor for higher unity gain cut-off frequency and lower NFmin while the common gate device is a body contacted device with higher self gain. High resistivity (HR) silicon-on-insulator (SOI) technology renders higher quality factor (Q) values for inductors which results in reduced NF. The prototype LNA is fabricated (Fig. 1) and characterized using a 180 nm RF-SOI CMOS technology. Measurements show 15.9 dB of gain, 0.92 dB of NF, -1.1 dBm of input third-order intercept point (IIP3) for the LNA, with 12 mW dc power consumption.
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)
In this paper, significant improvement in cascode LNA performance is demonstrated by using a new ... more In this paper, significant improvement in cascode LNA performance is demonstrated by using a new high self gain (HSG) common gate (CG) transistor. Emphasis has been on making the output conductance $g_{ds}$ lower and flatter with drain bias. A prototype cascode LNA is designed and fabricated using the developed HSG device in state-of-the-art 0.13 RF SOI technology. Thanks to the HSG device, more than +5 dBm input inter-modulation product (IIP3) improvement is seen in measurements. Very high gain of 19.5 dB at 2.5 GHz with IIP3 value of +1.5 dBm are seen in measurements. Due to optimized transistor sizing, the designed LNA operates at low power of 6.25 mW where 5.2 mA of current is drawn from 1.2 V supply. With integrated high quality factor inductors on high resistivity SOI substrate, the LNA also demonstrates very low noise figure of 0.85 dB. Furthermore, excellent correlation between model simulations and measurements is demonstrated.
2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)
Over the last few decades, SiGe BiCMOS has survived the continued onslaught of RF-CMOS technologi... more Over the last few decades, SiGe BiCMOS has survived the continued onslaught of RF-CMOS technologies. SiGe HBT invented in late 1980's and later introduced as a BiCMOS technology served as a sweet spot in the emerging RF market, thanks to the SiGe HBT's higher power and better noise characteristics. It did not take very long for RFCMOS scaling roadmap to catch up to SiGe HBT performance levels and displace it from high-volume market segment like RF cellular transceivers. Now with the advent of 5G millimeter-wave (mmWave) applications demanding higher power and lower noise for the front-end, will SiGe BiCMOS once again come back to the forefront to address this market? In this paper we will take a closer look at some of the key aspects of a 130 / 90nm SiGe BiCMOS relative to a 28nm bulk RFCMOS technology for addressing mmWave front-end as well as potential opportunities that lie ahead with scaling.
This paper describes 0.18um CMOS silicon-on-insulator (SOI) technology and design techniques for ... more This paper describes 0.18um CMOS silicon-on-insulator (SOI) technology and design techniques for SOI RF switch designs for wireless applications. The measured results of SP4T (single pole four throw) and SP8T (single pole eight throw) switch reference designs are presented. It has been demonstrated that SOI RF switch performance, in terms of power handling, linearity, insertion loss and isolation, is very competitive with those utilizing GaAs pHEMT and silicon-on-sapphire (SOS) technologies, while maintaining a cost and manufacturing advantage.
2015 IEEE 15th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2015
Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology fo... more Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology for RF switches in RF front end modules for cell phones and WiFi. RF SOI technologies were created from silicon processes originally used for high speed logic applications, but the technology was modified to meet the performance needs of RF switches. The RF SOI technologies have been improved to follow the evolving system requirements for insertion loss, isolation, voltage tolerance, linearity, integration and cost. In this paper, the performance results of the latest generations of RF SOI switch technologies from IBM are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also discussed.
Proceedings International Test Conference 2001 (Cat. No.01CH37260), 2001
A robust RF board design methodology is critical to containing costs, maintaining schedules and p... more A robust RF board design methodology is critical to containing costs, maintaining schedules and providing RF IC customers' adequate RF test coverage in high volume production for a test development organization. In this paper, a new, robust methodology is described to allow an organization to consistently generate high quality RF test hardware solutions, which will work the first time. This
2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2011
Abstract The 4 th generation wireless standard is ushering an era of ubiquitous connectivity. The... more Abstract The 4 th generation wireless standard is ushering an era of ubiquitous connectivity. The convergence of data and voice to a portable media device is producing an explosive demand for high data rate communication. Such convergence requirements along with the ...
2009 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2009
This paper describes a 180 nm CMOS thin film SOI technology developed for RF switch applications.... more This paper describes a 180 nm CMOS thin film SOI technology developed for RF switch applications. For the first time we show that the well-known harmonic generation issue in HRES SOI technologies can be suppressed with one additional mask. Power handling, linearity, and Ron*Coff product are competitive with GaAs pHEMT and silicon-on-sapphire technologies.
2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2014
IBM first qualified a 0.35μm generation 1000 Ω-cm high resistivity substrate (HiRES) SiGe BiCMOS ... more IBM first qualified a 0.35μm generation 1000 Ω-cm high resistivity substrate (HiRES) SiGe BiCMOS technology in 2011. This technology was optimized for WiFi and cellular NPN power amplifier (PA), NPN low noise amplifier (LNA), and isolated CMOS NFET switch rf front-end-IC (FEIC) integration. It includes an optional through silicon via used as a low inductance ground path for NPN emitters. Data for 50 Ω-cm, 1st generation HiRES, and 2nd generation HiRES NPN PA, LNA, and CMOS NFET switch devices are reviewed.
2013 IEEE 10th International Conference on ASIC, 2013
ABSTRACT Silicon technologies have continued to usurp other exotic technologies, such as GaAs and... more ABSTRACT Silicon technologies have continued to usurp other exotic technologies, such as GaAs and Silicon-on-Sapphire (SOS), from the RF wireless communication system to provide a more cost-effective integration path. The integration of RF front-end (RFFE) electronics is a good example of this trend. RFFE components such as, transmit-receive switch, antenna tuners, low-noise amplifiers, and power amplifiers, are being integrated wherever possible. In this paper we discuss the high-resistivity silicon-on-insulator (HR-SOI) technology as a cost effective solution for the RFFE integration in a wireless mobile communication system.
The following paper describes a method to characterize wafer probes using a 3D EM simulator. Rath... more The following paper describes a method to characterize wafer probes using a 3D EM simulator. Rather than following the traditional method of building a custom test fixture for different probe setups and measuring the S-parameters, this 3D EM characterization method yields multi-port S-parameters of a specific probe structure by utilizing simulations. For a standard characterization, the S-parameters can be a
2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014
In this paper, we introduce an isolated RF LDMOS NFET is for RF Power Amplifier (PA) and power ma... more In this paper, we introduce an isolated RF LDMOS NFET is for RF Power Amplifier (PA) and power management applications. The RF LDMOS NFET has demonstrated a drain-source turn-on resistance (Rds,on) of 1.45ohm-mm, a cutoff frequency (Ft) greater than 40GHz and a drain-source breakdown down voltage (BV) in excess of 9V. For PA designs, the isolation layer is floating to reduce the parasitic and achieve high PAE/nonlinearity performance. RF power amplifier cores were fabricated and measured at 2.4GHz and 5.8GHz to demonstrate the RF LDMOS performance in PAs. Under CW loadpull and 3.3V supply, 18dB and 12dB gains (Gt) are achieved at 2.4GHz and 5.8GHz respectively, with 1dB compression point power density at 22dBm/mm gate width, and PAE > 63%, maximum PAE > 70%. Due to good model to hardware Pout correlation in a 5.8GHz PA cell, a fully matched PA last stage with the load-pull fundamental and harmonic impedances showed a less than 4° AM-PM phase distortion, meeting the 802.11n spectral mask requirement with 20MHz 64QAM modulated signal at 19dBm Pout.
Uploads
Papers