2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
Carry out an electronic device/circuit at the scale of few nanometers usually implies a high leve... more Carry out an electronic device/circuit at the scale of few nanometers usually implies a high level of uncertainty due to device variability along the fabrication process. In fact, hybrid SET-FET circuit can be extremely delicate in front of parasitic elements, due to the low level of current provided by the SET device. So, in this contribution and study of their influence is done. Moreover, the suitability to implement this circuit by using FinFET SOI is observed, as well.
The need for design of new computing and storage paradigms has leaded to the emergence of new tec... more The need for design of new computing and storage paradigms has leaded to the emergence of new technologies and procedures. Among these technologies, emerging non-volatile memories such as RRAMs are getting intense attention due to their attractive characteristics such as scalability and CMOS friendly manufacturing. However, similar to any other new technology emergences, having reliability and high performance devices is a challenge, and innovative new techniques are required to make the products attractive and robust enough before entering into the semiconductor market. The research for such crucial reliability concerns and mitigation techniques are ongoing hot topic and the main motivation for this work. Therefore, in this paper, we have studied the origins of RRAM variability and reviewed some of the existing techniques to mitigate its effect at circuit level. To show the relevance of variability in RRAM memories we have further analyzed its impact in the Read/Write memory operation and have presented the memory unreliability that we measure by a parameter as probability of error can be 25% during the read operation and in presence of such resistance variations. In the next phase we have presented a conventional 1T1R memory architecture where we have proposed our reconfiguring strategies to extend the memory lifetime. These reconfiguration strategies utilize a monitoring technique, what we have implemented in order to measure the resistance ratios in RRAM memory cells. Such monitoring approach can detect the highly variability effected and differentiate the bad cells from the good cells; therefore, it can improve the overall RRAM memory reliability.Peer ReviewedPostprint (author's final draft
2018 Spanish Conference on Electron Devices (CDE), 2018
In this work, an electrical study of a vertical nanowire (NW)-based Field Effect Transistor (FET)... more In this work, an electrical study of a vertical nanowire (NW)-based Field Effect Transistor (FET) is presented. The resulting output current from the modelled NW-FET is optimized in terms of multiple parameters, in order to enhance the behavior at subthreshold regime. Variability tolerance is analyzed as well, in order to attain improvements concerning average device performance and stability. A process simulation model for a NW-FET is built in perspective for its further manufacturability and implementation into hybrid SET-FET circuits.
IEEE International Reliability Physics Symposium Proceedings, 2013
ABSTRACT In this work, the gate stack electrical properties of fresh and channel-hot-carrier (CHC... more ABSTRACT In this work, the gate stack electrical properties of fresh and channel-hot-carrier (CHC) stressed MOSFETs have been investigated at the nanoscale with a Conductive Atomic Force Microscope (CAFM). For the first time, by measuring on the bare oxide, the CAFM has allowed evaluation of the degradation induced along the channel by a previous CHC stress. In particular, higher gate leakage was measured close to source and drain, which has been related to NBTI and CHC degradation, respectively.
IEEE Transactions on Device and Materials Reliability, 2013
ABSTRACT In this paper, the 3T1D-DRAM cell based on FinFET devices is studied as an alternative t... more ABSTRACT In this paper, the 3T1D-DRAM cell based on FinFET devices is studied as an alternative to the bulk one. We observe an improvement in its behavior when IG and SG FinFETs are properly mixed, since together they provide a relevant increase in the memory circuit retention time. Moreover, our FinFET cell shows larger variability robustness, better performance at low supply voltage, and higher tolerance to elevated temperatures.
The scaling roadmap for realization of more than Moore in semiconductor industry has resulted in ... more The scaling roadmap for realization of more than Moore in semiconductor industry has resulted in emergence of new types of devices, among them, memristive devices seem to be a promising candidate to be applied in various applications such as in memories and neuromorphic chips. However memristive devices face some challenges to be resolved before becoming a mainstream. This paper work analyzes two of the main reliability concerns in design of memristive memories, and proposes circuit solution to enhance the reliability. Keywords—Memritor; reliability; process variability; endurance; crossbar; RRAM; reconfiguration; emerging device.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013, 2013
In this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs... more In this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs) has been carried out in front of some different reliability scenarios (variability and soft errors). The logic circuits based on FinFET devices have presented the best overall behavior, since we have obtained the best performance and variability robustness. Meanwhile, the III-V/Ge-based circuits have shown the best electrical masking in front of soft errors disturbances.
Memristors are considered one of the most favorable emerging device alternatives for future memor... more Memristors are considered one of the most favorable emerging device alternatives for future memory technologies. They are attracting great attention recently, due to their high scalability and compatibility with CMOS fabrication process. Alongside their benefits, they also face reliability concerns (e.g. manufacturing variability). In this sense our work analyzes key sources of uncertainties in the operation of the memristive memory and we present an analytic approach to predict the expected lifetime distribution of a memristive crossbar.
This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedd... more This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10nm FinFET devices. The use of individual transistor resizing in order to achieve better cell performance (i.e. retention time, access time, and energy consumption) at the sub-VT operating level is studied. In this scenario, asymmetrically resizing the memory cell, since we modify the channel length of the write access transistor and the width of the rest of the devices in the eDRAM cell, entails a 3.5x increase in retention time as compared to the nominal case and with smaller area overhead. Moreover, such a resizing significantly improves reliability against variability and soft errors (50% and 1.9x, respectively) when the cells are operated at sub-VT level.
2018 Conference on Design of Circuits and Integrated Systems (DCIS), 2018
Hybrid SET-FET circuits are candidates to extend the SET usefulness for low power circuits and wi... more Hybrid SET-FET circuits are candidates to extend the SET usefulness for low power circuits and with high integration density. The location of quantum dot (QD) of the SET is usually expected at the centre of the tunneling barrier, but out this ideality the QD may not be precisely located. For this, to analyse the impact of the QD location variation will be of high interest to predict the hybrid circuit behaviour.
2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
Carry out an electronic device/circuit at the scale of few nanometers usually implies a high leve... more Carry out an electronic device/circuit at the scale of few nanometers usually implies a high level of uncertainty due to device variability along the fabrication process. In fact, hybrid SET-FET circuit can be extremely delicate in front of parasitic elements, due to the low level of current provided by the SET device. So, in this contribution and study of their influence is done. Moreover, the suitability to implement this circuit by using FinFET SOI is observed, as well.
The need for design of new computing and storage paradigms has leaded to the emergence of new tec... more The need for design of new computing and storage paradigms has leaded to the emergence of new technologies and procedures. Among these technologies, emerging non-volatile memories such as RRAMs are getting intense attention due to their attractive characteristics such as scalability and CMOS friendly manufacturing. However, similar to any other new technology emergences, having reliability and high performance devices is a challenge, and innovative new techniques are required to make the products attractive and robust enough before entering into the semiconductor market. The research for such crucial reliability concerns and mitigation techniques are ongoing hot topic and the main motivation for this work. Therefore, in this paper, we have studied the origins of RRAM variability and reviewed some of the existing techniques to mitigate its effect at circuit level. To show the relevance of variability in RRAM memories we have further analyzed its impact in the Read/Write memory operation and have presented the memory unreliability that we measure by a parameter as probability of error can be 25% during the read operation and in presence of such resistance variations. In the next phase we have presented a conventional 1T1R memory architecture where we have proposed our reconfiguring strategies to extend the memory lifetime. These reconfiguration strategies utilize a monitoring technique, what we have implemented in order to measure the resistance ratios in RRAM memory cells. Such monitoring approach can detect the highly variability effected and differentiate the bad cells from the good cells; therefore, it can improve the overall RRAM memory reliability.Peer ReviewedPostprint (author's final draft
2018 Spanish Conference on Electron Devices (CDE), 2018
In this work, an electrical study of a vertical nanowire (NW)-based Field Effect Transistor (FET)... more In this work, an electrical study of a vertical nanowire (NW)-based Field Effect Transistor (FET) is presented. The resulting output current from the modelled NW-FET is optimized in terms of multiple parameters, in order to enhance the behavior at subthreshold regime. Variability tolerance is analyzed as well, in order to attain improvements concerning average device performance and stability. A process simulation model for a NW-FET is built in perspective for its further manufacturability and implementation into hybrid SET-FET circuits.
IEEE International Reliability Physics Symposium Proceedings, 2013
ABSTRACT In this work, the gate stack electrical properties of fresh and channel-hot-carrier (CHC... more ABSTRACT In this work, the gate stack electrical properties of fresh and channel-hot-carrier (CHC) stressed MOSFETs have been investigated at the nanoscale with a Conductive Atomic Force Microscope (CAFM). For the first time, by measuring on the bare oxide, the CAFM has allowed evaluation of the degradation induced along the channel by a previous CHC stress. In particular, higher gate leakage was measured close to source and drain, which has been related to NBTI and CHC degradation, respectively.
IEEE Transactions on Device and Materials Reliability, 2013
ABSTRACT In this paper, the 3T1D-DRAM cell based on FinFET devices is studied as an alternative t... more ABSTRACT In this paper, the 3T1D-DRAM cell based on FinFET devices is studied as an alternative to the bulk one. We observe an improvement in its behavior when IG and SG FinFETs are properly mixed, since together they provide a relevant increase in the memory circuit retention time. Moreover, our FinFET cell shows larger variability robustness, better performance at low supply voltage, and higher tolerance to elevated temperatures.
The scaling roadmap for realization of more than Moore in semiconductor industry has resulted in ... more The scaling roadmap for realization of more than Moore in semiconductor industry has resulted in emergence of new types of devices, among them, memristive devices seem to be a promising candidate to be applied in various applications such as in memories and neuromorphic chips. However memristive devices face some challenges to be resolved before becoming a mainstream. This paper work analyzes two of the main reliability concerns in design of memristive memories, and proposes circuit solution to enhance the reliability. Keywords—Memritor; reliability; process variability; endurance; crossbar; RRAM; reconfiguration; emerging device.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013, 2013
In this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs... more In this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs) has been carried out in front of some different reliability scenarios (variability and soft errors). The logic circuits based on FinFET devices have presented the best overall behavior, since we have obtained the best performance and variability robustness. Meanwhile, the III-V/Ge-based circuits have shown the best electrical masking in front of soft errors disturbances.
Memristors are considered one of the most favorable emerging device alternatives for future memor... more Memristors are considered one of the most favorable emerging device alternatives for future memory technologies. They are attracting great attention recently, due to their high scalability and compatibility with CMOS fabrication process. Alongside their benefits, they also face reliability concerns (e.g. manufacturing variability). In this sense our work analyzes key sources of uncertainties in the operation of the memristive memory and we present an analytic approach to predict the expected lifetime distribution of a memristive crossbar.
This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedd... more This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10nm FinFET devices. The use of individual transistor resizing in order to achieve better cell performance (i.e. retention time, access time, and energy consumption) at the sub-VT operating level is studied. In this scenario, asymmetrically resizing the memory cell, since we modify the channel length of the write access transistor and the width of the rest of the devices in the eDRAM cell, entails a 3.5x increase in retention time as compared to the nominal case and with smaller area overhead. Moreover, such a resizing significantly improves reliability against variability and soft errors (50% and 1.9x, respectively) when the cells are operated at sub-VT level.
2018 Conference on Design of Circuits and Integrated Systems (DCIS), 2018
Hybrid SET-FET circuits are candidates to extend the SET usefulness for low power circuits and wi... more Hybrid SET-FET circuits are candidates to extend the SET usefulness for low power circuits and with high integration density. The location of quantum dot (QD) of the SET is usually expected at the centre of the tunneling barrier, but out this ideality the QD may not be precisely located. For this, to analyse the impact of the QD location variation will be of high interest to predict the hybrid circuit behaviour.
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Papers by Esteve Amat