2010 IEEE International SOI Conference (SOI), 2010
... Investigation of kink-induced excess RF channel noise in sub -50 nm PD-SOI MOSFETs Ninad S. W... more ... Investigation of kink-induced excess RF channel noise in sub -50 nm PD-SOI MOSFETs Ninad S. Wadje, Vijaya Bhaskara Neeli, RP Jindal, HM Nayfeh, and R. Todi University of Louisiana at Lafayette, Lafayette LA, IBM Semiconductor Research and Development Center ...
In this paper, we quantify the relation of low lateral electric field hole mobility and channel s... more In this paper, we quantify the relation of low lateral electric field hole mobility and channel strain to the virtual source velocity of nanoscale p-type SOI MOSFET devices with effective channel length from 35 to 50 nm and show strong correlation. The mobility is modified by the application of uniaxial compressive strain in the I GPa regime to the channel
... J. Hilliard, D. Andsager, L. Abu Hassan,a) Hasan M. Nayfeh,b) and MH Nayfeh Deparhnent of Phy... more ... J. Hilliard, D. Andsager, L. Abu Hassan,a) Hasan M. Nayfeh,b) and MH Nayfeh Deparhnent of Physics, University of Illinois at Urbana-Champaign ... As the reader will note, the luminescent material typi-cally is a measurable fraction, but not a majority of the total porous material for ...
Abstract We investigate the single-event transient (SET) response of T-body and notched-body cont... more Abstract We investigate the single-event transient (SET) response of T-body and notched-body contacted MOSFETs from a commercial 45 nm SOI RF-CMOS technology. Although body-contacted devices suffer from reduced RF performance compared to floating body ...
The hot carrier and ionizing radiation responses of 45-nm SOI RF nMOSFETs are investigated. Devic... more The hot carrier and ionizing radiation responses of 45-nm SOI RF nMOSFETs are investigated. Devices with “tight” source/drain (S/D) contact spacing have improved RF performance but degraded hot carrier reliability and radiation tolerance. Devices with “loose” gate finger-to-gate finger spacing have improved RF performance and also improved hot carrier and radiation tolerance. The effects of finger width on the hot carrier stress and ionizing radiation degradation of strained silicon-on-insulator RF MOSFETs are also investigated. Enhanced degradation is observed for devices with wide finger widths and is attributed to the greater channel-region mechanical stress induced impact ionization. This result is contrary to the previous studies which showed that narrow channel width devices should exhibit greater damage. Taken together, these results have serious consequences for RF circuits that require large widths for sufficient RF gain. Finally, devices with symmetric halo doping are observed to exhibit greater total-dose degradation than devices with asymmetric halo doping.
... Gate workhction engineering is an attractive approach to achieve desired off-current in strai... more ... Gate workhction engineering is an attractive approach to achieve desired off-current in strained Si MOSFETs with sub-25-nm gate lengths, particularly in cases where the V, difference 6om unstrained Si devices is larger ... (I) H. M. Nayfeh, C. W. Leitz, A. 1. Piterq J. L. Hoyt, and D ...
... group, both past and present members including: Dr. Mark Armstrong, Dr. Anthony Lochtefeld, D... more ... group, both past and present members including: Dr. Mark Armstrong, Dr. Anthony Lochtefeld, Dr. Keith Jackson, Dr. Andy Wei, Dr. Ihsan Djomehri, Ali ... I would like to thank Ammar Nayfeh, Ph.D. student from Stanford for exciting discussions on the future of silicon microelectronic ...
2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2008
▪ Longitudinal compressive stress in the GPa regime is required for the 45nm SOI high-performance... more ▪ Longitudinal compressive stress in the GPa regime is required for the 45nm SOI high-performance pFET device to meet aggressive performance goals. ▪ Compressive stress liner, and eSiGe stressor enhancement was employed in order to achieve a 1.6 GPa channel stress level. ▪ Mobility enhancement of the 45nm baseline device is shown to be 4X-fold higher than relaxed-Si. Effective piezo-cofficients extracted for wide range of stress highlighting 3 stress regimes. Stress and drive current are shown to be correlated with a coefficient equal to ∼ 0.25. ▪ Low-field mobility is shown to be strongly correlated to injection velocity. High strain pFET devices with gate length down to 35nm operate at about 60% of the thermal limit. ▪ Challenge for future technology nodes- the mobility vs stress relationship for channel stress levels in the 1.6GPa regime is approaching saturation. To continue this incredible rate of performance increase (17%/year), methods of increasing the low-field mobility through increased thermal velocity is required.
In this paper, nFET-to-pFET (n-to-p) tracking characteristics in 14-nm silicon-on-insulator (SOI)... more In this paper, nFET-to-pFET (n-to-p) tracking characteristics in 14-nm silicon-on-insulator (SOI) FinFET technology are studied by technology computer-aided design-based statistical modeling. Compared with planar SOI high-k metal gate CMOS technologies, 14-nm SOI FinFET technology shows better n-to-p tracking mainly due to the strong influence of correlated Fin geometrical variation, as well as reduced uncorrelated variation from an innovative work function process. The impact of the n-to-p tracking characteristics on setup and hold (guard time) of latch circuits is evaluated by corner and Monte Carlo simulation using compact models. It is found that the guard time is significantly modulated by slow/fast and fast/slow corners in certain conditions and, therefore should be considered in guard time design.
2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008
If not yield optimized, embedded SiGe (eSiGe) processes with aggressive transistor performance en... more If not yield optimized, embedded SiGe (eSiGe) processes with aggressive transistor performance enhancements could induce high SRAM standby current and single cell failures in SRAM. In order to optimize the yield of eSiGe process, a SRAM-layout-based test structure was identified. It has the advantage of being able to be tested after silicidation or first metal level, therefore can be used
2010 IEEE International SOI Conference (SOI), 2010
... Investigation of kink-induced excess RF channel noise in sub -50 nm PD-SOI MOSFETs Ninad S. W... more ... Investigation of kink-induced excess RF channel noise in sub -50 nm PD-SOI MOSFETs Ninad S. Wadje, Vijaya Bhaskara Neeli, RP Jindal, HM Nayfeh, and R. Todi University of Louisiana at Lafayette, Lafayette LA, IBM Semiconductor Research and Development Center ...
In this paper, we quantify the relation of low lateral electric field hole mobility and channel s... more In this paper, we quantify the relation of low lateral electric field hole mobility and channel strain to the virtual source velocity of nanoscale p-type SOI MOSFET devices with effective channel length from 35 to 50 nm and show strong correlation. The mobility is modified by the application of uniaxial compressive strain in the I GPa regime to the channel
... J. Hilliard, D. Andsager, L. Abu Hassan,a) Hasan M. Nayfeh,b) and MH Nayfeh Deparhnent of Phy... more ... J. Hilliard, D. Andsager, L. Abu Hassan,a) Hasan M. Nayfeh,b) and MH Nayfeh Deparhnent of Physics, University of Illinois at Urbana-Champaign ... As the reader will note, the luminescent material typi-cally is a measurable fraction, but not a majority of the total porous material for ...
Abstract We investigate the single-event transient (SET) response of T-body and notched-body cont... more Abstract We investigate the single-event transient (SET) response of T-body and notched-body contacted MOSFETs from a commercial 45 nm SOI RF-CMOS technology. Although body-contacted devices suffer from reduced RF performance compared to floating body ...
The hot carrier and ionizing radiation responses of 45-nm SOI RF nMOSFETs are investigated. Devic... more The hot carrier and ionizing radiation responses of 45-nm SOI RF nMOSFETs are investigated. Devices with “tight” source/drain (S/D) contact spacing have improved RF performance but degraded hot carrier reliability and radiation tolerance. Devices with “loose” gate finger-to-gate finger spacing have improved RF performance and also improved hot carrier and radiation tolerance. The effects of finger width on the hot carrier stress and ionizing radiation degradation of strained silicon-on-insulator RF MOSFETs are also investigated. Enhanced degradation is observed for devices with wide finger widths and is attributed to the greater channel-region mechanical stress induced impact ionization. This result is contrary to the previous studies which showed that narrow channel width devices should exhibit greater damage. Taken together, these results have serious consequences for RF circuits that require large widths for sufficient RF gain. Finally, devices with symmetric halo doping are observed to exhibit greater total-dose degradation than devices with asymmetric halo doping.
... Gate workhction engineering is an attractive approach to achieve desired off-current in strai... more ... Gate workhction engineering is an attractive approach to achieve desired off-current in strained Si MOSFETs with sub-25-nm gate lengths, particularly in cases where the V, difference 6om unstrained Si devices is larger ... (I) H. M. Nayfeh, C. W. Leitz, A. 1. Piterq J. L. Hoyt, and D ...
... group, both past and present members including: Dr. Mark Armstrong, Dr. Anthony Lochtefeld, D... more ... group, both past and present members including: Dr. Mark Armstrong, Dr. Anthony Lochtefeld, Dr. Keith Jackson, Dr. Andy Wei, Dr. Ihsan Djomehri, Ali ... I would like to thank Ammar Nayfeh, Ph.D. student from Stanford for exciting discussions on the future of silicon microelectronic ...
2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2008
▪ Longitudinal compressive stress in the GPa regime is required for the 45nm SOI high-performance... more ▪ Longitudinal compressive stress in the GPa regime is required for the 45nm SOI high-performance pFET device to meet aggressive performance goals. ▪ Compressive stress liner, and eSiGe stressor enhancement was employed in order to achieve a 1.6 GPa channel stress level. ▪ Mobility enhancement of the 45nm baseline device is shown to be 4X-fold higher than relaxed-Si. Effective piezo-cofficients extracted for wide range of stress highlighting 3 stress regimes. Stress and drive current are shown to be correlated with a coefficient equal to ∼ 0.25. ▪ Low-field mobility is shown to be strongly correlated to injection velocity. High strain pFET devices with gate length down to 35nm operate at about 60% of the thermal limit. ▪ Challenge for future technology nodes- the mobility vs stress relationship for channel stress levels in the 1.6GPa regime is approaching saturation. To continue this incredible rate of performance increase (17%/year), methods of increasing the low-field mobility through increased thermal velocity is required.
In this paper, nFET-to-pFET (n-to-p) tracking characteristics in 14-nm silicon-on-insulator (SOI)... more In this paper, nFET-to-pFET (n-to-p) tracking characteristics in 14-nm silicon-on-insulator (SOI) FinFET technology are studied by technology computer-aided design-based statistical modeling. Compared with planar SOI high-k metal gate CMOS technologies, 14-nm SOI FinFET technology shows better n-to-p tracking mainly due to the strong influence of correlated Fin geometrical variation, as well as reduced uncorrelated variation from an innovative work function process. The impact of the n-to-p tracking characteristics on setup and hold (guard time) of latch circuits is evaluated by corner and Monte Carlo simulation using compact models. It is found that the guard time is significantly modulated by slow/fast and fast/slow corners in certain conditions and, therefore should be considered in guard time design.
2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008
If not yield optimized, embedded SiGe (eSiGe) processes with aggressive transistor performance en... more If not yield optimized, embedded SiGe (eSiGe) processes with aggressive transistor performance enhancements could induce high SRAM standby current and single cell failures in SRAM. In order to optimize the yield of eSiGe process, a SRAM-layout-based test structure was identified. It has the advantage of being able to be tested after silicidation or first metal level, therefore can be used
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