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42: Ensure that vectors are reported correctly in stackmaps. r=ltratt a=vext01 Co-authored-by: Edd Barrett <vext01@gmail.com>
2 parents a0fb4e0 + 72842cf commit 0276ef1

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3 files changed

+343
-10
lines changed

3 files changed

+343
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lines changed

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 30 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -9288,6 +9288,34 @@ void SelectionDAGBuilder::populateCallLoweringInfo(
92889288
Call->countOperandBundlesOfType(LLVMContext::OB_preallocated) != 0);
92899289
}
92909290

9291+
/// Given the stackmap live variable `N`, search its sub-DAG and return all of
9292+
/// the constituent values that need to be reported in the stackmap table.
9293+
static std::vector<SDValue> findLiveConstituents(SelectionDAG &DAG,
9294+
const SDValue &N) {
9295+
std::vector<SDValue> V;
9296+
9297+
switch (N.getOpcode()) {
9298+
case ISD::BUILD_PAIR:
9299+
case ISD::CONCAT_VECTORS:
9300+
case ISD::MERGE_VALUES:
9301+
case ISD::BUILD_VECTOR:
9302+
for (SDValue Op : N->op_values())
9303+
V.push_back(Op);
9304+
break;
9305+
case ISD::INSERT_VECTOR_ELT: {
9306+
V = findLiveConstituents(DAG, N.getOperand(0));
9307+
unsigned Idx =
9308+
cast<ConstantSDNode>(N.getOperand(2).getNode())->getZExtValue();
9309+
V[Idx] = N.getOperand(1);
9310+
break;
9311+
}
9312+
default:
9313+
V.push_back(N);
9314+
}
9315+
9316+
return V;
9317+
}
9318+
92919319
/// Add a stack map intrinsic call's live variable operands to a stackmap
92929320
/// or patchpoint target node's operand list.
92939321
///
@@ -9320,12 +9348,8 @@ static void addStackMapLiveVars(const CallBase &Call, unsigned StartIdx,
93209348
Ops.push_back(DAG.getTargetFrameIndex(FI->getIndex(), Op.getValueType()));
93219349
} else {
93229350
// Otherwise emit a target independent node to be legalised.
9323-
if (Op.getOpcode() == ISD::MERGE_VALUES) {
9324-
for (unsigned J = 0; J < Op.getNumOperands(); J++)
9325-
Ops.push_back(Op.getOperand(J));
9326-
} else {
9327-
Ops.push_back(Op);
9328-
}
9351+
for (SDValue &V : findLiveConstituents(DAG, Op))
9352+
Ops.push_back(V);
93299353
}
93309354
Ops.push_back(DAG.getTargetConstant(StackMaps::NextLive, DL, MVT::i64));
93319355
}

‎llvm/test/CodeGen/X86/selectiondag-patchpoint-legalize.ll

Lines changed: 188 additions & 2 deletions
207
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929
; CHECK-NEXT: .long {{.*}}
3030
; CHECK-NEXT: .short {{.*}}
3131
; NumLiveVars
32-
; CHECK-NEXT: .short 11
32+
; CHECK-NEXT: .short 16
3333
; LiveVar[NumLiveVars]
3434
; LiveVar[0]
3535
; CHECK-NEXT: .byte 1
@@ -165,6 +165,184 @@
165165
; CHECK-NEXT: .short 0
166166
; CHECK-NEXT: .short 0
167167
; CHECK-NEXT: .long 0
168+
; LiveVars[11]
169+
; CHECK-NEXT: .byte 4
170+
; Locations[0]
171+
; CHECK-NEXT: .byte 4
172+
; CHECK-NEXT: .byte 0
173+
; CHECK-NEXT: .short 8
174+
; CHECK-NEXT: .short 0
175+
; CHECK-NEXT: .short 0
176+
; CHECK-NEXT: .long 0
177+
; Locations[1]
178+
; CHECK-NEXT: .byte 4
179+
; CHECK-NEXT: .byte 0
180+
; CHECK-NEXT: .short 8
181+
; CHECK-NEXT: .short 0
182+
; CHECK-NEXT: .short 0
183+
; CHECK-NEXT: .long 1
184+
; Locations[1]
185+
; CHECK-NEXT: .byte 4
186+
; CHECK-NEXT: .byte 0
187+
; CHECK-NEXT: .short 8
188+
; CHECK-NEXT: .short 0
189+
; CHECK-NEXT: .short 0
190+
; CHECK-NEXT: .long 2
191+
; Locations[1]
192+
; CHECK-NEXT: .byte 4
193+
; CHECK-NEXT: .byte 0
194+
; CHECK-NEXT: .short 8
195+
; CHECK-NEXT: .short 0
196+
; CHECK-NEXT: .short 0
197+
; CHECK-NEXT: .long 3
198+
; LiveVars[12]
199+
; CHECK-NEXT: .byte 4
200+
; Locations[0]
201+
; CHECK-NEXT: .byte 1
202+
; CHECK-NEXT: .byte 0
203+
; CHECK-NEXT: .short 4
204+
; CHECK-NEXT: .short {{.*}}
205+
; CHECK-NEXT: .short 0
206+
; CHECK-NEXT: .long 0
+
; Locations[1]
208+
; CHECK-NEXT: .byte 4
209+
; CHECK-NEXT: .byte 0
210+
; CHECK-NEXT: .short 8
211+
; CHECK-NEXT: .short 0
212+
; CHECK-NEXT: .short 0
213+
; CHECK-NEXT: .long 0
214+
; Locations[1]
215+
; CHECK-NEXT: .byte 4
216+
; CHECK-NEXT: .byte 0
217+
; CHECK-NEXT: .short 8
218+
; CHECK-NEXT: .short 0
219+
; CHECK-NEXT: .short 0
220+
; CHECK-NEXT: .long 0
221+
; Locations[1]
222+
; CHECK-NEXT: .byte 4
223+
; CHECK-NEXT: .byte 0
224+
; CHECK-NEXT: .short 8
225+
; CHECK-NEXT: .short 0
226+
; CHECK-NEXT: .short 0
227+
; CHECK-NEXT: .long 0
228+
; LiveVars[13]
229+
; CHECK-NEXT: .byte 4
230+
; Locations[0]
231+
; CHECK-NEXT: .byte 4
232+
; CHECK-NEXT: .byte 0
233+
; CHECK-NEXT: .short 8
234+
; CHECK-NEXT: .short 0
235+
; CHECK-NEXT: .short 0
236+
; CHECK-NEXT: .long 0
237+
; Locations[1]
238+
; CHECK-NEXT: .byte 1
239+
; CHECK-NEXT: .byte 0
240+
; CHECK-NEXT: .short 4
241+
; CHECK-NEXT: .short {{.*}}
242+
; CHECK-NEXT: .short 0
243+
; CHECK-NEXT: .long 0
244+
; Locations[2]
245+
; CHECK-NEXT: .byte 4
246+
; CHECK-NEXT: .byte 0
247+
; CHECK-NEXT: .short 8
248+
; CHECK-NEXT: .short 0
249+
; CHECK-NEXT: .short 0
250+
; CHECK-NEXT: .long 0
251+
; Locations[3]
252+
; CHECK-NEXT: .byte 4
253+
; CHECK-NEXT: .byte 0
254+
; CHECK-NEXT: .short 8
255+
; CHECK-NEXT: .short 0
256+
; CHECK-NEXT: .short 0
257+
; CHECK-NEXT: .long 0
258+
; LiveVars[14]
259+
; CHECK-NEXT: .byte 8
260+
; Locations[0]
261+
; CHECK-NEXT: .byte 4
262+
; CHECK-NEXT: .byte 0
263+
; CHECK-NEXT: .short 8
264+
; CHECK-NEXT: .short 0
265+
; CHECK-NEXT: .short 0
266+
; CHECK-NEXT: .long 0
267+
; Locations[1]
268+
; CHECK-NEXT: .byte 4
269+
; CHECK-NEXT: .byte 0
270+
; CHECK-NEXT: .short 8
271+
; CHECK-NEXT: .short 0
272+
; CHECK-NEXT: .short 0
273+
; CHECK-NEXT: .long 0
274+
; Locations[2]
275+
; CHECK-NEXT: .byte 4
276+
; CHECK-NEXT: .byte 0
277+
; CHECK-NEXT: .short 8
278+
; CHECK-NEXT: .short 0
279+
; CHECK-NEXT: .short 0
280+
; CHECK-NEXT: .long 0
281+
; Locations[3]
282+
; CHECK-NEXT: .byte 4
283+
; CHECK-NEXT: .byte 0
284+
; CHECK-NEXT: .short 8
285+
; CHECK-NEXT: .short 0
286+
; CHECK-NEXT: .short 0
287+
; CHECK-NEXT: .long 0
288+
; Locations[4]
289+
; CHECK-NEXT: .byte 4
290+
; CHECK-NEXT: .byte 0
291+
; CHECK-NEXT: .short 8
292+
; CHECK-NEXT: .short 0
293+
; CHECK-NEXT: .short 0
294+
; CHECK-NEXT: .long 0
295+
; Locations[5]
296+
; CHECK-NEXT: .byte 4
297+
; CHECK-NEXT: .byte 10000 0
298+
; CHECK-NEXT: .short 8
299+
; CHECK-NEXT: .short 0
300+
; CHECK-NEXT: .short 0
301+
; CHECK-NEXT: .long 0
302+
; Locations[6]
303+
; CHECK-NEXT: .byte 4
304+
; CHECK-NEXT: .byte 0
305+
; CHECK-NEXT: .short 8
306+
; CHECK-NEXT: .short 0
307+
; CHECK-NEXT: .short 0
308+
; CHECK-NEXT: .long 0
309+
; Locations[7]
310+
; CHECK-NEXT: .byte 1
311+
; CHECK-NEXT: .byte 0
312+
; CHECK-NEXT: .short 4
313+
; CHECK-NEXT: .short {{.*}}
314+
; CHECK-NEXT: .short 0
315+
; CHECK-NEXT: .long 0
316+
; LiveVars[14]
317+
; CHECK-NEXT: .byte 4
318+
; Locations[0]
319+
; CHECK-NEXT: .byte 4
320+
; CHECK-NEXT: .byte 0
321+
; CHECK-NEXT: .short 8
322+
; CHECK-NEXT: .short 0
323+
; CHECK-NEXT: .short 0
324+
; CHECK-NEXT: .long 0
325+
; Locations[1]
326+
; CHECK-NEXT: .byte 4
327+
; CHECK-NEXT: .byte 0
328+
; CHECK-NEXT: .short 8
329+
; CHECK-NEXT: .short 0
330+
; CHECK-NEXT: .short 0
331+
; CHECK-NEXT: .long 1
332+
; Locations[2]
333+
; CHECK-NEXT: .byte 4
334+
; CHECK-NEXT: .byte 0
335+
; CHECK-NEXT: .short 8
336+
; CHECK-NEXT: .short 0
337+
; CHECK-NEXT: .short 0
338+
; CHECK-NEXT: .long 2
339+
; Locations[3]
340+
; CHECK-NEXT: .byte 4
341+
; CHECK-NEXT: .byte 0
342+
; CHECK-NEXT: .short 8
343+
; CHECK-NEXT: .short 0
344+
; CHECK-NEXT: .short 0
345+
; CHECK-NEXT: .long 3
168346

169347
@p32 = external global i8 addrspace(270)*
170348

@@ -181,6 +359,9 @@ entry:
181359
%ptr32 = load i8 addrspace(270)*, i8 addrspace(270)** @p32
182360
%structreg1 = insertvalue %struct1 zeroinitializer, i32 %argc, 0
183361
%structreg2 = insertvalue %struct2 zeroinitializer, i1 %i1reg, 0
362+
%arrayreg = insertvalue [4 x i32] zeroinitializer, i32 %argc, 0
363+
%vec = insertelement <4 x i32> zeroinitializer, i32 %argc, i32 1
364+
%bigvec = insertelement <8 x i32> zeroinitializer, i32 %argc, i32 7
184365
call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(
185366
i64 0,
186367
i32 0,
@@ -206,6 +387,11 @@ entry:
206387
%struct1 zeroinitializer,
207388
%struct1 %structreg1,
208389
%struct2 zeroinitializer,
209-
%struct2 %structreg2)
390+
%struct2 %structreg2,
391+
[4 x i32] [i32 0, i32 1, i32 2, i32 3],
392+
[4 x i32] %arrayreg,
393+
<4 x i32> %vec,
394+
<8 x i32> %bigvec,
395+
<4 x i8> <i8 0, i8 1, i8 2, i8 3>)
210396
ret i32 0
211397
}

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