8000 Fix broken link in node on parameterized class typedef · Issue #5977 · verilator/verilator · GitHub
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Fix broken link in node on parameterized class typedef #5977

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solomatnikov opened this issue May 5, 2025 & 8000 middot; 5 comments
Open

Fix broken link in node on parameterized class typedef #5977

solomatnikov opened this issue May 5, 2025 · 5 comments
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area: parser Issue involves SystemVerilog parsing status: ready Issue is ready for someone to fix; then goes to 'status: assigned'

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@solomatnikov
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solomatnikov commented May 5, 2025 •
edited by wsnyder
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From https://github.com/pulp-platform/axi

package axi_test;
  class axi_ax_beat #(
    parameter AW = 32,
    parameter IW = 8 ,
    parameter UW = 1
  );
    rand logic [IW-1:0] ax_id     = '0;
    rand logic [AW-1:0] ax_addr   = '0;
    logic [7:0]         ax_len    = '0;
    logic [2:0]         ax_size   = '0;
    logic [1:0]         ax_burst  = '0;
    logic               ax_lock   = '0;
    logic [3:0]         ax_cache  = '0;
    logic [2:0]         ax_prot   = '0;
    rand logic [3:0]    ax_qos    = '0;
    logic [3:0]         ax_region = '0;
    logic [5:0]         ax_atop   = '0;  
    rand logic [UW-1:0] ax_user   = '0;
  endclass

  class axi_driver #(
    parameter int  AW = 32  ,
    parameter int  DW = 32  ,
    parameter int  IW = 8   ,
    parameter int  UW = 1   ,
    parameter time TA = 0ns ,  
    parameter time TT = 0ns    
  );
    typedef axi_ax_beat #(.AW(AW), .IW(IW), .UW(UW)) ax_beat_t;
  endclass
endpackage

module tb_axi_bus_compare #(
  parameter time TbTclk = 10ns,
  parameter int unsigned TbAddrWidth = 32'd64,
  parameter int unsigned TbDataWidth = 32'd128,
  parameter int unsigned TbIdWidth = 32'd6,
  parameter int unsigned TbUserWidth = 32'd2,
  parameter bit TbWarnUninitialized = 1'b0,
  parameter time TbApplDelay = 2ns,
  parameter time TbAcqDelay = 8ns
);

  typedef axi_test::axi_driver #(
    .AW(TbAddrWidth), .DW(TbDataWidth), .IW(TbIdWidth), .UW(TbUserWidth),
    .TA(1ns), .TT(6ns)
  ) drv_t;

  localparam int StrbWidth = 1;

  initial begin
    automatic logic rand_success;
    automatic drv_t::ax_beat_t aw_beat = new, ar_beat = new;

    rand_success = aw_beat.randomize(); assert (rand_success);
    aw_beat.ax_addr >>= $clog2(StrbWidth);  
    aw_beat.ax_addr <<= $clog2(StrbWidth);

     $finish();
  end
endmodule

VCS compiles w/o problem.

What 'verilator' command line do we use to run your example?

verilator --binary test.sv

What 'verilator --version' are you using? Did you try it with the git master version?

Verilator 5.037 devel rev v5.036-30-g11cfa61f8

What OS and distribution are you using?

Linux 5.14.0-503.38.1.el9_5.x86_64

May we assist you in trying to fix this in Verilator yourself?

(Please avoid attaching screenshots that show text - you can convert images to text using e.g. https://ocr.space)
@solomatnikov solomatnikov added the new New issue not seen by maintainers label May 5, 2025
@solomatnikov solomatnikov mentioned this issue May 5, 2025
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@wsnyder wsnyder added area: parser Issue involves SystemVerilog parsing status: ready Issue is ready for someone to fix; then goes to 'status: assigned' and removed new New issue not seen by maintainers labels May 5, 2025
@wsnyder
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wsnyder commented May 11, 2025

Blocked by #2412, which fix is being worked on, then needs additional fix.
8000

@solomatnikov
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solomatnikov commented May 15, 2025 •
edited
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@wsnyder thank you for working on this and #2412

@wsnyder wsnyder changed the title Incorrect "syntax error, unexpected IDENTIFIER, expecting IDENTIFIER-for-type" Fix broken link in node on parameterized class typedef May 20, 2025
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wsnyder commented May 20, 2025

No longer blocked by #2412. Issue is now that typedef which is of a parameterized class gets resolved before the class is parameterized. This is a workaround:

-    automatic drv_t::ax_beat_t aw_beat = new;
+    automatic Pkg::axi_driver #(.AW(TbAddrWidth)) aw_beat = new;

@solomatnikov
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Will this be fixed?

It would be hard for such "workaround" to get accepted/merged.

@wsnyder
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wsnyder commented May 21, 2025

Will you contribute a pull? More seriously, yes, eventually, but we have many issues, but not enough time ;)

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