Description
Hello, i'm trying to add in my simulation class that contains a virtual interface, but i don't want to use this class in current testbench (just `include).
Verilator throws error:
"%Error-UNSUPPORTED: ...: Unsupported: virtual interface never assigned any actual interface"
but actually i don't see any violation of systemverilog and same example runs in vivado
Example:
- interface.svh
interface my_interface;
logic signal;
modport master(
output signal
);
modport slave(
input signal
);
endinterface- bfm.svh
class bfm;
virtual my_interface.master master;
virtual my_interface.slave slave;
function new(
virtual my_interface.master master,
virtual my_interface.slave slave
);
this.master = master;
this.slave = slave;
endfunction
endclass
6780
- top.sv
`include "bfm.svh"
`include "interface.svh"
module top(input a, output b);
endmodule- run.sh
verilator --binary -j 0 --threads "$(nproc)" --Mdir build --top-module top top.svlog:
%Error-UNSUPPORTED: bfm.svh:2:10: Unsupported: virtual interface never assigned any actual interface
2 | virtual my_interface.master master;
| ^~~~~~~~~~~~
top.sv:2:1: ... note: In file included from 'top.sv'
... For error description see https://verilator.org/warn/UNSUPPORTED?v=5.033
%Error-UNSUPPORTED: bfm.svh:3:10: Unsupported: virtual interface never assigned any actual interface
3 | virtual my_interface.slave slave;
| ^~~~~~~~~~~~
top.sv:2:1: ... note: In file included from 'top.sv'
%Error-UNSUPPORTED: bfm.svh:6:11: Unsupported: virtual interface never assigned any actual interface
6 | virtual my_interface.master master,
| ^~~~~~~~~~~~
top.sv:2:1: ... note: In file included from 'top.sv'
%Error-UNSUPPORTED: bfm.svh:7:11: Unsupported: virtual interface never assigned any actual interface
7 | virtual my_interface.slave slave
| ^~~~~~~~~~~~
top.sv:2:1: ... note: In file included from 'top.sv'
%Error: Exiting due to 4 error(s)
... See the manual at https://verilator.org/verilator_doc.html for more assistance.
It marked as unsupported, but maybe i can bypass this error somehow
Thanks