8000 system(WL) update STM32WLxx HAL Drivers to v1.2.0 · stm32duino/Arduino_Core_STM32@e2b492d · GitHub
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system(WL) update STM32WLxx HAL Drivers to v1.2.0
Included in STM32CubeWL FW v1.2.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 9adabec commit e2b492d
  • stm32wlxx_hal_rtc_ex.h
  • stm32wlxx_hal_smartcard.h
  • stm32wlxx_hal_smartcard_ex.h
  • stm32wlxx_hal_smbus.h
  • stm32wlxx_hal_smbus_ex.h
  • stm32wlxx_hal_spi.h
  • stm32wlxx_hal_spi_ex.h
  • stm32wlxx_hal_subghz.h
  • stm32wlxx_hal_tim.h
  • stm32wlxx_hal_tim_ex.h
  • stm32wlxx_hal_uart.h
  • stm32wlxx_hal_uart_ex.h
  • stm32wlxx_hal_usart.h
  • stm32wlxx_hal_usart_ex.h
  • stm32wlxx_hal_wwdg.h
  • stm32wlxx_ll_adc.h
  • stm32wlxx_ll_bus.h
  • stm32wlxx_ll_comp.h
  • stm32wlxx_ll_cortex.h
  • stm32wlxx_ll_crc.h
  • stm32wlxx_ll_dac.h
  • stm32wlxx_ll_dma.h
  • stm32wlxx_ll_dmamux.h
  • stm32wlxx_ll_exti.h
  • stm32wlxx_ll_gpio.h
  • stm32wlxx_ll_hsem.h
  • stm32wlxx_ll_i2c.h
  • stm32wlxx_ll_ipcc.h
  • stm32wlxx_ll_iwdg.h
  • stm32wlxx_ll_lptim.h
  • stm32wlxx_ll_lpuart.h
  • stm32wlxx_ll_pka.h
  • stm32wlxx_ll_pwr.h
  • stm32wlxx_ll_rcc.h
  • stm32wlxx_ll_rng.h
  • stm32wlxx_ll_rtc.h
  • stm32wlxx_ll_spi.h
  • stm32wlxx_ll_system.h
  • stm32wlxx_ll_tim.h
  • stm32wlxx_ll_usart.h
  • stm32wlxx_ll_utils.h
  • stm32wlxx_ll_wwdg.h
  • License.md
  • README.md
  • Release_Notes.html
  • Src
  • STM32YYxx_HAL_Driver_version.md

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    158 files changed

    +3812
    -2995
    lines changed

    ‎system/Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

    Lines changed: 164 additions & 12 deletions

    Original file line numberDiff line numberDiff line change
    @@ -7,13 +7,12 @@
    77
    ******************************************************************************
    88
    * @attention
    99
    *
    10-
    * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
    11-
    * All rights reserved.</center></h2>
    10+
    * Copyright (c) 2021 STMicroelectronics.
    11+
    * All rights reserved.
    1212
    *
    13-
    * This software component is licensed by ST under BSD 3-Clause license,
    14-
    * the "License"; You may not use this file except in compliance with the
    15-
    * License. You may obtain a copy of the License at:
    16-
    * opensource.org/licenses/BSD-3-Clause
    13+
    * This software is licensed under terms that can be found in the LICENSE file
    14+
    * in the root directory of this software component.
    15+
    * If no LICENSE file comes with this software, it is provided AS-IS.
    1716
    *
    1817
    ******************************************************************************
    1918
    */
    @@ -105,6 +104,12 @@ extern "C" {
    105104
    #if defined(STM32H7)
    106105
    #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
    107106
    #endif /* STM32H7 */
    107+
    108+
    #if defined(STM32U5)
    109+
    #define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
    110+
    #define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
    111+
    #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
    112+
    #endif /* STM32U5 */
    108113
    /**
    109114
    * @}
    110115
    */
    @@ -214,18 +219,21 @@ extern "C" {
    214219
    * @{
    215220
    */
    216221
    #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
    222+
    #if defined(STM32U5)
    223+
    #define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
    224+
    #define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
    225+
    #define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
    226+
    #endif /* STM32U5 */
    217227
    /**
    218228
    * @}
    219229
    */
    220230

    221231
    /** @defgroup CRC_Aliases CRC API aliases
    222232
    * @{
    223233
    */
    224-
    #if defined(STM32WL) || defined(STM32WB) || defined(STM32L5) || defined(STM32L4)
    225-
    #else
    226234
    #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
    227235
    #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
    228-
    #endif
    236+
    229237
    /**
    230238
    * @}
    231239
    */
    @@ -260,6 +268,13 @@ extern "C" {
    260268
    #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
    261269
    #endif
    262270

    271+
    #if defined(STM32U5)
    272+
    #define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
    273+
    #define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
    274+
    #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
    275+
    #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
    276+
    #endif
    277+
    263278
    #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
    264279
    #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
    265280
    #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
    @@ -402,6 +417,10 @@ extern "C" {
    402417
    #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
    403418

    404419
    #endif /* STM32H7 */
    420+
    421+
    #if defined(STM32U5)
    422+
    #define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
    423+
    #endif /* STM32U5 */
    405424
    /**
    406425
    * @}
    407426
    */
    @@ -624,12 +643,12 @@ extern "C" {
    624643
    #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
    625644
    #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
    626645

    627-
    #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
    646+
    #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
    628647
    #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
    629648
    #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
    630649
    #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
    631650
    #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
    632-
    #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
    651+
    #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
    633652

    634653
    #if defined(STM32L1)
    635654
    #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
    @@ -645,6 +664,20 @@ extern "C" {
    645664
    #endif /* STM32F0 || STM32F3 || STM32F1 */
    646665

    647666
    #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
    667+
    668+
    #if defined(STM32U5)
    669+
    #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
    670+
    #endif /* STM32U5 */
    671+
    /**
    672+
    * @}
    673+
    */
    674+
    675+
    /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
    676+
    * @{
    677+
    */
    678+
    #if defined(STM32U5)
    679+
    #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
    680+
    #endif /* STM32U5 */
    648681
    /**
    649682
    * @}
    650683
    */
    @@ -882,9 +915,19 @@ extern "C" {
    882915
    #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
    883916
    #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
    884917

    918+
    919+
    /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
    920+
    * @{
    921+
    */
    922+
    #define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
    923+
    /**
    924+
    * @}
    925+
    */
    926+
    885927
    #if defined(STM32U5)
    886928
    #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
    887929
    #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
    930+
    #define LPTIM_CHANNEL_ALL 0x00000000U
    888931
    #endif /* STM32U5 */
    889932
    /**
    890933
    * @}
    @@ -1224,6 +1267,10 @@ extern "C" {
    12241267
    #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
    12251268
    #endif
    12261269

    1270+
    #if defined(STM32U5) || defined(STM32MP2)
    1271+
    #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
    1272+
    #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
    1273+
    #endif
    12271274
    /**
    12281275
    * @}
    12291276
    */
    @@ -1440,6 +1487,19 @@ extern "C" {
    14401487
    * @{
    14411488
    */
    14421489
    #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
    1490+
    /**
    1491+
    * @}
    1492+
    */
    1493+
    1494+
    /** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
    1495+
    * @{
    1496+
    */
    1497+
    1498+
    #if defined(STM32U5)
    1499+
    #define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
    1500+
    #define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
    1501+
    #endif /* STM32U5 */
    1502+
    14431503
    /**
    14441504
    * @}
    14451505
    */
    @@ -1641,6 +1701,80 @@ extern "C" {
    16411701

    16421702
    #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
    16431703

    1704+
    #if defined (STM32U5)
    1705+
    #define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
    1706+
    #define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
    1707+
    #define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
    1708+
    #define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
    1709+
    #define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
    1710+
    #define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
    1711+
    #define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
    1712+
    #define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
    1713+
    #define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
    1714+
    #define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
    1715+
    #define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
    1716+
    #define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
    1717+
    #define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
    1718+
    #define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
    1719+
    1720+
    #define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
    1721+
    #define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
    1722+
    #define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
    1723+
    1724+
    #define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
    1725+
    #define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
    1726+
    #define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
    1727+
    #define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
    1728+
    #define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
    1729+
    #define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
    1730+
    #define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
    1731+
    #define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
    1732+
    #define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
    1733+
    #define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
    1734+
    #define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
    1735+
    #define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
    1736+
    #define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
    1737+
    #define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
    1738+
    1739+
    #define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
    1740+
    1741+
    #define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
    1742+
    #define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
    1743+
    #define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
    1744+
    #define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
    1745+
    #define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
    1746+
    #define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
    1747+
    #define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
    1748+
    #define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
    1749+
    #define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
    1750+
    #define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
    1751+
    #define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
    1752+
    #define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
    1753+
    #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
    1754+
    #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
    1755+
    1756+
    #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
    1757+
    #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
    1758+
    #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
    1759+
    #define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
    1760+
    #define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
    1761+
    #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
    1762+
    #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
    1763+
    #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
    1764+
    1765+
    #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
    1766+
    #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
    1767+
    #define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
    1768+
    1769+
    #define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
    1770+
    #define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
    1771+
    #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
    1772+
    #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
    1773+
    #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
    1774+
    1775+
    #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
    1776+
    #endif
    1777+
    16441778
    /**
    16451779
    * @}
    16461780
    */
    @@ -3399,7 +3533,21 @@ extern "C" {
    33993533
    #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
    34003534
    #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
    34013535
    #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
    3536+
    #define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
    3537+
    #define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
    3538+
    #define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
    3539+
    #define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
    3540+
    #define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
    3541+
    #define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
    3542+
    #define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
    3543+
    #define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
    3544+
    #define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
    3545+
    #define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
    3546+
    #define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
    3547+
    #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
    3548+
    #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
    34023549
    #endif
    3550+
    34033551
    /**
    34043552
    * @}
    34053553
    */
    @@ -3480,10 +3628,15 @@ extern "C" {
    34803628
    #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
    34813629
    #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
    34823630

    3631+
    #if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
    34833632
    #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
    34843633
    #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
    34853634
    #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
    34863635
    3636+
    #define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
    3637+
    #define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
    3638+
    #endif
    3639+
    34873640
    #if defined(STM32F4) || defined(STM32F2)
    34883641
    #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
    34893642
    #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
    @@ -3826,4 +3979,3 @@ extern "C" {
    38263979

    38273980
    #endif /* STM32_HAL_LEGACY */
    38283981

    3829-
    /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

    ‎system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32_assert_template.h

    Lines changed: 5 additions & 9 deletions
    Original file line numberDiff line numberDiff line change
    @@ -8,13 +8,12 @@
    88
    ******************************************************************************
    99
    * @attention
    1010
    *
    11-
    * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
    12-
    * All rights reserved.</center></h2>
    11+
    * Copyright (c) 2020 STMicroelectronics.
    12+
    * All rights reserved.
    1313
    *
    14-
    * This software component is licensed by ST under BSD 3-Clause license,
    15-
    * the "License"; You may not use this file except in compliance with the
    16-
    * License. You may obtain a copy of the License at:
    17-
    * opensource.org/licenses/BSD-3-Clause
    14+
    * This software is licensed under terms that can be found in the LICENSE file
    15+
    * in the root directory of this software component.
    16+
    * If no LICENSE file comes with this software, it is provided AS-IS.
    1817
    *
    1918
    ******************************************************************************
    2019
    */
    @@ -52,6 +51,3 @@
    5251
    #endif
    5352

    5453
    #endif /* __STM32_ASSERT_H */
    55-
    56-
    57-
    /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

    ‎system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h

    Lines changed: 5 additions & 8 deletions
    Original file line numberDiff line numberDiff line change
    @@ -7,13 +7,12 @@
    77
    ******************************************************************************
    88
    * @attention
    99
    *
    10-
    * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
    11-
    * All rights reserved.</center></h2>
    10+
    * Copyright (c) 2020 STMicroelectronics.
    11+
    * All rights reserved.
    1212
    *
    13-
    * This software component is licensed by ST under BSD 3-Clause license,
    14-
    * the "License"; You may not use this file except in compliance with the
    15-
    * License. You may obtain a copy of the License at:
    16-
    * opensource.org/licenses/BSD-3-Clause
    13+
    * This software is licensed under terms that can be found in the LICENSE file
    14+
    * in the root directory of this software component.
    15+
    * If no LICENSE file comes with this software, it is provided AS-IS.
    1716
    *
    1817
    ******************************************************************************
    1918
    */
    @@ -792,5 +791,3 @@ void HAL_SYSCFG_DisableIT(SYSCFG_InterruptTypeDef *Interrupt);
    792791
    #endif
    793792

    794793
    #endif /* __STM32WLxx_HAL_H */
    795-
    796-
    /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

    ‎system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h

    Lines changed: 5 additions & 8 deletions
    Original file line numberDiff line numberDiff line change
    @@ -6,13 +6,12 @@
    66
    ******************************************************************************
    77
    * @attention
    88
    *
    9-
    * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
    10-
    * All rights reserved.</center></h2>
    9+
    * Copyright (c) 2020 STMicroelectronics.
    10+
    * All rights reserved.
    1111
    *
    12-
    * This software component is licensed by ST under BSD 3-Clause license,
    13-
    * the "License"; You may not use this file except in compliance with the
    14-
    * License. You may obtain a copy of the License at:
    15-
    * opensource.org/licenses/BSD-3-Clause
    12+
    * This software is licensed under terms that can be found in the LICENSE file
    13+
    * in the root directory of this software component.
    14+
    * If no LICENSE file comes with this software, it is provided AS-IS.
    1615
    *
    1716
    ******************************************************************************
    1817
    */
    @@ -1712,5 +1711,3 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
    17121711

    17131712

    17141713
    #endif /* STM32WLxx_HAL_ADC_H */
    1715-
    1716-
    /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

    ‎system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h

    Lines changed: 5 additions & 9 deletions
    Original file line numberDiff line numberDiff line change
    @@ -6,13 +6,12 @@
    66
    ******************************************************************************
    77
    * @attention
    88
    *
    9-
    * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
    10-
    * All rights reserved.</center></h2>
    9+
    * Copyright (c) 2020 STMicroelectronics.
    10+
    * All rights reserved.
    1111
    *
    12-
    * This software component is licensed by ST under BSD 3-Clause license,
    13-
    * the "License"; You may not use this file except in compliance with the
    14-
    * License. You may obtain a copy of the License at:
    15-
    * opensource.org/licenses/BSD-3-Clause
    12+
    * This software is licensed under terms that can be found in the LICENSE file
    13+
    * in the root directory of this software component.
    14+
    * If no LICENSE file comes with this software, it is provided AS-IS.
    1615
    *
    1716
    ******************************************************************************
    1817
    */
    @@ -184,6 +183,3 @@ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *had
    184183
    #endif
    185184

    186185
    #endif /* STM32WLxx_HAL_ADC_EX_H */
    187-
    188-
    189-
    /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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