8000 system(f7) update STM32F7xx HAL Drivers to v1.3.2 · stm32duino/Arduino_Core_STM32@ad68430 · GitHub
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system(f7) update STM32F7xx HAL Drivers to v1.3.2
Included in STM32CubeF7 FW v1.17.3 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
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‎system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

Lines changed: 84 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -472,7 +472,9 @@ extern "C" {
472472
#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
473473
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
474474
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
475+
#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
475476
#define PAGESIZE FLASH_PAGE_SIZE
477+
#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */
476478
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
477479
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
478480
#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
@@ -536,6 +538,10 @@ extern "C" {
536538
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
537539
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
538540
#endif /* STM32H7 */
541+
#if defined(STM32H7RS)
542+
#define FLASH_OPTKEY1 FLASH_OPT_KEY1
543+
#define FLASH_OPTKEY2 FLASH_OPT_KEY2
544+
#endif /* STM32H7RS */
539545
#if defined(STM32U5)
540546
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
541547
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
@@ -601,6 +607,15 @@ extern "C" {
601607
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
602608
#endif /* STM32G4 */
603609

610+
#if defined(STM32U5)
611+
612+
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster
613+
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster
614+
#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection
615+
#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection
616+
617+
#endif /* STM32U5 */
618+
604619
#if defined(STM32H5)
605620
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
606621
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
@@ -806,6 +821,21 @@ extern "C" {
806821
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
807822
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
808823
#endif /* STM32U5 */
824+
825+
#if defined(STM32WBA)
826+
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
827+
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
828+
#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
829+
#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
830+
#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
831+
#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
832+
#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
833+
#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
834+
#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
835+
#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
836+
#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
837+
#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
838+
#endif /* STM32WBA */
809839
/**
810840
* @}
811841
*/
@@ -860,6 +890,10 @@ extern "C" {
860890
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
861891
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
862892

893+
#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
894+
#define HRTIMInterruptResquests HRTIMInterruptRequests
895+
#endif /* STM32F3 || STM32G4 || STM32H7 */
896+
863897
#if defined(STM32G4)
864898
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
865899
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
@@ -997,8 +1031,8 @@ extern "C" {
9971031
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
9981032
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
9991033
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
1000-
10011034
#endif /* STM32F3 */
1035+
10021036
/**
10031037
* @}
10041038
*/
@@ -1249,10 +1283,10 @@ extern "C" {
12491283
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
12501284
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
12511285

1252-
#if defined(STM32H5) || defined(STM32H7RS)
1286+
#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
12531287
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
12541288
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
1255-
#endif /* STM32H5 || STM32H7RS */
1289+
#endif /* STM32H5 || STM32H7RS || STM32N6 */
12561290

12571291
#if defined(STM32WBA)
12581292
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@@ -1264,27 +1298,27 @@ extern "C" {
12641298
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
12651299
#endif /* STM32WBA */
12661300

1267-
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
1301+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
12681302
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
12691303
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
1270-
#endif /* STM32H5 || STM32WBA || STM32H7RS */
1304+
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
12711305

1272-
#if defined(STM32F7)
1306+
#if defined(STM32F7) || defined(STM32WB)
12731307
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
12741308
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
1275-
#endif /* STM32F7 */
1309+
#endif /* STM32F7 || STM32WB */
12761310

12771311
#if defined(STM32H7)
12781312
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
12791313
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
12801314
#endif /* STM32H7 */
12811315

1282-
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
1316+
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
12831317
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
12841318
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
12851319
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
12861320
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
1287-
#endif /* STM32F7 || STM32H7 || STM32L0 */
1321+
#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
12881322

12891323
/**
12901324
* @}
@@ -1451,7 +1485,7 @@ extern "C" {
14511485
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
14521486
#endif
14531487

1454-
#if defined(STM32U5)
1488+
#if defined(STM32U5) || defined(STM32MP2)
14551489
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
14561490
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
14571491
#endif
@@ -1817,7 +1851,7 @@ extern "C" {
18171851
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
18181852
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
18191853

1820-
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
1854+
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
18211855
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
18221856
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
18231857

@@ -1999,12 +2033,12 @@ extern "C" {
19992033
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
20002034
* @{
20012035
*/
2002-
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
2036+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
20032037
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
20042038
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
20052039
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
20062040
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
2007-
#endif /* STM32H5 || STM32WBA || STM32H7RS */
2041+
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
20082042

20092043
/**
20102044
* @}
@@ -2731,6 +2765,12 @@ extern "C" {
27312765
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
27322766
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
27332767
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
2768+
#if defined(STM32C0)
2769+
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
2770+
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
2771+
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
2772+
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
2773+
#endif /* STM32C0 */
27342774
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
27352775
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
27362776
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@@ -3659,7 +3699,8 @@ extern "C" {
36593699
#endif
36603700

36613701
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
3662-
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
3702+
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
3703+
defined(STM32U0)
36633704
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
36643705
#else
36653706
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3910,7 +3951,8 @@ extern "C" {
39103951
*/
39113952
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
39123953
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
3913-
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
3954+
defined (STM32WBA) || defined (STM32H5) || \
3955+
defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
39143956
#else
39153957
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
39163958
#endif
@@ -4204,6 +4246,33 @@ extern "C" {
42044246

42054247
#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
42064248
#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
4249+
#if defined(STM32U5)
4250+
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD
4251+
#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK
4252+
#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC
4253+
#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST
4254+
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF
4255+
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT
4256+
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM
4257+
#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM
4258+
#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK
4259+
#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ
4260+
#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT
4261+
#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0
4262+
#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1
4263+
#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM
4264+
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG
4265+
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM
4266+
#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM
4267+
#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT
4268+
#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM
4269+
#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM
4270+
#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID
4271+
#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0
4272+
#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1
4273+
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
4274+
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
4275+
#endif
42074276
/**
42084277
* @}
42094278
*/

‎system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -859,7 +859,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
859859
* @param _CHANNELNB_ Channel number.
860860
* @retval None
861861
*/
862-
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
862+
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << ((3UL * ((uint32_t)((uint16_t)(_CHANNELNB_)))) & 0x1FUL))
863863

864864
/**
865865
* @brief Set the selected regular channel rank for rank between 1 and 6.

‎system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp.h

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,8 @@ typedef struct
5151
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
5252
This parameter can be a value of @ref CRYP_Data_Type */
5353
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
54-
128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
54+
128 or 256 bit key length in TinyAES This parameter can be a value
55+
of @ref CRYP_Key_Size */
5556
uint32_t *pKey; /*!< The key used for encryption/decryption */
5657
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
5758
counter in CTR mode */
@@ -402,8 +403,11 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
402403
*/
403404
#define CRYP_FLAG_MASK 0x0000001FU
404405
#if defined(CRYP)
405-
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
406-
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
406+
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)? \
407+
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) \
408+
& CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
409+
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK))\
410+
== ((__FLAG__) & CRYP_FLAG_MASK)))
407411
#else /* AES*/
408412
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
409413
#endif /* End AES or CRYP */

‎system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -577,7 +577,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0
577577
uint32_t YSize);
578578
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
579579
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
580-
HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
580+
HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, const DCMI_SyncUnmaskTypeDef *SyncUnmask);
581581

582582
/**
583583
* @}

‎system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -484,9 +484,9 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
484484
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
485485
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
486486
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
487-
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
487+
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
488488
uint32_t LayerIdx);
489-
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
489+
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
490490
uint32_t LayerIdx);
491491
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
492492
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
@@ -523,8 +523,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t
523523
*/
524524

525525
/* Peripheral State functions ***************************************************/
526-
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
527-
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
526+
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d);
527+
uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d);
528528

529529
/**
530530
* @}

‎system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ typedef struct
9898

9999
uint32_t *PacketAddress[ETH_TX_DESC_CNT]; /*<! Ethernet packet addresses array */
100100

101-
uint32_t *CurrentPacketAddress; /*<! Current transmit NX_PACKET addresses */
101+
uint32_t *CurrentPacketAddress; /*<! Current transmit packet addresses */
102102

103103
uint32_t BuffersInUse; /*<! Buffers in Use */
104104

@@ -1193,8 +1193,8 @@ TDES7 | Transmit Time Stamp High [31:0]
11931193
*/
11941194
#define HAL_ETH_STATE_RESET 0x00000000U /*!< Peripheral not yet Initialized or disabled */
11951195
#define HAL_ETH_STATE_READY 0x00000010U /*!< Peripheral Communication started */
1196-
#define HAL_ETH_STATE_BUSY 0x00000023U /*!< an internal process is ongoing */
1197-
#define HAL_ETH_STATE_STARTED 0x00000023U /*!< an internal process is started */
1196+
#define HAL_ETH_STATE_BUSY 0x00000020U /*!< an internal process is ongoing */
1197+
#define HAL_ETH_STATE_STARTED 0x00000040U /*!< an internal process is started */
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#define HAL_ETH_STATE_ERROR 0x000000E0U /*!< Error State */
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/**
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* @}
@@ -1787,7 +1787,6 @@ TDES7 | Transmit Time Stamp High [31:0]
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#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = ( __FLAG__))
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/**
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* @brief Checks whether the specified ETHERNET MAC flag is set or not.
17931792< 6A34 div class="diff-text-inner"> * @param __HANDLE__: ETH Handle
@@ -1992,6 +1991,7 @@ uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth);
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uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth);
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uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth);
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uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth);
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uint32_t HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth);
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/**
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* @}
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*/

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