10000 system(U0): update STM32U0xx CMSIS Drivers to v1.2.0 · stm32duino/Arduino_Core_STM32@6d0d956 · GitHub
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system(U0): update STM32U0xx CMSIS Drivers to v1.2.0
Included in STM32CubeU0 FW v1.2.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 39e4786 commit 6d0d956

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+39
-12
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7 files changed

+39
-12
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‎system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h

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@@ -706,6 +706,10 @@ typedef struct
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#define UID_BASE (0x1FFF3E50UL) /*!< Unique device ID register base address */
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#define FLASHSIZE_BASE (0x1FFF3EA0UL) /*!< Flash size data register base address */
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/*!< Bootloader Firmware */
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/************ Bootloader Exit Secure Memory Firmware *************/
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#define BL_EXIT_SEC_MEM_BASE (0x1FFF3500UL)
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/**
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* @}
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*/

‎system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u073xx.h

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@@ -775,6 +775,10 @@ typedef struct
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#define UID_BASE (0x1FFF6E50UL) /*!< Unique device ID register base address */
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#define FLASHSIZE_BASE (0x1FFF6EA0UL) /*!< Flash size data register base address */
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/*!< Bootloader Firmware */
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/************ Bootloader Exit Secure Memory Firmware *************/
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#define BL_EXIT_SEC_MEM_BASE (0x1FFF6000UL)
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/**
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* @}
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*/

‎system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u083xx.h

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@@ -809,6 +809,10 @@ typedef struct
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#define UID_BASE (0x1FFF6E50UL) /*!< Unique device ID register base address */
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#define FLASHSIZE_BASE (0x1FFF6EA0UL) /*!< Flash size data register base address */
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/*!< Bootloader Firmware */
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/************ Bootloader Exit Secure Memory Firmware *************/
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#define BL_EXIT_SEC_MEM_BASE (0x1FFF6000UL)
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/**
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* @}
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*/

‎system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u0xx.h

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@@ -8,8 +8,8 @@
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* is using in the C source code, usually in main.c. This file contains:
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* - Configuration section that allows to select:
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* - The STM32U0xx device used in the target application
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* - To use or not the peripheral’s drivers in application code(i.e.
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* code will be based on direct access to peripheral’s registers
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* - To use or not the peripheral's drivers in application code(i.e.
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* code will be based on direct access to peripheral's registers
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* rather than drivers API), this option is controlled by
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* "#define USE_HAL_DRIVER"
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*
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number 1.0.0
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* @brief CMSIS Device version number 1.2.0
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*/
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#define __STM32U0_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __STM32U0_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
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#define __STM32U0_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
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#define __STM32U0_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __STM32U0_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32U0_CMSIS_VERSION ((__STM32U0_CMSIS_VERSION_MAIN << 24)\
@@ -127,8 +127,8 @@ typedef enum
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typedef enum
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{
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ERROR = 0,
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SUCCESS = !ERROR
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SUCCESS = 0,
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ERROR = !SUCCESS
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} ErrorStatus;
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/**

‎system/Drivers/CMSIS/Device/ST/STM32U0xx/Release_Notes.html

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@@ -30,27 +30,42 @@ <h1 id="release-notes-for-stm32u0xx-cmsis">Release Notes for <mark> STM32U0xx C
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<div class="col-sm-12 col-lg-8">
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<h1 id="update-history"><strong>Update History</strong></h1>
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<div class="collapse">
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<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 05-June-2024</strong></label>
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<input type="checkbox" id="collapse-section3" checked aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 30-October-2024</strong></label>
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<div>
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<h2 id="main-changes">Main Changes</h2>
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<ul>
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<li><strong>CMSIS Device</strong> Maintenance Release version of bits and registers definition aligned with the <strong>RM0503</strong> (STM32U0 reference manual).
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<ul>
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<li>Fixed the right CFGR_HPRE shift in the SystemCoreClockUpdate API.</li>
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<li>Align the ErrorStatus typedef declaration with HAL_StatusTypeDef.</li>
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<li>Add the address to use for the bootloader jump service.</li>
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</ul></li>
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</ul>
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<h1 id="section"></h1>
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</div>
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</div>
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<div class="collapse">
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<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 05-June-2024</strong></label>
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<div>
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<h2 id="main-changes-1">Main Changes</h2>
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<ul>
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<li><strong>CMSIS Device</strong> Maintenance Release version of bits and registers definition aligned with the <strong>RM0503</strong> (STM32U0 reference manual).
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<ul>
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<li>Add I2C_CR1_SBC bit definition.</li>
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<li>Removed the I2C_CR1_SWRST bit definition.</li>
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</ul></li>
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</ul>
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<h1 id="section"></h1>
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<h1 id="section-1"></h1>
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</div>
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</div>
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<div class="collapse">
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<input type="checkbox" id="collapse-section1" ria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 12-February-2024</strong></label>
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<div>
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<h2 id="main-changes-1">Main Changes</h2>
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<h2 id="main-changes-2">Main Changes</h2>
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<ul>
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<li>First official release version of bits and registers definition aligned with the <strong>RM0503</strong> (STM32U0 reference manual).</li>
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</ul>
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<h1 id="section-1"></h1>
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<h1 id="section-2"></h1>
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</div>
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</div>
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</div>

‎system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c

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@@ -327,7 +327,7 @@ void SystemCoreClockUpdate(void)
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U) & 0xFU];
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos) & 0xFU];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}

‎system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md

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@@ -16,7 +16,7 @@
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* STM32L4: 1.7.4
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* STM32L5: 1.0.6
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* STM32MP1: 1.6.0
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* STM32U0: 1.0.0
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* STM32U0: 1.2.0
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* STM32U5: 1.4.0
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* STM32WB: 1.12.2
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* STM32WBA: 1.4.0

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