8000 update hci driver to avoid name collisions · sparkfun/mbed-os-ambiq-apollo3@4e0e283 · GitHub
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update hci driver to avoid name collisions
1 parent 1b822c0 commit 4e0e283

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+35
-47
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1 file changed

+35
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‎features/FEATURE_BLE/targets/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.c

Lines changed: 35 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,7 @@ hci_drv_write_t;
154154
//*****************************************************************************
155155

156156
// BLE module handle
157-
void *BLE;
157+
void *BLEM;
158158

159159
//**************************************************************
160160
// Set a Unique BLE MAC Address per Device
@@ -452,8 +452,8 @@ HciDrvRadioBoot(bool bColdBoot)
452452
uint32_t ui32Status = AM_HAL_STATUS_FAIL;
453453
while (ui32Status != AM_HAL_STATUS_SUCCESS)
454454
{
455-
ERROR_CHECK_VOID(am_hal_ble_initialize(0, &BLE));
456-
ERROR_CHECK_VOID(am_hal_ble_power_control(BLE, AM_HAL_BLE_POWER_ACTIVE));
455+
ERROR_CHECK_VOID(am_hal_ble_initialize(0, &BLEM));
456+
ERROR_CHECK_VOID(am_hal_ble_power_control(BLEM, AM_HAL_BLE_POWER_ACTIVE));
457457

458458
am_hal_ble_config_t sBleConfig =
459459
{
@@ -481,7 +481,7 @@ HciDrvRadioBoot(bool bColdBoot)
481481
.bUseDefaultPatches = true,
482482
};
483483

484-
ERROR_CHECK_VOID(am_hal_ble_config(BLE, &sBleConfig));
484+
ERROR_CHECK_VOID(am_hal_ble_config(BLEM, &sBleConfig));
485485
//
486486
// Delay 1s for 32768Hz clock stability. This isn't required unless this is
487487
// our first run immediately after a power-up.
@@ -493,7 +493,7 @@ HciDrvRadioBoot(bool bColdBoot)
493493
//
494494
// Attempt to boot the radio.
495495
//
496-
ui32Status = am_hal_ble_boot(BLE);
496+
ui32Status = am_hal_ble_boot(BLEM);
497497

498498
//
499499
// Check our status.
@@ -511,8 +511,8 @@ HciDrvRadioBoot(bool bColdBoot)
511511
// If the radio is running, but the clock looks bad, we can try to
512512
// restart.
513513
//
514-
ERROR_CHECK_VOID(am_hal_ble_power_control(BLE, AM_HAL_BLE_POWER_OFF));
515-
ERROR_CHECK_VOID(am_hal_ble_deinitialize(BLE));
514+
ERROR_CHECK_VOID(am_hal_ble_power_control(BLEM, AM_HAL_BLE_POWER_OFF));
515+
ERROR_CHECK_VOID(am_hal_ble_deinitialize(BLEM));
516516

517517
//
518518
// We won't restart forever. After we hit the maximum number of
@@ -529,8 +529,8 @@ HciDrvRadioBoot(bool bColdBoot)
529529
}
530530
else
531531
{
532-
ERROR_CHECK_VOID(am_hal_ble_power_control(BLE, AM_HAL_BLE_POWER_OFF));
533-
ERROR_CHECK_VOID(am_hal_ble_deinitialize(BLE));
532+
ERROR_CHECK_VOID(am_hal_ble_power_control(BLEM, AM_HAL_BLE_POWER_OFF));
533+
ERROR_CHECK_VOID(am_hal_ble_deinitialize(BLEM));
534534
//
535535
// If the radio failed for some reason other than 32K Clock
536536
// instability, we should just report the failure and return.
@@ -543,18 +543,18 @@ HciDrvRadioBoot(bool bColdBoot)
543543
//
544544
// Set the BLE TX Output power to 0dBm.
545545
//
546-
am_hal_ble_tx_power_set(BLE, 0x8);
546+
am_hal_ble_tx_power_set(BLEM, 0x8);
547547

548548
//
549549
// Enable interrupts for the BLE module.
550550
//
551551
#if USE_NONBLOCKING_HCI
552-
am_hal_ble_int_clear(BLE, (AM_HAL_BLE_INT_CMDCMP |
552+
am_hal_ble_int_clear(BLEM, (AM_HAL_BLE_INT_CMDCMP |
553553
AM_HAL_BLE_INT_DCMP |
554554
AM_HAL_BLE_INT_BLECIRQ |
555555
AM_HAL_BLE_INT_BLECSSTAT));
556556

557-
am_hal_ble_int_enable(BLE, (AM_HAL_BLE_INT_CMDCMP |
557+
am_hal_ble_int_enable(BLEM, (AM_HAL_BLE_INT_CMDCMP |
558558
AM_HAL_BLE_INT_DCMP |
559559
AM_HAL_BLE_INT_BLECIRQ |
560560
AM_HAL_BLE_INT_BLECSSTAT));
@@ -563,21 +563,21 @@ HciDrvRadioBoot(bool bColdBoot)
563563
#else
564564
if (APOLLO3_GE_B0)
565565
{
566-
am_hal_ble_int_clear(BLE, (AM_HAL_BLE_INT_BLECIRQN |
566+
am_hal_ble_int_clear(BLEM, (AM_HAL_BLE_INT_BLECIRQN |
567567
AM_HAL_BLE_INT_BLECSSTATN));
568568

569-
am_hal_ble_int_enable(BLE, (AM_HAL_BLE_INT_BLECIRQN |
569+
am_hal_ble_int_enable(BLEM, (AM_HAL_BLE_INT_BLECIRQN |
570570
AM_HAL_BLE_INT_BLECSSTATN));
571571
}
572572
#endif
573573

574574
#else
575575

576-
am_hal_ble_int_clear(BLE, (AM_HAL_BLE_INT_CMDCMP |
576+
am_hal_ble_int_clear(BLEM, (AM_HAL_BLE_INT_CMDCMP |
577577
AM_HAL_BLE_INT_DCMP |
578578
AM_HAL_BLE_INT_BLECIRQ));
579579

580-
am_hal_ble_int_enable(BLE, (AM_HAL_BLE_INT_CMDCMP |
580+
am_hal_ble_int_enable(BLEM, (AM_HAL_BLE_INT_CMDCMP |
581581
AM_HAL_BLE_INT_DCMP |
582582
AM_HAL_BLE_INT_BLECIRQ));
583583
#endif
@@ -612,11 +612,11 @@ HciDrvRadioShutdown(void)
612612

613613
NVIC_DisableIRQ(BLE_IRQn);
614614

615-
ERROR_CHECK_VOID(am_hal_ble_power_control(BLE, AM_HAL_BLE_POWER_OFF));
615+
ERROR_CHECK_VOID(am_hal_ble_power_control(BLEM, AM_HAL_BLE_POWER_OFF));
616616

617617
while ( PWRCTRL->DEVPWREN_b.PWRBLEL );
618618

619-
ERROR_CHECK_VOID(am_hal_ble_deinitialize(BLE));
619+
ERROR_CHECK_VOID(am_hal_ble_deinitialize(BLEM));
620620

621621
g_ui32NumBytes = 0;
622622
g_consumed_bytes = 0;
@@ -641,15 +641,15 @@ update_wake(void)
641641
(BLEIFn(0)->BSTATUS_b.SPISTATUS == 0) &&
642642
(BLE_IRQ_CHECK() == false))
643643
{
644-
am_hal_ble_wakeup_set(BLE, 1);
644+
am_hal_ble_wakeup_set(BLEM, 1);
645645

646646
//
647647
// If we've set wakeup, but IRQ came up at the same time, we should
648648
// just lower WAKE again.
649649
//
650650
if (BLE_IRQ_CHECK() == true)
651651
{
652-
am_hal_ble_wakeup_set(BLE, 0);
652+
am_hal_ble_wakeup_set(BLEM, 0);
653653
}
654654
}
655655

@@ -766,23 +766,11 @@ ap3_hciDrvWrite(uint8_t type, uint16_t len, uint8_t *pData)
766766
// 3: Via macros defined to 24 bit numbers. If an octet is zero, we skip
767767
// setting that octet it
768768
#ifdef AM_CUSTOM_BDADDR_TEMPLT0
769-
// if(AM_CUSTOM_BDADDR_TEMPLT0 & 0xFF)
770-
// bd_addr[0] = AM_CUSTOM_BDADDR_TEMPLT0; // lower 8 bits
771-
// if(AM_CUSTOM_BDADDR_TEMPLT0 & 0xFF00)
772-
// bd_addr[1] = AM_CUSTOM_BDADDR_TEMPLT0 >> 8; // mid 8 bits
773-
// if(AM_CUSTOM_BDADDR_TEMPLT0 & 0xFF0000)
774-
// bd_addr[2] = AM_CUSTOM_BDADDR_TEMPLT0 >> 16; // high 8 bits
775769
bd_addr[0] = (bd_addr[0] & ~AM_CUSTOM_BDADDR_TEMPLT0_MASK) | (AM_CUSTOM_BDADDR_TEMPLT0 & AM_CUSTOM_BDADDR_TEMPLT0_MASK);
776770
bd_addr[1] = (bd_addr[1] & ~(AM_CUSTOM_BDADDR_TEMPLT0_MASK >> 8) ) | ( (AM_CUSTOM_BDADDR_TEMPLT0 & AM_CUSTOM_BDADDR_TEMPLT0_MASK) >> 8);
777771
bd_addr[2] = (bd_addr[2] & ~(AM_CUSTOM_BDADDR_TEMPLT0_MASK >> 16) ) | ( (AM_CUSTOM_BDADDR_TEMPLT0 & AM_CUSTOM_BDADDR_TEMPLT0_MASK) >> 16);
778772
#endif
779773
#ifdef AM_CUSTOM_BDADDR_TEMPLT1
780-
// if(AM_CUSTOM_BDADDR_TEMPLT1 & 0xFF)
781-
// bd_addr[3] = AM_CUSTOM_BDADDR_TEMPLT1; // lower 8 bits
782-
// if(AM_CUSTOM_BDADDR_TEMPLT1 & 0xFF00)
783-
// bd_addr[4] = AM_CUSTOM_BDADDR_TEMPLT1 >> 8; // mid 8 bits
784-
// if(AM_CUSTOM_BDADDR_TEMPLT1 & 0xFF0000)
785-
// bd_addr[5] = AM_CUSTOM_BDADDR_TEMPLT1 >> 16; // high 8 bits
786774
bd_addr[3] = (bd_addr[3] & ~AM_CUSTOM_BDADDR_TEMPLT1_MASK) | (AM_CUSTOM_BDADDR_TEMPLT1 & AM_CUSTOM_BDADDR_TEMPLT1_MASK);
787775
bd_addr[4] = (bd_addr[4] & ~(AM_CUSTOM_BDADDR_TEMPLT1_MASK >> 8) ) | ( (AM_CUSTOM_BDADDR_TEMPLT1 & AM_CUSTOM_BDADDR_TEMPLT1_MASK) >> 8);
788776
bd_addr[5] = (bd_addr[5] & ~(AM_CUSTOM_BDADDR_TEMPLT1_MASK >> 16) ) | ( (AM_CUSTOM_BDADDR_TEMPLT1 & AM_CUSTOM_BDADDR_TEMPLT1_MASK) >> 16);
@@ -854,14 +842,14 @@ HciDrvIntService(void)
854842
//
855843
// Read and clear the interrupt status.
856844
//
857-
uint32_t ui32Status = am_hal_ble_int_status(BLE, true);
858-
am_hal_ble_int_clear(BLE, ui32Status);
845+
uint32_t ui32Status = am_hal_ble_int_status(BLEM, true);
846+
am_hal_ble_int_clear(BLEM, ui32Status);
859847

860848
#if USE_NONBLOCKING_HCI
861849
//
862850
// Handle any DMA or Command Complete interrupts.
863851
//
864-
am_hal_ble_int_service(BLE, ui32Status);
852+
am_hal_ble_int_service(BLEM, ui32Status);
865853

866854
//
867855
// If this was a BLEIRQ interrupt, attempt to start a read operation. If it
@@ -876,7 +864,7 @@ HciDrvIntService(void)
876864
//
877865
//WsfTimerStop(&g_WakeTimer);
878866
// CRITICAL_PRINT("IRQ Drop\n");
879-
am_hal_ble_wakeup_set(BLE, 0);
867+
am_hal_ble_wakeup_set(BLEM, 0);
880868

881869
//
882870
// Prepare to read a message.
@@ -897,7 +885,7 @@ HciDrvIntService(void)
897885
hci_drv_write_t *psWriteBuffer = am_hal_queue_peek(&g_sWriteQueue);
898886

899887
ui32WriteStatus =
900-
am_hal_ble_nonblocking_hci_write(BLE,
888+
am_hal_ble_nonblocking_hci_write(BLEM,
901889
AM_HAL_BLE_RAW,
902890
psWriteBuffer->pui32Data,
903891
psWriteBuffer->ui32Length,
@@ -1010,7 +998,7 @@ hciDrvReadCallback(uint8_t *pui8Data, uint32_t ui32Length, void *pvContext)
1010998
//
1011999
if ( !am_hal_queue_empty(&g_sWriteQueue) )
10121000
{
1013-
am_hal_ble_wakeup_set(BLE, 1);
1001+
am_hal_ble_wakeup_set(BLEM, 1);
10141002
}
10151003

10161004
#endif // TASK_LEVEL_DELAYS
@@ -1107,7 +1095,7 @@ HciDrvHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg)
11071095
//
11081096
CRITICAL_PRINT("INFO: HCI Read started.\n");
11091097
bReadBufferInUse = true;
1110-
ui32ErrorStatus = am_hal_ble_nonblocking_hci_read(BLE,
1098+
ui32ErrorStatus = am_hal_ble_nonblocking_hci_read(BLEM,
11111099
g_pui32ReadBuffer,
11121100
hciDrvReadCallback,
11131101
0);
@@ -1228,7 +1216,7 @@ HciDrvHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg)
12281216
// Is the BLE core asking for a read? If so, do that now.
12291217
//
12301218
g_ui32NumBytes = 0;
1231-
ui32ErrorStatus = am_hal_ble_blocking_hci_read(BLE, (uint32_t*)g_pui32ReadBuffer, &g_ui32NumBytes);
1219+
ui32ErrorStatus = am_hal_ble_blocking_hci_read(BLEM, (uint32_t*)g_pui32ReadBuffer, &g_ui32NumBytes);
12321220

12331221
if (g_ui32NumBytes > HCI_DRV_MAX_RX_PACKET)
12341222
{
@@ -1332,7 +1320,7 @@ HciDrvHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg)
13321320
am_hal_debug_gpio_set(BLE_DEBUG_TRACE_07);
13331321
hci_drv_write_t *psWriteBuffer = am_hal_queue_peek(&g_sWriteQueue);
13341322

1335-
ui32ErrorStatus = am_hal_ble_blocking_hci_write(BLE,
1323+
ui32ErrorStatus = am_hal_ble_blocking_hci_write(BLEM,
13361324
AM_HAL_BLE_RAW,
13371325
psWriteBuffer->pui32Data,
13381326
psWriteBuffer->ui32Length);
@@ -1413,15 +1401,15 @@ HciVsA3_SetRfPowerLevelEx(txPowerLevel_t txPowerlevel)
14131401
switch (txPowerlevel) {
14141402

14151403
case TX_POWER_LEVEL_MINUS_10P0_dBm:
1416-
am_hal_ble_tx_power_set(BLE,0x04);
1404+
am_hal_ble_tx_power_set(BLEM,0x04);
14171405
return true;
14181406
break;
14191407
case TX_POWER_LEVEL_0P0_dBm:
1420-
am_hal_ble_tx_power_set(BLE,0x08);
1408+
am_hal_ble_tx_power_set(BLEM,0x08);
14211409
return true;
14221410
break;
14231411
case TX_POWER_LEVEL_PLUS_3P0_dBm:
1424-
am_hal_ble_tx_power_set(BLE,0x0F);
1412+
am_hal_ble_tx_power_set(BLEM,0x0F);
14251413
return true;
14261414
break;
14271415
default:
@@ -1445,7 +1433,7 @@ HciVsA3_SetRfPowerLevelEx(txPowerLevel_t txPowerlevel)
14451433
void
14461434
HciVsA3_ConstantTransmission(uint8_t txchannel)
14471435
{
1448-
am_util_ble_set_constant_transmission_ex(BLE, txchannel);
1436+
am_util_ble_set_constant_transmission_ex(BLEM, txchannel);
14491437
}
14501438

14511439
/*************************************************************************************************/
@@ -1463,7 +1451,7 @@ HciVsA3_ConstantTransmission(uint8_t txchannel)
14631451
void
14641452
HciVsA3_CarrierWaveMode(uint8_t txchannel)
14651453
{
1466-
am_util_ble_transmitter_control_ex(BLE, txchannel);
1454+
am_util_ble_transmitter_control_ex(BLEM, txchannel);
14671455
}
14681456

14691457
/*************************************************************************************************/
@@ -1480,7 +1468,7 @@ HciVsA3_CarrierWaveMode(uint8_t txchannel)
14801468
void
14811469
HciDrvBleSleepSet(bool enable)
14821470
{
1483-
am_hal_ble_sleep_set(BLE, enable);
1471+
am_hal_ble_sleep_set(BLEM, enable);
14841472
}
14851473

14861474
//*****************************************************************************

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