8000 Merge pull request #2863 from jepler/sdcard-in-core · russbot/circuitpython@111f7dd · GitHub
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Merge pull request adafruit#2863 from jepler/sdcard-in-core
Sdcard in core
2 parents 7750eb0 + 472a04b commit 111f7dd

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‎locale/circuitpython.pot

Lines changed: 48 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ msgid ""
88
msgstr ""
99
"Project-Id-Version: PACKAGE VERSION\n"
1010
"Report-Msgid-Bugs-To: \n"
11-
"POT-Creation-Date: 2020-06-25 11:44-0500\n"
11+
"POT-Creation-Date: 2020-06-26 11:50-0500\n"
1212
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
1313
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
1414
"Language-Team: LANGUAGE <LL@li.org>\n"
@@ -58,6 +58,10 @@ msgstr ""
5858
msgid "%d address pins and %d rgb pins indicate a height of %d, not %d"
5959
msgstr ""
6060

61+
#: ports/atmel-samd/common-hal/sdioio/SDCard.c
62+
msgid "%q failure: %d"
63+
msgstr ""
64+
6165
#: shared-bindings/microcontroller/Pin.c
6266
msgid "%q in use"
6367
msgstr ""
@@ -85,6 +89,10 @@ msgstr ""
8589
msgid "%q must be a tuple of length 2"
8690
msgstr ""
8791

92+
#: ports/atmel-samd/common-hal/sdioio/SDCard.c
93+
msgid "%q pin invalid"
94+
msgstr ""
95+
8896
#: shared-bindings/fontio/BuiltinFont.c
8997
msgid "%q should be an int"
9098
msgstr ""
@@ -338,7 +346,7 @@ msgstr ""
338346
msgid "Array values should be single bytes."
339347
msgstr ""
340348

341-
#: shared-bindings/rgbmatrix/RGBMatrix.c
349+
#: shared-bindings/microcontroller/Pin.c
342350
msgid "At most %d %q may be specified (not %d)"
343351
msgstr ""
344352

@@ -417,6 +425,10 @@ msgstr ""
417425
msgid "Buffer length %d too big. It must be less than %d"
418426
msgstr ""
419427

428+
#: ports/atmel-samd/common-hal/sdioio/SDCard.c shared-module/sdcardio/SDCard.c
429+
msgid "Buffer length must be a multiple of 512"
430+
msgstr ""
431+
420432
#: shared-bindings/bitbangio/I2C.c shared-bindings/busio/I2C.c
421433
msgid "Buffer must be at least length 1"
422434
msgstr ""
@@ -698,7 +710,8 @@ msgstr ""
698710
msgid "Error in regex"
699711
msgstr ""
700712

701-
#: shared-bindings/aesio/aes.c shared-bindings/microcontroller/Pin.c
713+
#: shared-bindings/aesio/aes.c shared-bindings/busio/SPI.c
714+
#: shared-bindings/microcontroller/Pin.c
702715
#: shared-bindings/neopixel_write/__init__.c shared-bindings/pulseio/PulseOut.c
703716
#: shared-bindings/terminalio/Terminal.c
704717
msgid "Expected a %q"
@@ -858,6 +871,10 @@ msgstr ""
858871
msgid "Internal error #%d"
859872
msgstr ""
860873

874+
#: shared-bindings/sdioio/SDCard.c
875+
msgid "Invalid %q"
876+
msgstr ""
877+
861878
#: ports/atmel-samd/common-hal/audiobusio/I2SOut.c
862879
#: ports/atmel-samd/common-hal/audiobusio/PDMIn.c
863880
msgid "Invalid %q pin"
@@ -1358,6 +1375,10 @@ msgstr ""
13581375
msgid "Running in safe mode! Not running saved code.\n"
13591376
msgstr ""
13601377

1378+
#: shared-module/sdcardio/SDCard.c
1379+
msgid "SD card CSD format not supported"
1380+
msgstr ""
1381+
13611382
#: ports/atmel-samd/common-hal/busio/I2C.c
13621383
#: ports/mimxrt10xx/common-hal/busio/I2C.c ports/nrf/common-hal/busio/I2C.c
13631384
msgid "SDA or SCL needs a pull up"
@@ -1979,6 +2000,10 @@ msgstr ""
19792000
msgid "can't send non-None value to a just-started generator"
19802001
msgstr ""
19812002

2003+
#: shared-module/sdcardio/SDCard.c
2004+
msgid "can't set 512 block size"
2005+
msgstr ""
2006+
19822007
#: py/objnamedtuple.c
19832008
msgid "can't set attribute"
19842009
msgstr ""
@@ -2105,6 +2130,10 @@ msgstr ""
21052130
msgid "could not invert Vandermonde matrix"
21062131
msgstr ""
21072132

2133+
#: shared-module/sdcardio/SDCard.c
2134+
msgid "couldn't determine SD card version"
2135+
msgstr ""
2136+
21082137
#: extmod/ulab/code/approx.c
21092138
msgid "data must be iterable"
21102139
msgstr ""
@@ -2662,6 +2691,10 @@ msgstr ""
26622691
msgid "negative shift count"
26632692
msgstr ""
26642693

2694+
#: shared-module/sdcardio/SDCard.c
2695+
msgid "no SD card"
2696+
msgstr ""
2697+
26652698
#: py/vm.c
26662699
msgid "no active exception to reraise"
26672700
msgstr ""
@@ -2683,6 +2716,10 @@ msgstr ""
26832716
msgid "no reset pin available"
26842717
msgstr ""
26852718

2719+
#: shared-module/sdcardio/SDCard.c
2720+
msgid "no response from SD card"
2721+
msgstr ""
2722+
26862723
#: py/runtime.c
26872724
msgid "no such attribute"
26882725
msgstr ""
@@ -3073,6 +3110,14 @@ msgstr ""
30733110
msgid "timeout must be >= 0.0"
30743111
msgstr ""
30753112

3113+
#: shared-module/sdcardio/SDCard.c
3114+
msgid "timeout waiting for v1 card"
3115+
msgstr ""
3116+
3117+
#: shared-module/sdcardio/SDCard.c
3118+
msgid "timeout waiting for v2 card"
3119+
msgstr ""
3120+
30763121
#: shared-bindings/time/__init__.c
30773122
msgid "timestamp out of range for platform time_t"
30783123
msgstr ""

‎ports/atmel-samd/Makefile

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -246,6 +246,14 @@ SRC_ASF += \
246246

247247
endif
248248

249+
ifeq ($(CIRCUITPY_SDIOIO),1)
250+
SRC_ASF += \
251+
hal/src/hal_mci_sync.c \
252+
hpl/sdhc/hpl_sdhc.c \
253+
254+
$(BUILD)/asf4/$(CHIP_FAMILY)/hpl/sdhc/hpl_sdhc.o: CFLAGS += -Wno-cast-align
255+
endif
256+
249257
SRC_ASF := $(addprefix asf4/$(CHIP_FAMILY)/, $(SRC_ASF))
250258

251259
SRC_C = \
@@ -290,6 +298,9 @@ SRC_C = \
290298
supervisor/shared/memory.c \
291299
timer_handler.c \
292300

301+
ifeq ($(CIRCUITPY_SDIOIO),1)
302+
SRC_C += ports/atmel-samd/sd_mmc/sd_mmc.c
303+
endif
293304

294305
ifeq ($(CIRCUITPY_NETWORK),1)
295306
CFLAGS += -DMICROPY_PY_NETWORK=1
@@ -346,6 +357,10 @@ endif
346357
OBJ += $(addprefix $(BUILD)/, $(SRC_S:.s=.o))
347358
OBJ += $(addprefix $(BUILD)/, $(SRC_MOD:.c=.o))
348359

360+
SRC_QSTR += $(HEADER_BUILD)/sdiodata.h
361+
$(HEADER_BUILD)/sdiodata.h: $(TOP)/tools/mksdiodata.py | $(HEADER_BUILD)
362+
$(Q)$(PYTHON3) $< > $@
363+
349364
SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED)
350365
# Sources that only hold QSTRs after pre-processing.
351366
SRC_QSTR_PREPROCESSOR += peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/clocks.c

‎ports/atmel-samd/asf4

‎ports/atmel-samd/asf4_conf/samd51/hpl_sdhc_config.h

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
/* Auto-generated config file hpl_sdhc_config.h */
2+
#ifndef HPL_SDHC_CONFIG_H
3+
#define HPL_SDHC_CONFIG_H
4+
5+
// <<< Use Configuration Wizard in Context Menu >>>
6+
7+
#include "peripheral_clk_config.h"
8+
9+
#ifndef CONF_BASE_FREQUENCY
10+
#define CONF_BASE_FREQUENCY CONF_SDHC0_FREQUENCY
11+
#endif
12+
13+
// <o> Clock Generator Select
14+
// <0=> Divided Clock mode
15+
// <1=> Programmable Clock mode
16+
// <i> This defines the clock generator mode in the SDCLK Frequency Select field
17+
// <id> sdhc_clk_gsel
18+
#ifndef CONF_SDHC0_CLK_GEN_SEL
19+
#define CONF_SDHC0_CLK_GEN_SEL 0
20+
#endif
21+
22+
// <<< end of configuration section >>>
23+
24+
#endif // HPL_SDHC_CONFIG_H

‎ports/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h

Lines changed: 164 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1001,6 +1001,170 @@
10011001
#define CONF_GCLK_USB_FREQUENCY 48000000
10021002
#endif
10031003

1004+
// <h> SDHC Clock Settings
1005+
// <y> SDHC Clock source
1006+
1007+
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
1008+
1009+
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
1010+
1011+
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
1012+
1013+
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
1014+
1015+
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
1016+
1017+
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
1018+
1019+
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
1020+
1021+
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
1022+
1023+
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
1024+
1025+
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
1026+
1027+
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
1028+
1029+
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
1030+
1031+
// <i> Select the clock source for SDHC.
1032+
// <id> sdhc_gclk_selection
1033+
#ifndef CONF_GCLK_SDHC0_SRC
1034+
#define CONF_GCLK_SDHC0_SRC GCLK_GENCTRL_SRC_DFLL_Val
1035+
#endif
1036+
1037+
// <y> SDHC clock slow source
1038+
1039+
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
1040+
1041+
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
1042+
1043+
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
1044+
1045+
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
1046+
1047+
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
1048+
1049+
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
1050+
1051+
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
1052+
1053+
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
1054+
1055+
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
1056+
1057+
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
1058+
1059+
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
1060+
1061+
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
1062+
1063+
// <i> Select the clock source for SDHC.
1064+
// <id> sdhc_slow_gclk_selection
1065+
#ifndef CONF_GCLK_SDHC0_SLOW_SRC
1066+
#define CONF_GCLK_SDHC0_SLOW_SRC GCLK_GENCTRL_SRC_DFLL_Val
1067+
#endif
1068+
// </h>
1069+
1070+
/**
1071+
* \def SDHC FREQUENCY
1072+
* \brief SDHC's Clock frequency
1073+
*/
1074+
#ifndef CONF_SDHC0_FREQUENCY
1075+
#define CONF_SDHC0_FREQUENCY 12000000
1076+
#endif
1077+
1078+
/**
1079+
* \def SDHC FREQUENCY
1080+
* \brief SDHC's Clock slow frequency
1081+
*/
1082+
#ifndef CONF_SDHC0_SLOW_FREQUENCY
1083+
#define CONF_SDHC0_SLOW_FREQUENCY 12000000
1084+
#endif
1085+
1086+
// <h> SDHC Clock Settings
1087+
// <y> SDHC Clock source
1088+
1089+
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
1090+
1091+
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
1092+
1093+
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
1094+
1095+
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
1096+
1097+
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
1098+
1099+
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
1100+
1101+
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
1102+
1103+
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
1104+
1105+
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
1106+
1107+
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
1108+
1109+
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
1110+
1111+
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
1112+
1113+
// <i> Select the clock source for SDHC.
1114+
// <id> sdhc_gclk_selection
1115+
#ifndef CONF_GCLK_SDHC1_SRC
1116+
#define CONF_GCLK_SDHC1_SRC GCLK_GENCTRL_SRC_DFLL_Val
1117+
#endif
1118+
1119+
// <y> SDHC clock slow source
1120+
1121+
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
1122+
1123+
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
1124+
1125+
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
1126+
1127+
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
1128+
1129+
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
1130+
1131+
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
1132+
1133+
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
1134+
1135+
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
1136+
1137+
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
1138+
1139+
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
1140+
1141+
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
1142+
1143+
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
1144+
1145+
// <i> Select the clock source for SDHC.
1146+
// <id> sdhc_slow_gclk_selection
1147+
#ifndef CONF_GCLK_SDHC1_SLOW_SRC
1148+
#define CONF_GCLK_SDHC1_SLOW_SRC GCLK_GENCTRL_SRC_DFLL_Val
1149+
#endif
1150+
// </h>
1151+
1152+
/**
1153+
* \def SDHC FREQUENCY
1154+
* \brief SDHC's Clock frequency
1155+
*/
1156+
#ifndef CONF_SDHC1_FREQUENCY
1157+
#define CONF_SDHC1_FREQUENCY 12000000
1158+
#endif
1159+
1160+
/**
1161+
* \def SDHC FREQUENCY
1162+
* \brief SDHC's Clock slow frequency
1163+
*/
1164+
#ifndef CONF_SDHC1_SLOW_FREQUENCY
1165+
#define CONF_SDHC1_SLOW_FREQUENCY 12000000
1166+
#endif
1167+
10041168
// <<< end of configuration section >>>
10051169

10061170
#endif // PERIPHERAL_CLK_CONFIG_H

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