8000 ZJIT: Pass self through basic block params · ruby/ruby@84d0f24 · GitHub
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ZJIT: Pass self through basic block params
Co-authored-by: Max Bernstein <tekknolagi@gmail.com>
1 parent 2f80117 commit 84d0f24

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4 files changed

+571
-599
lines changed

4 files changed

+571
-599
lines changed

‎zjit/src/backend/arm64/mod.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -641,7 +641,7 @@ impl Assembler
641641
},
642642
// If we're loading a memory operand into a register, then
643643
// we'll switch over to the load instruction.
644-
(Opnd::Reg(_), Opnd::Mem(_)) => {
644+
(Opnd::Reg(_) | Opnd::VReg { .. }, Opnd::Mem(_)) => {
645645
let value = split_memory_address(asm, *src);
646646
asm.load_into(*dest, value);
647647
},
@@ -654,7 +654,7 @@ impl Assembler
654654
};
655655
asm.mov(*dest, value);
656656
},
657-
_ => unreachable!()
657+
_ => unreachable!("unexpected combination of operands in Insn::Mov: {dest:?}, {src:?}")
658658
};
659659
},
660660
Insn::Not { opnd, .. } => {

‎zjit/src/backend/lir.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ impl fmt::Debug for Opnd {
7777
match self {
7878
Self::None => write!(fmt, "None"),
7979
Value(val) => write!(fmt, "Value({val:?})"),
80-
VReg { idx, num_bits } => write!(fmt, "Out{num_bits}({idx})"),
80+
VReg { idx, num_bits } => write!(fmt, "VReg{num_bits}({idx})"),
8181
Imm(signed) => write!(fmt, "{signed:x}_i64"),
8282
UImm(unsigned) => write!(fmt, "{unsigned:x}_u64"),
8383
// Say Mem and Reg only once

‎zjit/src/codegen.rs

Lines changed: 6 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ use crate::state::ZJITState;
77
use crate::{asm::CodeBlock, cruby::*, options::debug, virtualmem::CodePtr};
88
use crate::invariants::{iseq_escapes_ep, track_no_ep_escape_assumption};
99
use crate::backend::lir::{self, asm_comment, Assembler, Opnd, Target, CFP, C_ARG_OPNDS, C_RET_OPND, EC, SP};
10-
use crate::hir::{iseq_to_hir, Block, BlockId, BranchEdge, CallInfo, RangeType};
10+
use crate::hir::{iseq_to_hir, Block, BlockId, BranchEdge, CallInfo, RangeType, SELF_PARAM_IDX};
1111
use crate::hir::{Const, FrameState, Function, Insn, InsnId};
1212
use crate::hir_type::{types::Fixnum, Type};
1313
use crate::options::get_option;
@@ -248,7 +248,6 @@ fn gen_insn(cb: &mut CodeBlock, jit: &mut JITState, asm: &mut Assembler, functio
248248
}
249249

250250
let out_opnd = match insn {
251-
Insn::PutSelf => gen_putself(),
252251
Insn::Const { val: Const::Value(val) } => gen_const(*val),
253252
Insn::NewArray { elements, state } => gen_new_array(jit, asm, elements, &function.frame_state(*state)),
254253
Insn::NewRange { low, high, flag, state } => gen_new_range(asm, opnd!(low), opnd!(high), *flag, &function.frame_state(*state)),
@@ -324,13 +323,16 @@ fn gen_entry_prologue(asm: &mut Assembler, iseq: IseqPtr) {
324323

325324
/// Assign method arguments to basic block arguments at JIT entry
326325
fn gen_method_params(asm: &mut Assembler, iseq: IseqPtr, entry_block: &Block) {
326+
let self_param = gen_param(asm, SELF_PARAM_IDX);
327+
asm.mov(self_param, Opnd::mem(VALUE_BITS, CFP, RUBY_OFFSET_CFP_SELF));
328+
327329
let num_params = entry_block.params().len();
328330
if num_params > 0 {
329331
asm_comment!(asm, "set method params: {num_params}");
330332

331333
// Allocate registers for basic block arguments
332334
let params: Vec<Opnd> = (0..num_params).map(|idx|
333-
gen_param(asm, idx)
335+
gen_param(asm, idx + 1)
334336
).collect();
335337

336338
// Assign local variables to the basic block arguments
@@ -374,11 +376,6 @@ fn gen_getlocal(asm: &mut Assembler, iseq: IseqPtr, local_idx: usize) -> lir::Op
374376
}
375377
}
376378

377-
/// Compile self in the current frame
378-
fn gen_putself() -> lir::Opnd {
379-
Opnd::mem(VALUE_BITS, CFP, RUBY_OFFSET_CFP_SELF)
380-
}
381-
382379
/// Compile a constant
383380
fn gen_const(val: VALUE) -> lir::Opnd {
384381
// Just propagate the constant value and generate nothing
@@ -482,16 +479,14 @@ fn gen_send_without_block_direct(
482479
recv: Opnd,
483480
args: &Vec<InsnId>,
484481
) -> Option<lir::Opnd> {
485-
// Set up the new frame
486-
gen_push_frame(asm, recv);
487-
488482
asm_comment!(asm, "switch to new CFP");
489483
let new_cfp = asm.sub(CFP, RUBY_SIZEOF_CONTROL_FRAME.into());
490484
asm.mov(CFP, new_cfp);
491485
asm.store(Opnd::mem(64, EC, RUBY_OFFSET_EC_CFP), CFP);
492486

493487
// Set up arguments
494488
let mut c_args: Vec<Opnd> = vec![];
489+
c_args.push(recv);
495490
for &arg in args.iter() {
496491
c_args.push(jit.get_opnd(arg)?);
497492
}
@@ -714,18 +709,6 @@ fn gen_save_sp(asm: &mut Assembler, stack_size: usize) {
714709
asm.mov(cfp_sp, sp_addr);
715710
}
716711

717-
/// Compile an interpreter frame
718-
fn gen_push_frame(asm: &mut Assembler, recv: Opnd) {
719-
// Write to a callee CFP
720-
fn cfp_opnd(offset: i32) -> Opnd {
721-
Opnd::mem(64, CFP, offset - (RUBY_SIZEOF_CONTROL_FRAME as i32))
722-
}
723-
724-
asm_comment!(asm, "push callee control frame");
725-
asm.mov(cfp_opnd(RUBY_OFFSET_CFP_SELF), recv);
726-
// TODO: Write more fields as needed
727-
}
728-
729712
/// Return a register we use for the basic block argument at a given index
730713
fn param_reg(idx: usize) -> Reg {
731714
// To simplify the implementation, allocate a fixed register for each basic block argument for now.

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