cc3200: Fix SPI clock divider calculation.

danicampora · danicampora · commit f67d06194fd5 · 2015-11-01T23:33:12.000+01:00
diff --git a/cc3200/hal/spi.c b/cc3200/hal/spi.c
@@ -782,23 +782,17 @@ SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk,
   }
 
   //
-  // Mask the configurations and set clock divider granularity
-  // to 1 cycle
+  // set clock divider granularity to 1 cycle
   //
-  ulRegData = (ulRegData & (~(MCSPI_CH0CONF_WL_M |
-                             MCSPI_CH0CONF_EPOL |
-                             MCSPI_CH0CONF_POL  |
-                             MCSPI_CH0CONF_PHA  |
-                             MCSPI_CH0CONF_TURBO ) |
-               MCSPI_CH0CONF_CLKG));
+  ulRegData |= MCSPI_CH0CONF_CLKG;
 
   //
   // Get the divider value
   //
   ulDivider = ((ulSPIClk/ulBitRate) - 1);
 
   //
-  // The least significant four bits of the divider is used fo configure
+  // The least significant four bits of the divider is used to configure
   // CLKD in MCSPI_CHCONF next eight least significant bits are used to
   // configure the EXTCLK in MCSPI_CHCTRL
   //
