10000 Merge pull request #3281 from dhalbert/fix-spim3-buffer-location · ricardoquesada/circuitpython@94ecf33 · GitHub
[go: up one dir, main page]
Skip to content

Commit 94ecf33

Browse files
dhalbertdhalbert
authored
Merge pull request adafruit#3281 from dhalbert/fix-spim3-buffer-location
SPIM3 buffer must be in first 64kB of RAM
2 parents abfe718 + cf0f3d7 commit 94ecf33

File tree

13 files changed

+115
-100
lines changed

13 files changed

+115
-100
lines changed

‎ports/nrf/boards/arduino_nano_33_ble/mpconfigboard.mk

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,3 @@ USB_MANUFACTURER = "Arduino"
66
MCU_CHIP = nrf52840
77

88
INTERNAL_FLASH_FILESYSTEM = 1
9-
10-
# Allocate two, not just one I2C peripheral, so that we have both
11-
# on-board and off-board I2C available.
12-
# When SPIM3 becomes available we'll be able to have two I2C and two SPI peripherals.
13-
# We use a CFLAGS define here because there are include order issues
14-
# if we try to include "mpconfigport.h" into nrfx_config.h .
15-
CFLAGS += -DCIRCUITPY_NRF_NUM_I2C=2

‎ports/nrf/boards/circuitplayground_bluefruit/mpconfigboard.mk

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,3 @@ MCU_CHIP = nrf52840
88
QSPI_FLASH_FILESYSTEM = 1
99
EXTERNAL_FLASH_DEVICE_COUNT = 1
1010
EXTERNAL_FLASH_DEVICES = "GD25Q16C"
11-
12-
# Allocate two, not just one I2C peripheral for CPB, so that we have both
13-
# on-board and off-board I2C available.
14-
# We use a CFLAGS define here because there are include order issues
15-
# if we try to include "mpconfigport.h" into nrfx_config.h .
16-
CFLAGS += -DCIRCUITPY_NRF_NUM_I2C=2

‎ports/nrf/boards/common.template.ld

Lines changed: 19 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -18,30 +18,33 @@ MEMORY
1818
FLASH_BOOTLOADER_SETTINGS (r) : ORIGIN = ${BOOTLOADER_SETTINGS_START_ADDR}, LENGTH = ${BOOTLOADER_SETTINGS_SIZE}
1919

2020

21-
/* 0x2000000 - RAM:ORIGIN is reserved for Softdevice */
22-
/* SoftDevice 6.1.0 with 5 connections and various increases takes just under 64kiB.
23-
/* To measure the minimum required amount of memory for given configuration, set this number
24-
high enough to work and then check the mutation of the value done by sd_ble_enable. */
25-
SPIM3_RAM (rw) : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE}, LENGTH = ${SPIM3_BUFFER_SIZE}
26-
RAM (xrw) : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE} + ${SPIM3_BUFFER_SIZE}, LENGTH = ${RAM_SIZE} - ${SOFTDEVICE_RAM_SIZE} -${SPIM3_BUFFER_SIZE}
27-
21+
/* SoftDevice RAM must start at the beginning of RAM: 0x2000000 (RAM_START_ADDR).
22+
On nRF52840, the first 64kB of RAM is composed of 8 8kB RAM blocks. Above those is
23+
RAM block 8, which is 192kB.
24+
If SPIM3_BUFFER_RAM_SIZE is 8kB, as opposed to zero, it must be in the first 64kB of RAM.
25+
So the amount of RAM reserved for the SoftDevice must be no more than 56kB.
26+
*/
27+
RAM (xrw) : ORIGIN = ${RAM_START_ADDR}, LENGTH = ${RAM_SIZE}
28+
SD_RAM (rw) : ORIGIN = ${SOFTDEVICE_RAM_START_ADDR}, LENGTH = ${SOFTDEVICE_RAM_SIZE}
29+
SPIM3_RAM (rw) : ORIGIN = ${SPIM3_BUFFER_RAM_START_ADDR}, LENGTH = ${SPIM3_BUFFER_RAM_SIZE}
30+
APP_RAM (xrw) : ORIGIN = ${APP_RAM_START_ADDR}, LENGTH = ${APP_RAM_SIZE}
2831
}
2932

3033
/* produce a link error if there is not this amount of RAM available */
3134
_minimum_heap_size = 0;
3235

3336
/* top end of the stack */
3437

35-
/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
36-
_estack = ORIGIN(RAM) + LENGTH(RAM);
38+
/*_stack_end = ORIGIN(APP_RAM) + LENGTH(APP_RAM);*/
39+
_estack = ORIGIN(APP_RAM) + LENGTH(APP_RAM);
3740

3841
/* RAM extents for the garbage collector */
39-
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
42+
_ram_end = ORIGIN(APP_RAM) + LENGTH(APP_RAM);
4043
_heap_end = 0x20020000; /* tunable */
4144

4245
/* nrf52840 SPIM3 needs its own area to work around hardware problems. Nothing else may use this space. */
4346
_spim3_ram = ORIGIN(SPIM3_RAM);
44-
_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(RAM);
47+
_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(SPIM3_RAM);
4548

4649
/* define output sections */
4750
SECTIONS
@@ -87,7 +90,7 @@ SECTIONS
8790

8891
. = ALIGN(4);
8992
_edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
90-
} >RAM
93+
} >APP_RAM
9194

9295
/* Zero-initialized data section */
9396
.bss :
@@ -100,7 +103,7 @@ SECTIONS
100103

101104
. = ALIGN(4);
102105
_ebss = .; /* define a global symbol at bss end; used by startup code and GC */
103-
} >RAM
106+
} >APP_RAM
104107

105108
/* Uninitialized data section
106109
Data placed into this section will remain unchanged across reboots. */
@@ -113,7 +116,7 @@ SECTIONS
113116

114117
. = ALIGN(4);
115118
_euninitialized = .; /* define a global symbol at uninitialized end; currently unused */
116-
} >RAM
119+
} >APP_RAM
117120

118121
/* this is to define the start of the heap, and make sure we have a minimum size */
119122
.heap :
@@ -123,15 +126,15 @@ SECTIONS
123126
PROVIDE ( _end = . );
124127
_heap_start = .; /* define a global symbol at heap start */
125128
. = . + _minimum_heap_size;
126-
} >RAM
129+
} >APP_RAM
127130

128131
/* this just checks there is enough RAM for the stack */
129132
.stack :
130133
{
131134
. = ALIGN(4);
132135
. = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};
133136
. = ALIGN(4);
134-
} >RAM
137+
} >APP_RAM
135138

136139
/* Remove exception unwinding information, since Circuit Python
137140
does not support this GCC feature. */

‎ports/nrf/boards/hiibot_bluefi/mpconfigboard.mk

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,3 @@ MCU_CHIP = nrf52840
88
QSPI_FLASH_FILESYSTEM = 1
99
EXTERNAL_FLASH_DEVICE_COUNT = 1
1010
EXTERNAL_FLASH_DEVICES = "W25Q16JV_IQ"
11-
12-
# Allocate two, not just one I2C peripheral for Bluefi, so that we have both
13-
# on-board and off-board I2C available.
14-
# When SPIM3 becomes available we'll be able to have two I2C and two SPI peripherals.
15-
# We use a CFLAGS define here because there are include order issues
16-
# if we try to include "mpconfigport.h" into nrfx_config.h .
17-
CFLAGS += -DCIRCUITPY_NRF_NUM_I2C=2

‎ports/nrf/boards/pca10100/mpconfigboard.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,3 +46,5 @@
4646
#define BLEIO_PERIPH_ROLE_COUNT 2
4747
#define BLEIO_TOTAL_CONNECTION_COUNT 2
4848
#define BLEIO_ATTR_TAB_SIZE (BLE_GATTS_ATTR_TAB_SIZE_DEFAULT * 2)
49+
50+
#define SOFTDEVICE_RAM_SIZE (32*1024)

‎ports/nrf/boards/pca10100/mpconfigboard.mk

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -27,9 +27,5 @@ CIRCUITPY_ULAB = 0
2727

2828
SUPEROPT_GC = 0
2929

30-
# These defines must be overridden before mpconfigboard.h is included, which is
31-
# why they are passed on the command line.
32-
CFLAGS += -DSPIM3_BUFFER_SIZE=0 -DSOFTDEVICE_RAM_SIZE='(32*1024)'
33-
3430
# Override optimization to keep binary small
3531
OPTIMIZATION_FLAGS = -Os

‎ports/nrf/boards/simmel/mpconfigboard.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,3 +52,5 @@
5252
#define BLEIO_PERIPH_ROLE_COUNT 2
5353
#define BLEIO_TOTAL_CONNECTION_COUNT 2
5454
#define BLEIO_ATTR_TAB_SIZE (BLE_GATTS_ATTR_TAB_SIZE_DEFAULT * 2)
55+
56+
#define SOFTDEVICE_RAM_SIZE (32*1024)

‎ports/nrf/boards/simmel/mpconfigboard.mk

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -29,9 +29,5 @@ CIRCUITPY_WATCHDOG = 1
2929
# Enable micropython.native
3030
#CIRCUITPY_ENABLE_MPY_NATIVE = 1
3131

32-
# These defines must be overridden before mpconfigboard.h is included, which is
33-
# why they are passed on the command line.
34-
CFLAGS += -DSPIM3_BUFFER_SIZE=0 -DSOFTDEVICE_RAM_SIZE='(32*1024)' -DNRFX_SPIM3_ENABLED=0
35-
3632
# Override optimization to keep binary small
3733
OPTIMIZATION_FLAGS = -Os

‎ports/nrf/common-hal/_bleio/Adapter.c

Lines changed: 15 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@
6161
#endif
6262

6363
#ifndef BLEIO_HVN_TX_QUEUE_SIZE
64-
#define BLEIO_HVN_TX_QUEUE_SIZE 9
64+
#define BLEIO_HVN_TX_QUEUE_SIZE 5
6565
#endif
6666

6767
#ifndef BLEIO_CENTRAL_ROLE_COUNT
@@ -120,11 +120,11 @@ STATIC uint32_t ble_stack_enable(void) {
120120
// Start with no event handlers, etc.
121121
ble_drv_reset();
122122

123-
// Set everything up to have one persistent code editing connection and one user managed
124-
// connection. In the future we could move .data and .bss to the other side of the stack and
123+
// In the future we might move .data and .bss to the other side of the stack and
125124
// dynamically adjust for different memory requirements of the SD based on boot.py
126-
// configuration.
127-
uint32_t app_ram_start = (uint32_t) &_ram_start;
125+
// configuration. But we still need to keep the SPIM3 buffer (if needed) in the first 64kB of RAM.
126+
127+
uint32_t sd_ram_end = SOFTDEVICE_RAM_START_ADDR + SOFTDEVICE_RAM_SIZE;
128128

129129
ble_cfg_t ble_conf;
130130
ble_conf.conn_cfg.conn_cfg_tag = BLE_CONN_CFG_TAG_CUSTOM;
@@ -135,7 +135,7 @@ STATIC uint32_t ble_stack_enable(void) {
135135
// Event length here can influence throughput so perhaps make multiple connection profiles
136136
// available.
137137
ble_conf.conn_cfg.params.gap_conn_cfg.event_length = BLE_GAP_EVENT_LENGTH_DEFAULT;
138-
err_code = sd_ble_cfg_set(BLE_CONN_CFG_GAP, &ble_conf, app_ram_start);
138+
err_code = sd_ble_cfg_set(BLE_CONN_CFG_GAP, &ble_conf, sd_ram_end);
139139
if (err_code != NRF_SUCCESS) {
140140
return err_code;
141141
}
@@ -147,7 +147,7 @@ STATIC uint32_t ble_stack_enable(void) {
147147
ble_conf.gap_cfg 2851 .role_count_cfg.periph_role_count = BLEIO_PERIPH_ROLE_COUNT;
148148
// central_role_count costs 648 bytes for 1 to 2, then ~1250 for each further increment.
149149
ble_conf.gap_cfg.role_count_cfg.central_role_count = BLEIO_CENTRAL_ROLE_COUNT;
150-
err_code = sd_ble_cfg_set(BLE_GAP_CFG_ROLE_COUNT, &ble_conf, app_ram_start);
150+
err_code = sd_ble_cfg_set(BLE_GAP_CFG_ROLE_COUNT, &ble_conf, sd_ram_end);
151151
if (err_code != NRF_SUCCESS) {
152152
return err_code;
153153
}
@@ -158,7 +158,7 @@ STATIC uint32_t ble_stack_enable(void) {
158158
// DevZone recommends not setting this directly, but instead changing gap_conn_cfg.event_length.
159159
// However, we are setting connection extension, so this seems to make sense.
160160
ble_conf.conn_cfg.params.gatts_conn_cfg.hvn_tx_queue_size = BLEIO_HVN_TX_QUEUE_SIZE;
161-
err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATTS, &ble_conf, app_ram_start);
161+
err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATTS, &ble_conf, sd_ram_end);
162162
if (err_code != NRF_SUCCESS) {
163163
return err_code;
164164
}
@@ -167,7 +167,7 @@ STATIC uint32_t ble_stack_enable(void) {
167167
memset(&ble_conf, 0, sizeof(ble_conf));
168168
ble_conf.conn_cfg.conn_cfg_tag = BLE_CONN_CFG_TAG_CUSTOM;
169169
ble_conf.conn_cfg.params.gatt_conn_cfg.att_mtu = BLE_GATTS_VAR_ATTR_LEN_MAX;
170-
err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATT, &ble_conf, app_ram_start);
170+
err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATT, &ble_conf, sd_ram_end);
171171
if (err_code != NRF_SUCCESS) {
172172
return err_code;
173173
}
@@ -177,7 +177,7 @@ STATIC uint32_t ble_stack_enable(void) {
177177
memset(&ble_conf, 0, sizeof(ble_conf));
178178
// Each increment to the BLE_GATTS_ATTR_TAB_SIZE_DEFAULT multiplier costs 1408 bytes.
179179
ble_conf.gatts_cfg.attr_tab_size.attr_tab_size = BLEIO_ATTR_TAB_SIZE;
180-
err_code = sd_ble_cfg_set(BLE_GATTS_CFG_ATTR_TAB_SIZE, &ble_conf, app_ram_start);
180+
err_code = sd_ble_cfg_set(BLE_GATTS_CFG_ATTR_TAB_SIZE, &ble_conf, sd_ram_end);
181181
if (err_code != NRF_SUCCESS) {
182182
return err_code;
183183
}
@@ -187,13 +187,15 @@ STATIC uint32_t ble_stack_enable(void) {
187187
memset(&ble_conf, 0, sizeof(ble_conf));
188188
// Each additional vs_uuid_count costs 16 bytes.
189189
ble_conf.common_cfg.vs_uuid_cfg.vs_uuid_count = BLEIO_VS_UUID_COUNT; // Defaults to 10.
190-
err_code = sd_ble_cfg_set(BLE_COMMON_CFG_VS_UUID, &ble_conf, app_ram_start);
190+
err_code = sd_ble_cfg_set(BLE_COMMON_CFG_VS_UUID, &ble_conf, sd_ram_end);
191191
if (err_code != NRF_SUCCESS) {
192192
return err_code;
193193
}
194194

195-
// This sets app_ram_start to the minimum value needed for the settings set above.
196-
err_code = sd_ble_enable(&app_ram_start);
195+
// This sets sd_ram_end to the minimum value needed for the settings set above.
196+
// You can set a breakpoint just after this call and examine sd_ram_end to see
197+
// how much RAM the SD needs with the configuration above.
198+
err_code = sd_ble_enable(&sd_ram_end);
197199
if (err_code != NRF_SUCCESS) {
198200
return err_code;
199201
}

‎ports/nrf/common-hal/busio/SPI.c

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ STATIC spim_peripheral_t spim_peripherals[] = {
5757
// Allocate SPIM3 first.
5858
{ .spim = NRFX_SPIM_INSTANCE(3),
5959
.max_frequency = 32000000,
60-
.max_xfer_size = MIN(SPIM3_BUFFER_SIZE, (1UL << SPIM3_EASYDMA_MAXCNT_SIZE) - 1)
60+
.max_xfer_size = MIN(SPIM3_BUFFER_RAM_SIZE, (1UL << SPIM3_EASYDMA_MAXCNT_SIZE) - 1)
6161
},
6262
#endif
6363
#if NRFX_CHECK(NRFX_SPIM2_ENABLED)
@@ -87,8 +87,7 @@ STATIC bool never_reset[MP_ARRAY_SIZE(spim_peripherals)];
8787

8888
// Separate RAM area for SPIM3 transmit buffer to avoid SPIM3 hardware errata.
8989
// https://infocenter.nordicsemi.com/index.jsp?topic=%2Ferrata_nRF52840_Rev2%2FERR%2FnRF52840%2FRev2%2Flatest%2Fanomaly_840_198.html
90-
extern uint32_t _spim3_ram;
91-
STATIC uint8_t *spim3_transmit_buffer = (uint8_t *) &_spim3_ram;
90+
STATIC uint8_t *spim3_transmit_buffer = (uint8_t *) SPIM3_BUFFER_RAM_START_ADDR;
9291

9392
void spi_reset(void) {
9493
for (size_t i = 0 ; i < MP_ARRAY_SIZE(spim_peripherals); i++) {

0 commit comments

Comments
 (0)
0