8000 Update cpuinfo.c comments · python/cpython@e758065 · GitHub
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Update cpuinfo.c comments
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‎Python/cpuinfo.c

Lines changed: 15 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -10,14 +10,12 @@
1010
#include <stdint.h> // UINT32_C()
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/* Macro to mark a CPUID register function parameter as being used. */
13-
#define CPUID_REG(PARAM) PARAM
13+
#define CPUID_REG(PARAM) PARAM
1414
/* Macro to check one or more CPUID register bits. */
1515
#define CPUID_CHECK_REG(REG, MASK) ((((REG) & (MASK)) == (MASK)) ? 0 : 1)
1616

17-
/*
18-
* For simplicity, we only enable SIMD instructions for Intel CPUs,
19-
* even though we could support ARM NEON and POWER.
20-
*/
17+
// For simplicity, we only enable SIMD instructions for Intel CPUs,
18+
// even though we could support ARM NEON and POWER.
2119
#if defined(__x86_64__) && defined(__GNUC__)
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# include <cpuid.h> // __cpuid_count()
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#elif defined(_M_X64)
@@ -33,7 +31,7 @@
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|| defined(CAN_COMPILE_SIMD_SSSE3_INSTRUCTIONS) \
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|| defined(CAN_COMPILE_SIMD_SSE4_1_INSTRUCTIONS) \
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|| defined(CAN_COMPILE_SIMD_SSE4_2_INSTRUCTIONS) \
36-
// macros above should be sorted in an alphabetical order
34+
// macros above should be sorted in alphabetical order
3735
/* Used to guard any SSE instructions detection code. */
3836
# define SIMD_SSE_INSTRUCTIONS_DETECTION_GUARD
3937
#endif
@@ -44,13 +42,13 @@
4442
|| defined(CAN_COMPILE_SIMD_AVX_VNNI_INSTRUCTIONS) \
4543
|| defined(CAN_COMPILE_SIMD_AVX_VNNI_INT8_INSTRUCTIONS) \
4644
|| defined(CAN_COMPILE_SIMD_AVX_VNNI_INT16_INSTRUCTIONS) \
47-
// macros above should be sorted in an alphabetical order
45+
// macros above should be sorted in alphabetical order
4846
/* Used to guard any AVX instructions detection code. */
4947
# define SIMD_AVX_INSTRUCTIONS_DETECTION_GUARD
5048
#endif
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5250
#if defined(CAN_COMPILE_SIMD_AVX2_INSTRUCTIONS) \
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// macros above should be sorted in an alphabetical order
51+
// macros above should be sorted in alphabetical order
5452
/* Used to guard any AVX-2 instructions detection code. */
5553
# define SIMD_AVX2_INSTRUCTIONS_DETECTION_GUARD
5654
#endif
@@ -71,7 +69,7 @@
7169
|| defined(CAN_COMPILE_SIMD_AVX512_VPOPCNTDQ_INSTRUCTIONS) \
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|| defined(CAN_COMPILE_SIMD_AVX512_4FMAPS_INSTRUCTIONS) \
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|| defined(CAN_COMPILE_SIMD_AVX512_4VNNIW_INSTRUCTIONS) \
74-
// macros above should be sorted in an alphabetical order
72+
// macros above should be sorted in alphabetical order
7573
/* Used to guard any AVX-512 instructions detection code. */
7674
# define SIMD_AVX512_INSTRUCTIONS_DETECTION_GUARD
7775
#endif
@@ -84,7 +82,7 @@
8482
//
8583
// Additionally, AVX2 cannot be compiled on macOS ARM64 (yet it can be
8684
// compiled on x86_64). However, since autoconf incorrectly assumes so
87-
// when compiling a universal2 binary, we disable AVX for such builds.
85+
// when compiling a universal2 binary, we disable AVX on such builds.
8886
#if defined(__APPLE__)
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# undef SIMD_AVX512_INSTRUCTIONS_DETECTION_GUARD
9088
# if defined(__arm64__)
@@ -181,7 +179,7 @@ get_cpuid_info(uint32_t level /* input eax */,
181179
#if defined(__x86_64__) && defined(__GNUC__)
182180
__cpuid_count(level, count, *eax, *ebx, *ecx, *edx);
183181
#elif defined(_M_X64)
184-
int32_t info[4] = {0};
182+
uint32_t info[4] = {0};
185183
__cpuidex(info, level, count);
186184
*eax = info[0];
187185
*ebx = info[1];
@@ -247,13 +245,13 @@ detect_simd_features(py_simd_features *flags,
247245
#ifdef CAN_COMPILE_SIMD_SSE4_2_INSTRUCTIONS
248246
flags->sse42 = CPUID_CHECK_REG(ecx, ECX_L1_SSE4_2);
249247
#endif
250-
#endif
248+
#endif // !SIMD_SSE_INSTRUCTIONS_DETECTION_GUARD
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252250
#ifdef SIMD_AVX_INSTRUCTIONS_DETECTION_GUARD
253251
#ifdef CAN_COMPILE_SIMD_AVX_INSTRUCTIONS
254252
flags->avx = CPUID_CHECK_REG(ecx, ECX_L1_AVX);
255253
#endif
256-
#endif
254+
#endif // !SIMD_AVX_INSTRUCTIONS_DETECTION_GUARD
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258256
flags->os_xsave = CPUID_CHECK_REG(ecx, ECX_L1_OSXSAVE);
259257
}
@@ -329,7 +327,7 @@ detect_simd_extended_features_ecx_0(py_simd_features *flags,
329327
#ifdef CAN_COMPILE_SIMD_AVX512_VP2INTERSECT_INSTRUCTIONS
330328
flags->avx512_vp2intersect = CPUID_CHECK_REG(edx, EDX_L7_AVX512_VP2INTERSECT);
331329
#endif
332-
#endif
330+
#endif // !SIMD_AVX512_INSTRUCTIONS_DETECTION_GUARD
333331
}
334332

335333
/* Extended Feature Bits (LEAF=7, SUBLEAF=1). */
@@ -357,7 +355,7 @@ detect_simd_extended_features_ecx_1(py_simd_features *flags,
357355
#ifdef CAN_COMPILE_SIMD_AVX_VNNI_INT16_INSTRUCTIONS
358356
flags->avx_vnni_int16 = CPUID_CHECK_REG(edx, EDX_L7S1_AVX_VNNI_INT16);
359357
#endif
360-
#endif
358+
#endif // !SIMD_AVX_INSTRUCTIONS_DETECTION_GUARD
361359
}
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363361
static inline void
@@ -552,7 +550,7 @@ _Py_detect_simd_features(py_simd_features *flags)
552550
#else
553551
(void) maxleaf;
554552
(void) eax; (void) ebx; (void) ecx; (void) edx;
555-
#endif
553+
#endif // !SHOULD_DETECT_SIMD_FEATURES_L1
556554
#ifdef SHOULD_DETECT_SIMD_FEATURES_L7
557555
if (maxleaf >= 7) {
558556
#ifdef SHOULD_DETECT_SIMD_FEATURES_L7S0
@@ -569,7 +567,7 @@ _Py_detect_simd_features(py_simd_features *flags)
569567
#else
570568
(void) maxleaf;
571569
(void) eax; (void) ebx; (void) ecx; (void) edx;
572-
#endif
570+
#endif // !SHOULD_DETECT_SIMD_FEATURES_L7
573571
finalize_simd_features(flags);
574572
if (validate_simd_features(flags) < 0) {
575573
_Py_disable_simd_features(flags);

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