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#include "Python.h"
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#include "pycore_cpuinfo.h"
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- #define CPUID_REG (ARG ) ARG
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+ /* Macro to mark a CPUID register function parameter as being used. */
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+ #define CPUID_REG (PARAM ) PARAM
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+ /* Macro to check a CPUID register bit. */
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+ #define CPUID_CHECK_REG (REGISTER , MASK ) ((REGISTER) & (MASK)) == 0 ? 0 : 1
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/*
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* For simplicity, we only enable SIMD instructions for Intel CPUs,
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# include <intrin.h>
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#else
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# undef CPUID_REG
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- # define CPUID_REG (ARG ) Py_UNUSED(ARG )
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+ # define CPUID_REG (PARAM ) Py_UNUSED(PARAM )
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#endif
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// AVX2 cannot be compiled on macOS ARM64 (yet it can be compiled on x86_64).
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*
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* - REGISTER is either EBX, ECX or EDX,
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* - PAGE is either 1 or 7 depending, and
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- * - FEATURE is an SIMD instruction set .
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+ * - FEATURE is a SIMD feature (with one or more specialized instructions) .
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*/
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- #define EDX1_SSE (1 << 25) // sse, EDX, page 1, bit 25
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- #define EDX1_SSE2 (1 << 26) // sse2, EDX, page 1, bit 26
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- #define ECX1_SSE3 (1 << 9) // sse3, ECX, page 1, bit 0
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- #define ECX1_SSE4_1 (1 << 19) // sse4.1, ECX, page 1, bit 19
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- #define ECX1_SSE4_2 (1 << 20) // sse4.2, ECX, page 1, bit 20
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- #define ECX1_AVX (1 << 28) // avx, ECX, page 1, bit 28
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- #define EBX7_AVX2 (1 << 5) // avx2, EBX, page 7, bit 5
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- #define ECX7_AVX512_VBMI (1 << 1) // avx512-vbmi, ECX, page 7, bit 1
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-
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- #define CHECK_CPUID_REGISTER (REGISTER , MASK ) ((REGISTER) & (MASK)) == 0 ? 0 : 1
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+ #define EDX1_SSE (1 << 25)
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+ #define EDX1_SSE2 (1 << 26)
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+ #define ECX1_SSE3 (1 << 9)
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+ #define ECX1_SSE4_1 (1 << 19)
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+ #define ECX1_SSE4_2 (1 << 20)
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+ #define ECX1_AVX (1 << 28)
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+ #define EBX7_AVX2 (1 << 5)
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+ #define ECX7_AVX512_VBMI (1 << 1)
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/*
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* Indicate whether the CPUID input EAX=1 may be needed to
@@ -100,22 +101,22 @@ detect_cpu_simd_features(py_cpu_simd_flags *flags)
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int32_t eax = 0 , ebx = 0 , ecx = 0 , edx = 0 ;
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get_cpuid_info (1 , 0 , & eax , & ebx , & ecx , & edx );
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#ifdef CAN_COMPILE_SIMD_SSE_INSTRUCTIONS
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- flags -> sse = CHECK_CPUID_REGISTER (edx , EDX1_SSE );
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+ flags -> sse = CPUID_CHECK_REG (edx , EDX1_SSE );
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#endif
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#ifdef CAN_COMPILE_SIMD_SSE2_INSTRUCTIONS
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- flags -> sse2 = CHECK_CPUID_REGISTER (edx , EDX1_SSE2 );
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+ flags -> sse2 = CPUID_CHECK_REG (edx , EDX1_SSE2 );
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#endif
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#ifdef CAN_COMPILE_SIMD_SSE3_INSTRUCTIONS
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- flags -> sse3 = CHECK_CPUID_REGISTER (ecx , ECX1_SSE3 );
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+ flags -> sse3 = CPUID_CHECK_REG (ecx , ECX1_SSE3 );
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#endif
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#ifdef CAN_COMPILE_SIMD_SSE4_1_INSTRUCTIONS
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- flags -> sse41 = CHECK_CPUID_REGISTER (ecx , ECX1_SSE4_1 );
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+ flags -> sse41 = CPUID_CHECK_REG (ecx , ECX1_SSE4_1 );
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#endif
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#ifdef CAN_COMPILE_SIMD_SSE4_2_INSTRUCTIONS
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- flags -> sse42 = CHECK_CPUID_REGISTER (ecx , ECX1_SSE4_2 );
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+ flags -> sse42 = CPUID_CHECK_REG (ecx , ECX1_SSE4_2 );
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#endif
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#ifdef CAN_COMPILE_SIMD_AVX_INSTRUCTIONS
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- flags -> avx = CHECK_CPUID_REGISTER (ecx , ECX1_AVX );
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+ flags -> avx = CPUID_CHECK_REG (ecx , ECX1_AVX );
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#endif
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}
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@@ -126,10 +127,10 @@ detect_cpu_simd_extended_features(py_cpu_simd_flags *flags)
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int32_t eax = 0 , ebx = 0 , ecx = 0 , edx = 0 ;
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get_cpuid_info (7 , 0 , & eax , & ebx , & ecx , & edx );
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#ifdef CAN_COMPILE_SIMD_AVX2_INSTRUCTIONS
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- flags -> avx2 = CHECK_CPUID_REGISTER (ebx , EBX7_AVX2 );
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+ flags -> avx2 = CPUID_CHECK_REG (ebx , EBX7_AVX2 );
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#endif
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#ifdef CAN_COMPILE_SIMD_AVX512_VBMI_INSTRUCTIONS
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- flags -> avx512vbmi = CHECK_CPUID_REGISTER (ecx , ECX7_AVX512_VBMI );
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+ flags -> avx512vbmi = CPUID_CHECK_REG (ecx , ECX7_AVX512_VBMI );
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#endif
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}
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