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Python/cpuinfo.c

Lines changed: 22 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,10 @@
77
#include "Python.h"
88
#include "pycore_cpuinfo.h"
99

10-
#define CPUID_REG(ARG) ARG
10+
/* Macro to mark a CPUID register function parameter as being used. */
11+
#define CPUID_REG(PARAM) PARAM
12+
/* Macro to check a CPUID register bit. */
13+
#define CPUID_CHECK_REG(REGISTER, MASK) ((REGISTER) & (MASK)) == 0 ? 0 : 1
1114

1215
/*
1316
* For simplicity, we only enable SIMD instructions for Intel CPUs,
@@ -19,7 +22,7 @@
1922
# include <intrin.h>
2023
#else
2124
# undef CPUID_REG
22-
# define CPUID_REG(ARG) Py_UNUSED(ARG)
25+
# define CPUID_REG(PARAM) Py_UNUSED(PARAM)
2326
#endif
2427

2528
// AVX2 cannot be compiled on macOS ARM64 (yet it can be compiled on x86_64).
@@ -38,18 +41,16 @@
3841
*
3942
* - REGISTER is either EBX, ECX or EDX,
4043
* - PAGE is either 1 or 7 depending, and
41-
* - FEATURE is an SIMD instruction set.
44+
* - FEATURE is a SIMD feature (with one or more specialized instructions).
4245
*/
43-
#define EDX1_SSE (1 << 25) // sse, EDX, page 1, bit 25
44-
#define EDX1_SSE2 (1 << 26) // sse2, EDX, page 1, bit 26
45-
#define ECX1_SSE3 (1 << 9) // sse3, ECX, page 1, bit 0
46-
#define ECX1_SSE4_1 (1 << 19) // sse4.1, ECX, page 1, bit 19
47-
#define ECX1_SSE4_2 (1 << 20) // sse4.2, ECX, page 1, bit 20
48-
#define ECX1_AVX (1 << 28) // avx, ECX, page 1, bit 28
49-
#define EBX7_AVX2 (1 << 5) // avx2, EBX, page 7, bit 5
50-
#define ECX7_AVX512_VBMI (1 << 1) // avx512-vbmi, ECX, page 7, bit 1
51-
52-
#define CHECK_CPUID_REGISTER(REGISTER, MASK) ((REGISTER) & (MASK)) == 0 ? 0 : 1
46+
#define EDX1_SSE (1 << 25)
47+
#define EDX1_SSE2 (1 << 26)
48+
#define ECX1_SSE3 (1 << 9)
49+
#define ECX1_SSE4_1 (1 << 19)
50+
#define ECX1_SSE4_2 (1 << 20)
51+
#define ECX1_AVX (1 << 28)
52+
#define EBX7_AVX2 (1 << 5)
53+
#define ECX7_AVX512_VBMI (1 << 1)
5354

5455
/*
5556
* Indicate whether the CPUID input EAX=1 may be needed to
@@ -100,22 +101,22 @@ detect_cpu_simd_features(py_cpu_simd_flags *flags)
100101
int32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
101102
get_cpuid_info(1, 0, &eax, &ebx, &ecx, &edx);
102103
#ifdef CAN_COMPILE_SIMD_SSE_INSTRUCTIONS
103-
flags->sse = CHECK_CPUID_REGISTER(edx, EDX1_SSE);
104+
flags->sse = CPUID_CHECK_REG(edx, EDX1_SSE);
104105
#endif
105106
#ifdef CAN_COMPILE_SIMD_SSE2_INSTRUCTIONS
106-
flags->sse2 = CHECK_CPUID_REGISTER(edx, EDX1_SSE2);
107+
flags->sse2 = CPUID_CHECK_REG(edx, EDX1_SSE2);
107108
#endif
108109
#ifdef CAN_COMPILE_SIMD_SSE3_INSTRUCTIONS
109-
flags->sse3 = CHECK_CPUID_REGISTER(ecx, ECX1_SSE3);
110+
flags->sse3 = CPUID_CHECK_REG(ecx, ECX1_SSE3);
110111
#endif
111112
#ifdef CAN_COMPILE_SIMD_SSE4_1_INSTRUCTIONS
112-
flags->sse41 = CHECK_CPUID_REGISTER(ecx, ECX1_SSE4_1);
113+
flags->sse41 = CPUID_CHECK_REG(ecx, ECX1_SSE4_1);
113114
#endif
114115
#ifdef CAN_COMPILE_SIMD_SSE4_2_INSTRUCTIONS
115-
flags->sse42 = CHECK_CPUID_REGISTER(ecx, ECX1_SSE4_2);
116+
flags->sse42 = CPUID_CHECK_REG(ecx, ECX1_SSE4_2);
116117
#endif
117118
#ifdef CAN_COMPILE_SIMD_AVX_INSTRUCTIONS
118-
flags->avx = CHECK_CPUID_REGISTER(ecx, ECX1_AVX);
119+
flags->avx = CPUID_CHECK_REG(ecx, ECX1_AVX);
119120
#endif
120121
}
121122

@@ -126,10 +127,10 @@ detect_cpu_simd_extended_features(py_cpu_simd_flags *flags)
126127
int32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
127128
get_cpuid_info(7, 0, &eax, &ebx, &ecx, &edx);
128129
#ifdef CAN_COMPILE_SIMD_AVX2_INSTRUCTIONS
129-
flags->avx2 = CHECK_CPUID_REGISTER(ebx, EBX7_AVX2);
130+
flags->avx2 = CPUID_CHECK_REG(ebx, EBX7_AVX2);
130131
#endif
131132
#ifdef CAN_COMPILE_SIMD_AVX512_VBMI_INSTRUCTIONS
132-
flags->avx512vbmi = CHECK_CPUID_REGISTER(ecx, ECX7_AVX512_VBMI);
133+
flags->avx512vbmi = CPUID_CHECK_REG(ecx, ECX7_AVX512_VBMI);
133134
#endif
134135
}
135136

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