spi: dw-dma: Get the last DMA scoop out of the FIFO

pelwell · popcornmix · commit 6aab06ff9f81 · 2024-03-05T13:55:32.000Z
With a DMA FIFO threshold greater than 1 (encoded as 0), it is possible for data in the FIFO to be inaccessible, causing the transfer to fail after a timeout. If the transfer includes a transmission, reduce the RX threshold when the TX completes, otherwise use 1 for the whole transfer (inefficient, but not catastrophic at SPI data rates). See: raspberrypi#5696 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
@@ -315,8 +315,10 @@ static void dw_spi_dma_tx_done(void *arg)
 	struct dw_spi *dws = arg;
 
 	clear_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy);
-	if (test_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy))
+	if (test_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy)) {
+		dw_writel(dws, DW_SPI_DMARDLR, 0);
 		return;
+	}
 
 	complete(&dws->dma_completion);
 }
@@ -642,6 +644,8 @@ static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
 
 	nents = max(xfer->tx_sg.nents, xfer->rx_sg.nents);
 
+	dw_writel(dws, DW_SPI_DMARDLR, xfer->tx_buf ? (dws->rxburst - 1) : 0);
+
 	/*
 	 * Execute normal DMA-based transfer (which submits the Rx and Tx SG
 	 * lists directly to the DMA engine at once) if either full hardware
