8000 Merge pull request #18086 from seiko2plus/fix_simd_aarch64_clang · numpy/numpy@c4ae3ce · GitHub
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Merge pull request #18086 from seiko2plus/fix_simd_aarch64_clang
BUG, SIMD: Fix _simd module build for 64bit Arm/neon clang
2 parents 0f63c5e + 14385cd commit c4ae3ce

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3 files changed

+18
-11
lines changed

3 files changed

+18
-11
lines changed

‎numpy/core/src/_simd/_simd_easyintrin.inc

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -87,10 +87,10 @@
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simd_arg_converter, &arg1, \
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simd_arg_converter, &arg2 \
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)) return NULL; \
90-
simd_data data; \
90+
simd_data data = {.u64 = 0}; \
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data.RET = NPY_CAT(SIMD__IMPL_COUNT_, CONST_RNG)( \
9292
SIMD__REPEAT_2IMM, NAME, IN0 \
93-
) npyv_##NAME(arg1.data.IN0, 0); \
93+
) data.RET; \
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simd_arg_free(&arg1); \
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simd_arg ret = { \
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.data = data, .dtype = simd_data_##RET \

‎numpy/core/src/common/simd/neon/operators.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -34,12 +34,12 @@
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#define npyv_shr_s64(A, C) vshlq_s64(A, npyv_setall_s64(-(C)))
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// right by an immediate constant
37-
#define npyv_shri_u16(VEC, C) ((C) == 0 ? VEC : vshrq_n_u16(VEC, C))
38-
#define npyv_shri_s16(VEC, C) ((C) == 0 ? VEC : vshrq_n_s16(VEC, C))
39-
#define npyv_shri_u32(VEC, C) ((C) == 0 ? VEC : vshrq_n_u32(VEC, C))
40-
#define npyv_shri_s32(VEC, C) ((C) == 0 ? VEC : vshrq_n_s32(VEC, C))
41-
#define npyv_shri_u64(VEC, C) ((C) == 0 ? VEC : vshrq_n_u64(VEC, C))
42-
#define npyv_shri_s64(VEC, C) ((C) == 0 ? VEC : vshrq_n_s64(VEC, C))
37+
#define npyv_shri_u16 vshrq_n_u16
38+
#define npyv_shri_s16 vshrq_n_s16
39+
#define npyv_shri_u32 vshrq_n_u32
40+
#define npyv_shri_s32 vshrq_n_s32
41+
#define npyv_shri_u64 vshrq_n_u64
42+
#define npyv_shri_s64 vshrq_n_s64
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4444
/***************************
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* Logical

‎numpy/core/tests/test_simd.py

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -173,14 +173,21 @@ def test_operators_shift(self):
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# left shift
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shl = self.shl(vdata_a, count)
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assert shl == data_shl_a
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# left shift by an immediate constant
177-
shli = self.shli(vdata_a, count)
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assert shli == data_shl_a
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# load to cast
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data_shr_a = self.load([a >> count for a in data_a])
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# right shift
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shr = self.shr(vdata_a, count)
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assert shr == data_shr_a
181+
182+
# shift by zero or max or out-range immediate constant is not applicable and illogical
183+
for count in range(1, self._scalar_size()):
184+
# load to cast
185+
data_shl_a = self.load([a << count for a in data_a])
186+
# left shift by an immediate constant
187+
shli = self.shli(vdata_a, count)
188+
assert shli == data_shl_a
189+
# load to cast
190+
data_shr_a = self.load([a >> count for a in data_a])
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# right shift by an immediate constant
185192
shri = self.shri(vdata_a, count)
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assert shri == data_shr_a

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