8000 stm32/uart: Always enable global UART IRQ handler on init. · msuszko/micropython@0d860fd · GitHub
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dpgeorgedpgeorge
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stm32/uart: Always enable global UART IRQ handler on init.
Otherwise IRQs may not be enabled for the user UART.irq() handler. In particular this fixes the user IRQ_RXIDLE interrupt so that it triggers even when there is no RX buffer.
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2 files changed

+45
-5
lines changed

2 files changed

+45
-5
lines changed

‎ports/stm32/uart.c

Lines changed: 45 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,44 @@
4646
#define UART_RXNE_IT_EN(uart) do { (uart)->CR1 |= USART_CR1_RXNEIE; } while (0)
4747
#define UART_RXNE_IT_DIS(uart) do { (uart)->CR1 &= ~USART_CR1_RXNEIE; } while (0)
4848

49+
#define USART_CR1_IE_BASE (USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | USART_CR1_IDLEIE)
50+
#define USART_CR2_IE_BASE (USART_CR2_LBDIE)
51+
#define USART_CR3_IE_BASE (USART_CR3_CTSIE | USART_CR3_EIE)
52+
53+
#if defined(STM32F0)
54+
#define USART_CR1_IE_ALL (USART_CR1_IE_BASE | USART_CR1_EOBIE | USART_CR1_RTOIE | USART_CR1_CMIE)
55+
#define USART_CR2_IE_ALL (USART_CR2_IE_BASE)
56+
#define USART_CR3_IE_ALL (USART_CR3_IE_BASE | USART_CR3_WUFIE)
57+
58+
#elif defined(STM32F4)
59+
#define USART_CR1_IE_ALL (USART_CR1_IE_BASE)
60+
#define USART_CR2_IE_ALL (USART_CR2_IE_BASE)
61+
#define USART_CR3_IE_ALL (USART_CR3_IE_BASE)
62+
63+
#elif defined(STM32F7)
64+
#define USART_CR1_IE_ALL (USART_CR1_IE_BASE | USART_CR1_EOBIE | USART_CR1_RTOIE | USART_CR1_CMIE)
65+
#define USART_CR2_IE_ALL (USART_CR2_IE_BASE)
66+
#if defined(USART_CR3_TCBGTIE)
67+
#define USART_CR3_IE_ALL (USART_CR3_IE_BASE | USART_CR3_TCBGTIE)
68+
#else
69+
#define USART_CR3_IE_ALL (USART_CR3_IE_BASE)
70+
#endif
71+
72+
#elif defined(STM32H7)
73+
#define USART_CR1_IE_ALL (USART_CR1_IE_BASE | USART_CR1_RXFFIE | USART_CR1_TXFEIE | USART_CR1_EOBIE | USART_CR1_RTOIE | USART_CR1_CMIE)
74+
#define USART_CR2_IE_ALL (USART_CR2_IE_BASE)
75+
#define USART_CR3_IE_ALL (USART_CR3_IE_BASE | USART_CR3_RXFTIE | USART_CR3_TCBGTIE | USART_CR3_TXFTIE | USART_CR3_WUFIE)
76+
77+
#elif defined(STM32L4)
78+
#define USART_CR1_IE_ALL (USART_CR1_IE_BASE | USART 8000 _CR1_EOBIE | USART_CR1_RTOIE | USART_CR1_CMIE)
79+
#define USART_CR2_IE_ALL (USART_CR2_IE_BASE)
80+
#if defined(USART_CR3_TCBGTIE)
81+
#define USART_CR3_IE_ALL (USART_CR3_IE_BASE | USART_CR3_TCBGTIE | USART_CR3_WUFIE)
82+
#else
83+
#define USART_CR3_IE_ALL (USART_CR3_IE_BASE | USART_CR3_WUFIE)
84+
#endif
85+
#endif
86+
4987
extern void NORETURN __fatal_error(const char *msg);
5088

5189
void uart_init0(void) {
@@ -297,7 +335,6 @@ bool uart_init(pyb_uart_obj_t *uart_obj,
297335
}
298336
}
299337

300-
uart_obj->irqn = irqn;
301338
uart_obj->uartx = UARTx;
302339

303340
// init UARTx
@@ -313,6 +350,13 @@ bool uart_init(pyb_uart_obj_t *uart_obj,
313350
huart.Init.OverSampling = UART_OVERSAMPLING_16;
314351
HAL_UART_Init(&huart);
315352

353+
// Disable all individual UART IRQs, but enable the global handler
354+
uart_obj->uartx->CR1 &= ~USART_CR1_IE_ALL;
355+
uart_obj->uartx->CR2 &= ~USART_CR2_IE_ALL;
356+
uart_obj->uartx->CR3 &= ~USART_CR3_IE_ALL;
357+
NVIC_SetPriority(IRQn_NONNEG(irqn), IRQ_PRI_UART);
358+
HAL_NVIC_EnableIRQ(irqn);
359+
316360
uart_obj->is_enabled = true;
317361
uart_obj->attached_to_repl = false;
318362

@@ -340,12 +384,9 @@ void uart_set_rxbuf(pyb_uart_obj_t *self, size_t len, void *buf) {
340384
self->read_buf_len = len;
341385
self->read_buf = buf;
342386
if (len == 0) {
343-
HAL_NVIC_DisableIRQ(self->irqn);
344387
UART_RXNE_IT_DIS(self->uartx);
345388
} else {
346389
UART_RXNE_IT_EN(self->uartx);
347-
NVIC_SetPriority(IRQn_NONNEG(self->irqn), IRQ_PRI_UART);
348-
HAL_NVIC_EnableIRQ(self->irqn);
349390
}
350391
}
351392

‎ports/stm32/uart.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,6 @@ typedef enum {
4646
typedef struct _pyb_uart_obj_t {
4747
mp_obj_base_t base;
4848
USART_TypeDef *uartx;
49-
IRQn_Type irqn;
5049
pyb_uart_t uart_id : 8;
5150
bool is_static : 1;
5251
bool is_enabled : 1;

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