diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile
index 5cf8be79aa1de..24e12d669dd48 100644
--- a/ports/stm32/Makefile
+++ b/ports/stm32/Makefile
@@ -253,6 +253,7 @@ SRC_C = \
 	spibdev.c \
 	storage.c \
 	sdcard.c \
+	sdram.c \
 	fatfs_port.c \
 	lcd.c \
 	accel.c \
@@ -305,10 +306,17 @@ ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f4 f7 h7 l4))
 SRC_HAL += $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES)xx_,\
 	hal_sd.c \
 	ll_sdmmc.c \
+	ll_fmc.c \
 	ll_usb.c \
 	)
 endif
 
+ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f4 f7 h7))
+SRC_HAL += $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES)xx_,\
+	hal_sdram.c \
+	)
+endif
+
 ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),STM32H743xx))
     SRC_HAL += $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES)xx_, hal_fdcan.c)
 else
diff --git a/ports/stm32/boards/STM32F429DISC/mpconfigboard.h b/ports/stm32/boards/STM32F429DISC/mpconfigboard.h
index be25d2e772027..d31160b14b78f 100644
--- a/ports/stm32/boards/STM32F429DISC/mpconfigboard.h
+++ b/ports/stm32/boards/STM32F429DISC/mpconfigboard.h
@@ -72,3 +72,66 @@
 #define MICROPY_HW_USB_HS_IN_FS        (1)
 #define MICROPY_HW_USB_VBUS_DETECT_PIN (pin_B13)
 #define MICROPY_HW_USB_OTG_ID_PIN      (pin_B12)
+
+// SDRAM
+#define MICROPY_HW_SDRAM_SIZE  (64 / 8 * 1024 * 1024)  // 64 Mbit
+#define MICROPY_HW_SDRAM_STARTUP_TEST             (1)
+
+/* Timing configuration for 90 Mhz (11.90ns) of SD clock frequency (180Mhz/2) */
+#define MICROPY_HW_SDRAM_TIMING_TMRD        2
+#define MICROPY_HW_SDRAM_TIMING_TXSR        7
+#define MICROPY_HW_SDRAM_TIMING_TRAS        4
+#define MICROPY_HW_SDRAM_TIMING_TRC         7
+#define MICROPY_HW_SDRAM_TIMING_TWR         2
+#define MICROPY_HW_SDRAM_TIMING_TRP         2
+#define MICROPY_HW_SDRAM_TIMING_TRCD        2
+#define MICROPY_HW_SDRAM_REFRESH_RATE       64 /* ms */
+
+#define MICROPY_HW_SDRAM_CAS_LATENCY        3
+#define MICROPY_HW_SDRAM_COLUMN_BITS_NUM    8
+#define MICROPY_HW_SDRAM_ROW_BITS_NUM       12
+#define MICROPY_HW_SDRAM_MEM_BUS_WIDTH      16
+#define MICROPY_HW_SDRAM_INTERN_BANKS_NUM   4
+#define MICROPY_HW_SDRAM_CLOCK_PERIOD       2
+#define MICROPY_HW_SDRAM_RPIPE_DELAY        1
+#define MICROPY_HW_SDRAM_RBURST            (0)  
+#define MICROPY_HW_SDRAM_WRITE_PROTECTION  (0)  
+
+#define MICROPY_HW_FMC_SDCKE1            (pin_B5)
+#define MICROPY_HW_FMC_SDNE1             (pin_B6)
+#define MICROPY_HW_FMC_SDCLK             (pin_G8)
+#define MICROPY_HW_FMC_SDNCAS            (pin_G15)
+#define MICROPY_HW_FMC_SDNRAS            (pin_F11)
+#define MICROPY_HW_FMC_SDNWE             (pin_C0)
+#define MICROPY_HW_FMC_BA0               (pin_G4)
+#define MICROPY_HW_FMC_BA1               (pin_G5)
+#define MICROPY_HW_FMC_NBL0              (pin_E0)
+#define MICROPY_HW_FMC_NBL1              (pin_E1)
+#define MICROPY_HW_FMC_A0                (pin_F0)
+#define MICROPY_HW_FMC_A1                (pin_F1)
+#define MICROPY_HW_FMC_A2                (pin_F2)
+#define MICROPY_HW_FMC_A3                (pin_F3)
+#define MICROPY_HW_FMC_A4                (pin_F4)
+#define MICROPY_HW_FMC_A5                (pin_F5)
+#define MICROPY_HW_FMC_A6                (pin_F12)
+#define MICROPY_HW_FMC_A7                (pin_F13)
+#define MICROPY_HW_FMC_A8                (pin_F14)
+#define MICROPY_HW_FMC_A9                (pin_F15)
+#define MICROPY_HW_FMC_A10               (pin_G0)
+#define MICROPY_HW_FMC_A11               (pin_G1)
+#define MICROPY_HW_FMC_D0                (pin_D14)
+#define MICROPY_HW_FMC_D1                (pin_D15)
+#define MICROPY_HW_FMC_D2                (pin_D0)
+#define MICROPY_HW_FMC_D3                (pin_D1)
+#define MICROPY_HW_FMC_D4                (pin_E7)
+#define MICROPY_HW_FMC_D5                (pin_E8)
+#define MICROPY_HW_FMC_D6                (pin_E9)
+#define MICROPY_HW_FMC_D7                (pin_E10)
+#define MICROPY_HW_FMC_D8                (pin_E11)
+#define MICROPY_HW_FMC_D9                (pin_E12)
+#define MICROPY_HW_FMC_D10               (pin_E13)
+#define MICROPY_HW_FMC_D11               (pin_E14)
+#define MICROPY_HW_FMC_D12               (pin_E15)
+#define MICROPY_HW_FMC_D13               (pin_D8)
+#define MICROPY_HW_FMC_D14               (pin_D9)
+#define MICROPY_HW_FMC_D15               (pin_D10)
diff --git a/ports/stm32/boards/STM32F429DISC/stm32f4xx_hal_conf.h b/ports/stm32/boards/STM32F429DISC/stm32f4xx_hal_conf.h
index 5b5a8a3e43e52..ec70793c8b915 100644
--- a/ports/stm32/boards/STM32F429DISC/stm32f4xx_hal_conf.h
+++ b/ports/stm32/boards/STM32F429DISC/stm32f4xx_hal_conf.h
@@ -65,7 +65,7 @@
 /* #define HAL_NOR_MODULE_ENABLED */
 /* #define HAL_PCCARD_MODULE_ENABLED */
 /* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
+#define HAL_SDRAM_MODULE_ENABLED
 /* #define HAL_HASH_MODULE_ENABLED */
 #define HAL_GPIO_MODULE_ENABLED
 #define HAL_I2C_MODULE_ENABLED
diff --git a/ports/stm32/main.c b/ports/stm32/main.c
index a8600d975cbe4..eefb19b56710d 100644
--- a/ports/stm32/main.c
+++ b/ports/stm32/main.c
@@ -55,6 +55,7 @@
 #include "rtc.h"
 #include "storage.h"
 #include "sdcard.h"
+#include "sdram.h"
 #include "rng.h"
 #include "accel.h"
 #include "servo.h"
@@ -555,7 +556,16 @@ void stm32_main(uint32_t reset_mode) {
     mp_stack_set_limit((char*)&_estack - (char*)&_heap_end - 1024);
 
     // GC init
+    #if MICROPY_HW_SDRAM_SIZE
+    sdram_init();
+    #if MICROPY_HW_SDRAM_STARTUP_TEST
+    sdram_test(true);
+    #endif
+
+    gc_init(sdram_start(), sdram_end());
+    #else
     gc_init(&_heap_start, &_heap_end);
+    #endif
 
     #if MICROPY_ENABLE_PYSTACK
     static mp_obj_t pystack[384];
diff --git a/ports/stm32/sdram.c b/ports/stm32/sdram.c
new file mode 100644
index 0000000000000..a2bb1cffcc56d
--- /dev/null
+++ b/ports/stm32/sdram.c
@@ -0,0 +1,316 @@
+/*
+ * This file is part of the OpenMV project.
+ * Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
+ * This work is licensed under the MIT license, see the file LICENSE for details.
+ *
+ * SDRAM Driver.
+ *
+ */
+#include <stdio.h>
+#include <stdbool.h>
+#include <string.h>
+#include "py/runtime.h"
+#include "py/mphal.h"
+#include "pin.h"
+#include "pin_static_af.h"
+#include "systick.h"
+#include "sdram.h"
+
+#define SDRAM_TIMEOUT                            ((uint32_t)0xFFFF)
+#define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
+#define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
+#define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
+#define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
+#define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
+
+#if defined(MICROPY_HW_FMC_SDCKE0) && defined(MICROPY_HW_FMC_SDNE0)
+    #define FMC_SDRAM_BANK FMC_SDRAM_BANK1
+    #define FMC_SDRAM_CMD_TARGET_BANK FMC_SDRAM_CMD_TARGET_BANK1
+    #define SDRAM_START_ADDRESS 0xC0000000
+
+#elif defined(MICROPY_HW_FMC_SDCKE1) && defined(MICROPY_HW_FMC_SDNE1)
+    #define FMC_SDRAM_BANK FMC_SDRAM_BANK2
+    #define FMC_SDRAM_CMD_TARGET_BANK FMC_SDRAM_CMD_TARGET_BANK2
+    #define SDRAM_START_ADDRESS 0xD0000000
+#endif
+
+#ifdef FMC_SDRAM_BANK
+static void sdram_init_seq(SDRAM_HandleTypeDef
+        *hsdram, FMC_SDRAM_CommandTypeDef *command);
+extern void __fatal_error(const char *msg);
+#endif
+
+bool sdram_init()
+{
+    #ifndef FMC_SDRAM_BANK
+        return false;
+    #else
+
+    SDRAM_HandleTypeDef hsdram;
+    FMC_SDRAM_TimingTypeDef SDRAM_Timing;
+    FMC_SDRAM_CommandTypeDef command;
+
+    __HAL_RCC_FMC_CLK_ENABLE();
+    
+    #if defined(MICROPY_HW_FMC_SDCKE0)
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDCKE0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDCKE0);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDNE0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDNE0);
+    
+    #elif defined(MICROPY_HW_FMC_SDCKE1)
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDCKE1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDCKE1);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDNE1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDNE1);
+    #endif
+
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDCLK, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDCLK);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDNCAS, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDNCAS);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDNRAS, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDNRAS);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDNWE, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDNWE);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_BA0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_BA0);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_BA1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_BA1);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_NBL0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_NBL0);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_NBL1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_NBL1);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A0);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A1);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A2, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A2);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A3, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A3);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A4, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A4);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A5, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A5);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A6, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A6);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A7, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A7);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A8, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A8);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A9, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A9);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A10, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A10);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A11, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A11);
+    #ifdef MICROPY_HW_FMC_A12
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A12, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A12);
+    #endif
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D0);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D1);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D2, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D2);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D3, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D3);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D4, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D4);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D5, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D5);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D6, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D6);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D7, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D7);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D8, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D8);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D9, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D9);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D10, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D10);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D11, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D11);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D12, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D12);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D13, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D13);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D14, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D14);
+    mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D15, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D15);
+    
+    /* SDRAM device configuration */
+    hsdram.Instance = FMC_SDRAM_DEVICE;
+    /* Timing configuration for 90 Mhz of SD clock frequency (180Mhz/2) */
+    /* TMRD: 2 Clock cycles */
+    SDRAM_Timing.LoadToActiveDelay    = MICROPY_HW_SDRAM_TIMING_TMRD;
+    /* TXSR: min=70ns (6x11.90ns) */
+    SDRAM_Timing.ExitSelfRefreshDelay = MICROPY_HW_SDRAM_TIMING_TXSR;
+    /* TRAS */
+    SDRAM_Timing.SelfRefreshTime      = MICROPY_HW_SDRAM_TIMING_TRAS;
+    /* TRC */
+    SDRAM_Timing.RowCycleDelay        = MICROPY_HW_SDRAM_TIMING_TRC;
+    /* TWR */
+    SDRAM_Timing.WriteRecoveryTime    = MICROPY_HW_SDRAM_TIMING_TWR;
+    /* TRP */
+    SDRAM_Timing.RPDelay              = MICROPY_HW_SDRAM_TIMING_TRP;
+    /* TRCD */
+    SDRAM_Timing.RCDDelay             = MICROPY_HW_SDRAM_TIMING_TRCD;
+
+    #define _FMC_INIT(x, n) x ## _ ## n
+    #define FMC_INIT(x, n) _FMC_INIT(x,  n)
+    
+    hsdram.Init.SDBank             = FMC_SDRAM_BANK;
+    hsdram.Init.ColumnBitsNumber   = FMC_INIT(FMC_SDRAM_COLUMN_BITS_NUM, MICROPY_HW_SDRAM_COLUMN_BITS_NUM);
+    hsdram.Init.RowBitsNumber      = FMC_INIT(FMC_SDRAM_ROW_BITS_NUM, MICROPY_HW_SDRAM_ROW_BITS_NUM);
+    hsdram.Init.MemoryDataWidth    = FMC_INIT(FMC_SDRAM_MEM_BUS_WIDTH, MICROPY_HW_SDRAM_MEM_BUS_WIDTH);
+    hsdram.Init.InternalBankNumber = FMC_INIT(FMC_SDRAM_INTERN_BANKS_NUM, MICROPY_HW_SDRAM_INTERN_BANKS_NUM);
+    hsdram.Init.CASLatency         = FMC_INIT(FMC_SDRAM_CAS_LATENCY, MICROPY_HW_SDRAM_CAS_LATENCY);
+    hsdram.Init.SDClockPeriod      = FMC_INIT(FMC_SDRAM_CLOCK_PERIOD, MICROPY_HW_SDRAM_CLOCK_PERIOD);
+    hsdram.Init.ReadPipeDelay      = FMC_INIT(FMC_SDRAM_RPIPE_DELAY, MICROPY_HW_SDRAM_RPIPE_DELAY);
+    hsdram.Init.ReadBurst          = (MICROPY_HW_SDRAM_RBURST) ? FMC_SDRAM_RBURST_ENABLE : FMC_SDRAM_RBURST_DISABLE;
+    hsdram.Init.WriteProtection    = (MICROPY_HW_SDRAM_WRITE_PROTECTION) ? FMC_SDRAM_WRITE_PROTECTION_ENABLE : FMC_SDRAM_WRITE_PROTECTION_DISABLE;
+
+    /* Initialize the SDRAM controller */
+    if(HAL_SDRAM_Init(&hsdram, &SDRAM_Timing) != HAL_OK) {
+        return false;
+    }
+
+    sdram_init_seq(&hsdram, &command);
+    return true;
+
+    #endif
+}
+
+void * sdram_start() {
+    #ifdef FMC_SDRAM_BANK
+        return (void *)SDRAM_START_ADDRESS;
+    #else
+        return NULL;
+    #endif
+}
+
+void * sdram_end() {
+    #ifdef FMC_SDRAM_BANK
+        return (void *)(SDRAM_START_ADDRESS + MICROPY_HW_SDRAM_SIZE);
+    #else
+        return NULL;
+    #endif
+}
+
+#ifdef FMC_SDRAM_BANK
+static void sdram_init_seq(SDRAM_HandleTypeDef
+        *hsdram, FMC_SDRAM_CommandTypeDef *command)
+{
+    /* Program the SDRAM external device */
+    __IO uint32_t tmpmrd =0;
+
+    /* Step 3:  Configure a clock configuration enable command */
+    command->CommandMode           = FMC_SDRAM_CMD_CLK_ENABLE;
+    command->CommandTarget         = FMC_SDRAM_CMD_TARGET_BANK;
+    command->AutoRefreshNumber     = 1;
+    command->ModeRegisterDefinition = 0;
+
+    /* Send the command */
+    HAL_SDRAM_SendCommand(hsdram, command, 0x1000);
+
+    /* Step 4: Insert 100 ms delay */
+    HAL_Delay(100);
+
+    /* Step 5: Configure a PALL (precharge all) command */
+    command->CommandMode           = FMC_SDRAM_CMD_PALL;
+    command->CommandTarget         = FMC_SDRAM_CMD_TARGET_BANK;
+    command->AutoRefreshNumber     = 1;
+    command->ModeRegisterDefinition = 0;
+
+    /* Send the command */
+    HAL_SDRAM_SendCommand(hsdram, command, 0x1000);
+
+    /* Step 6 : Configure a Auto-Refresh command */
+    command->CommandMode           = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
+    command->CommandTarget         = FMC_SDRAM_CMD_TARGET_BANK;
+    command->AutoRefreshNumber     = 4;
+    command->ModeRegisterDefinition = 0;
+
+    /* Send the command */
+    HAL_SDRAM_SendCommand(hsdram, command, 0x1000);
+
+    /* Step 7: Program the external memory mode register */
+    tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2   |
+        SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |
+        FMC_INIT(SDRAM_MODEREG_CAS_LATENCY, MICROPY_HW_SDRAM_CAS_LATENCY) |
+        SDRAM_MODEREG_OPERATING_MODE_STANDARD |
+        SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
+
+    command->CommandMode           = FMC_SDRAM_CMD_LOAD_MODE;
+    command->CommandTarget         = FMC_SDRAM_CMD_TARGET_BANK;
+    command->AutoRefreshNumber     = 1;
+    command->ModeRegisterDefinition = tmpmrd;
+
+    /* Send the command */
+    HAL_SDRAM_SendCommand(hsdram, command, 0x1000);
+
+    /* Step 8: Set the refresh rate counter 
+       RefreshRate = 64 ms / 8192 cyc = 7.8125 us/cyc
+      
+       RefreshCycles = 7.8125 us * 90 MHz = 703
+       According to the formula on p.1665 of the reference manual,
+       we also need to subtract 20 from the value, so the target
+       refresh rate is 703 - 20 = 683.
+     */
+    #define REFRESH_COUNT (MICROPY_HW_SDRAM_REFRESH_RATE*90000/8192-20)
+    HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);
+
+    #if defined(STM32F7)
+    /* Enable MPU for the SDRAM Memory Region to allow non-aligned 
+       accesses (hard-fault otherwise) 
+    */
+
+    MPU_Region_InitTypeDef MPU_InitStruct;
+
+    /* Disable the MPU */
+    HAL_MPU_Disable();
+
+    /* Configure the MPU attributes for SDRAM */
+    MPU_InitStruct.Enable = MPU_REGION_ENABLE;
+    MPU_InitStruct.BaseAddress = SDRAM_START_ADDRESS;
+    MPU_InitStruct.Size = MPU_REGION_SIZE_4MB;
+    MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
+    MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+    MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
+    MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+    MPU_InitStruct.Number = MPU_REGION_NUMBER0;
+    MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
+    MPU_InitStruct.SubRegionDisable = 0x00;
+    MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
+
+    HAL_MPU_ConfigRegion(&MPU_InitStruct);
+
+    /* Enable the MPU */
+    HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+    #endif
+}
+#endif //FMC_SDRAM_BANK
+
+bool __attribute__((optimize("O0"))) sdram_test(bool fast)
+{
+    #ifndef FMC_SDRAM_BANK
+        return false;
+    #else
+
+        uint8_t const pattern = 0xAA;
+        uint8_t const antipattern = 0x55;
+        uint8_t * const mem_base = (uint8_t*)sdram_start();
+
+        /* test data bus */
+        for (uint8_t i=1; i; i<<=1) {
+            *mem_base = i;
+            if (*mem_base != i) {
+                printf("data bus lines test failed! data (%d)\n", i);
+                __asm__ volatile ("BKPT");
+            }
+        }
+
+        /* test address bus */
+        /* Check individual address lines */
+        for (uint32_t i=1; i<MICROPY_HW_SDRAM_SIZE; i<<=1) {
+            mem_base[i] = pattern;
+            if (mem_base[i] != pattern) {
+                printf("address bus lines test failed! address (%p)\n", &mem_base[i]);
+                __asm__ volatile ("BKPT");
+            }
+        }
+
+        /* Check for aliasing (overlaping addresses) */
+        mem_base[0] = antipattern;
+        for (uint32_t i=1; i<MICROPY_HW_SDRAM_SIZE; i<<=1) {
+            if (mem_base[i] != pattern) {
+                printf("address bus overlap %p\n", &mem_base[i]);
+                __asm__ volatile ("BKPT");
+            }
+        }
+
+        /* test all ram cells */
+        if (!fast) {
+            for (uint32_t i=0; i<MICROPY_HW_SDRAM_SIZE; i++) {
+                mem_base[i] = pattern;
+                if (mem_base[i] != pattern) {
+                    printf("address bus test failed! address (%p)\n", &mem_base[i]);
+                    __asm__ volatile ("BKPT");
+                }
+            }
+        } else {
+            memset(mem_base, pattern, MICROPY_HW_SDRAM_SIZE);
+        }
+
+        return true;
+    #endif
+}
diff --git a/ports/stm32/sdram.h b/ports/stm32/sdram.h
new file mode 100644
index 0000000000000..c9aeafa00a3af
--- /dev/null
+++ b/ports/stm32/sdram.h
@@ -0,0 +1,15 @@
+/*
+ * This file is part of the OpenMV project.
+ * Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
+ * This work is licensed under the MIT license, see the file LICENSE for details.
+ *
+ * SDRAM Driver.
+ *
+ */
+#ifndef __SDRAM_H__
+#define __SDRAM_H__
+bool sdram_init();
+void * sdram_start();
+void * sdram_end();
+bool sdram_test(bool fast);
+#endif // __SDRAM_H__