From 232898ffe6dd866a584077a42a048d6dc41e9ed0 Mon Sep 17 00:00:00 2001 From: mbedNoobNinja Date: Fri, 28 Jul 2023 17:19:46 +0300 Subject: [PATCH] ports/renesas-ra/boards/VK-RA6M3: New Board. ports/renesas-ra/boards: New processor RA6M3. ports/renesas-ra: Integration to the existing RA family. Signed-off-by: mbedNoobNinja --- ports/renesas-ra/Makefile | 72 +- ports/renesas-ra/RA6M3_hal.h | 109 ++ ports/renesas-ra/boards/VK_RA6M3/README.md | 2 + ports/renesas-ra/boards/VK_RA6M3/board.json | 23 + ports/renesas-ra/boards/VK_RA6M3/manifest.py | 3 + .../boards/VK_RA6M3/mpconfigboard.h | 95 + .../boards/VK_RA6M3/mpconfigboard.mk | 24 + ports/renesas-ra/boards/VK_RA6M3/pins.csv | 168 ++ .../VK_RA6M3/ra_cfg/driver/r_qspi_cfg.h | 14 + .../VK_RA6M3/ra_cfg/fsp_cfg/bsp/board_cfg.h | 13 + .../VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 62 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 83 + .../VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h | 25 + .../boards/VK_RA6M3/ra_gen/bsp_clock_cfg.h | 24 + .../boards/VK_RA6M3/ra_gen/common_data.c | 91 + .../boards/VK_RA6M3/ra_gen/common_data.h | 58 + .../boards/VK_RA6M3/ra_gen/hal_data.c | 1558 +++++++++++++++++ .../boards/VK_RA6M3/ra_gen/hal_data.h | 393 +++++ .../boards/VK_RA6M3/ra_gen/pin_data.c | 414 +++++ .../boards/VK_RA6M3/ra_gen/vector_data.c | 107 ++ .../boards/VK_RA6M3/ra_gen/vector_data.h | 148 ++ ports/renesas-ra/boards/VK_RA6M3/vk_ra6m3.ld | 315 ++++ .../boards/VK_RA6M3/vk_ra6m3_conf.h | 30 + ports/renesas-ra/boards/VK_RA6M5/board.json | 11 +- ports/renesas-ra/boards/ra6m3_af.csv | 193 ++ ports/renesas-ra/eth.c | 291 +++ ports/renesas-ra/eth.h | 42 + ports/renesas-ra/fsp_cfg/r_ether_cfg.h | 15 + ports/renesas-ra/fsp_cfg/r_ether_phy_cfg.h | 26 + ports/renesas-ra/fsp_cfg/r_glcdc_cfg.h | 13 + ports/renesas-ra/fsp_cfg/r_jpeg_cfg.h | 14 + ports/renesas-ra/fsp_cfg/r_pdc_cfg.h | 12 + ports/renesas-ra/fsp_cfg/r_sci_i2c_cfg.h | 15 + ports/renesas-ra/lwip_inc/arch/cc.h | 6 +- ports/renesas-ra/machine_cam.c | 1020 +++++++++++ ports/renesas-ra/machine_lcd.c | 374 ++++ ports/renesas-ra/main.c | 7 +- ports/renesas-ra/modmachine.c | 6 + ports/renesas-ra/modmachine.h | 2 + ports/renesas-ra/mpconfigboard_common.h | 5 + ports/renesas-ra/mpconfigport.h | 17 +- ports/renesas-ra/mpnetworkport.c | 25 +- ports/renesas-ra/network_lan.c | 186 ++ ports/renesas-ra/ra/ra_config.h | 2 +- ports/renesas-ra/ra/ra_sci.c | 2 +- ports/renesas-ra/rng.c | 12 +- ports/renesas-ra/uart.c | 4 +- 49 files changed, 6125 insertions(+), 22 deletions(-) create mode 100644 ports/renesas-ra/RA6M3_hal.h create mode 100644 ports/renesas-ra/boards/VK_RA6M3/README.md create mode 100644 ports/renesas-ra/boards/VK_RA6M3/board.json create mode 100644 ports/renesas-ra/boards/VK_RA6M3/manifest.py create mode 100644 ports/renesas-ra/boards/VK_RA6M3/mpconfigboard.h create mode 100644 ports/renesas-ra/boards/VK_RA6M3/mpconfigboard.mk create mode 100644 ports/renesas-ra/boards/VK_RA6M3/pins.csv create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_cfg/driver/r_qspi_cfg.h create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/board_cfg.h create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_cfg.h create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_gen/bsp_clock_cfg.h create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_gen/common_data.c create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_gen/common_data.h create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_gen/hal_data.c create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_gen/hal_data.h create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_gen/pin_data.c create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_gen/vector_data.c create mode 100644 ports/renesas-ra/boards/VK_RA6M3/ra_gen/vector_data.h create mode 100644 ports/renesas-ra/boards/VK_RA6M3/vk_ra6m3.ld create mode 100644 ports/renesas-ra/boards/VK_RA6M3/vk_ra6m3_conf.h create mode 100644 ports/renesas-ra/boards/ra6m3_af.csv create mode 100644 ports/renesas-ra/eth.c create mode 100644 ports/renesas-ra/eth.h create mode 100644 ports/renesas-ra/fsp_cfg/r_ether_cfg.h create mode 100644 ports/renesas-ra/fsp_cfg/r_ether_phy_cfg.h create mode 100644 ports/renesas-ra/fsp_cfg/r_glcdc_cfg.h create mode 100644 ports/renesas-ra/fsp_cfg/r_jpeg_cfg.h create mode 100644 ports/renesas-ra/fsp_cfg/r_pdc_cfg.h create mode 100644 ports/renesas-ra/fsp_cfg/r_sci_i2c_cfg.h create mode 100644 ports/renesas-ra/machine_cam.c create mode 100644 ports/renesas-ra/machine_lcd.c create mode 100644 ports/renesas-ra/network_lan.c diff --git a/ports/renesas-ra/Makefile b/ports/renesas-ra/Makefile index 8126dbe7772d5..6ef7e4283e55f 100644 --- a/ports/renesas-ra/Makefile +++ b/ports/renesas-ra/Makefile @@ -25,6 +25,10 @@ include $(BOARD_DIR)/mpconfigboard.mk USE_FSP_LPM ?= 1 USE_FSP_QSPI ?= 0 +USE_FSP_SDHI ?= 0 +USE_FSP_ETH ?= 0 +USE_FSP_LCD ?= 0 +USE_FSP_CAM ?= 0 FSP_BOARD_NAME ?= $(shell echo $(BOARD) | tr '[:upper:]' '[:lower:]') # Files that are generated and needed before the QSTR build. @@ -73,7 +77,7 @@ INC += -I$(TOP)/lib/tinyusb/hw INC += -I$(TOP)/lib/tinyusb/src INC += -I$(TOP)/shared/tinyusb INC += -Ilwip_inc -ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1 RA4W1 RA6M1 RA6M2 RA6M5)) +ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1 RA4W1 RA6M1 RA6M2 RA6M3 RA6M5)) INC += -Ira endif INC += -I$(BOARD_DIR)/ra_gen @@ -108,6 +112,7 @@ CFLAGS_MCU_RA4M1 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 CFLAGS_MCU_RA4W1 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 CFLAGS_MCU_RA6M1 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 CFLAGS_MCU_RA6M2 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 +CFLAGS_MCU_RA6M3 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 CFLAGS_MCU_RA6M5 = $(CFLAGS_CORTEX_M) -mtune=cortex-m33 -mcpu=cortex-m33 ASFLAGS += $(CFLAGS_CORTEX_M) -mcpu=cortex-$(MCU_SERIES) @@ -327,7 +332,11 @@ SRC_C += \ machine_pin.c \ machine_rtc.c \ machine_sdcard.c \ + machine_lcd.c \ + machine_cam.c \ modmachine.c \ + network_lan.c \ + eth.c \ extint.c \ usrsw.c \ flash.c \ @@ -396,6 +405,26 @@ HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_sdhi/r_sdhi.c \ $(HAL_DIR)/ra/fsp/src/r_dtc/r_dtc.c endif +ifeq ($(USE_FSP_ETH), 1) +CFLAGS += -DUSE_FSP_ETH +HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_ether_phy/targets/ICS1894/r_ether_phy_target_ics1894.c \ + $(HAL_DIR)/ra/fsp/src/r_ether_phy/r_ether_phy.c \ + $(HAL_DIR)/ra/fsp/src/r_ether/r_ether.c +endif + +ifeq ($(USE_FSP_LCD), 1) +CFLAGS += -DUSE_FSP_LCD +HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_glcdc/r_glcdc.c \ + $(HAL_DIR)/ra/fsp/src/r_sci_i2c/r_sci_i2c.c \ + $(HAL_DIR)/ra/fsp/src/r_icu/r_icu.c +endif + +ifeq ($(USE_FSP_CAM), 1) +CFLAGS += -DUSE_FSP_CAM +HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_pdc/r_pdc.c \ + $(HAL_DIR)/ra/fsp/src/r_jpeg/r_jpeg.c +endif + ifeq ($(USE_FSP_LPM), 1) CFLAGS += -DUSE_FSP_LPM HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_lpm/r_lpm.c @@ -408,14 +437,14 @@ HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_flash_lp/r_flash_lp.c endif endif -ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M1 RA6M2 RA6M5)) +ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M1 RA6M2 RA6M3 RA6M5)) ifeq ($(USE_FSP_FLASH), 1) CFLAGS += -DUSE_FSP_FLASH HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_flash_hp/r_flash_hp.c endif endif -ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1 RA4W1 RA6M1 RA6M2 RA6M5)) +ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1 RA4W1 RA6M1 RA6M2 RA6M3 RA6M5)) HAL_SRC_C += $(addprefix ra/,\ ra_adc.c \ ra_dac.c \ @@ -432,10 +461,43 @@ HAL_SRC_C += $(addprefix ra/,\ ra_gpt.c \ ra_utils.c \ ) +endif +ifeq ($(MICROPY_SSL_MBEDTLS),1) +LIB_SRC_C += mbedtls/mbedtls_port.c endif ifeq ($(MICROPY_HW_ENABLE_RNG),1) +ifeq ($(CMSIS_MCU),RA6M3) +CRYPTO_DIR = ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/ + +INC += -I$(TOP)/$(HAL_DIR)/$(CRYPTO_DIR)/private/inc +INC += -I$(TOP)/$(HAL_DIR)/$(CRYPTO_DIR)/public/inc +INC += -I$(TOP)/$(HAL_DIR)/$(CRYPTO_DIR)/primitive +INC += -I$(TOP)/$(HAL_DIR)/ra/fsp/src/r_sce/common +INC += -I$(TOP)/$(HAL_DIR)/ra/fsp/src/r_sce + +# The following FSP files are required for the random number generator. +HAL_SRC_C += $(addprefix $(HAL_DIR)/$(CRYPTO_DIR)/,\ + adaptors/r_sce_adapt.c \ + primitive/hw_sce_p_p00.c \ + primitive/hw_sce_p_p01.c \ + primitive/hw_sce_p_p02.c \ + primitive/hw_sce_p_p20.c \ + primitive/hw_sce_p_func050.c \ + primitive/hw_sce_p_func051.c \ + primitive/hw_sce_p_func052.c \ + primitive/hw_sce_p_func053.c \ + primitive/hw_sce_p_func054.c \ + primitive/hw_sce_p_func100.c \ + primitive/hw_sce_p_func101.c \ + primitive/hw_sce_p_func102.c \ + primitive/hw_sce_p_func103.c \ + primitive/hw_sce_p_subprc01.c \ + primitive/hw_sce_p_subprc02.c \ + ) +endif +ifeq ($(CMSIS_MCU),RA6M5) CRYPTO_DIR = ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/ INC += -I$(TOP)/$(HAL_DIR)/$(CRYPTO_DIR)/inc @@ -471,6 +533,7 @@ HAL_SRC_C += $(addprefix $(HAL_DIR)/$(CRYPTO_DIR)/,\ primitive/r_sce_subprc01.c\ ) endif +endif OBJ += $(PY_O) OBJ += $(addprefix $(BUILD)/, $(LIB_SRC_C:.c=.o)) @@ -554,6 +617,9 @@ endif ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M2)) AF_FILE = boards/ra6m2_af.csv endif +ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M3)) +AF_FILE = boards/ra6m3_af.csv +endif ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M5)) AF_FILE = boards/ra6m5_af.csv endif diff --git a/ports/renesas-ra/RA6M3_hal.h b/ports/renesas-ra/RA6M3_hal.h new file mode 100644 index 0000000000000..d693386dc18ea --- /dev/null +++ b/ports/renesas-ra/RA6M3_hal.h @@ -0,0 +1,109 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * Copyright (c) 2023 Vekatech Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef PORTS_RA_RA6M3_HAL_H_ +#define PORTS_RA_RA6M3_HAL_H_ + +#include +#include +#include +// #include "hal_data.h" +#include "bsp_api.h" +#include "common_data.h" +#if defined(USE_DBG_PRINT) +#include RA_CFG_H +#endif + +#define SCI_CH DEFAULT_DBG_CH +#define SCI_BAUD 115200 +#define UART_CH SCI_CH +#define UART_TxStr sci_tx_str +#define PCLK 120000000 + +#define RA_PRI_SYSTICK (0) +#define RA_PRI_UART (1) +#define RA_PRI_SDIO (4) +#define RA_PRI_DMA (5) +#define RA_PRI_FLASH (6) +#define RA_PRI_OTG_FS (6) +#define RA_PRI_OTG_HS (6) +#define RA_PRI_TIM5 (6) +#define RA_PRI_CAN (7) +#define RA_PRI_SPI (8) +#define RA_PRI_I2C (8) +#define RA_PRI_TIMX (13) +#define RA_PRI_EXTINT (14) +#define RA_PRI_PENDSV (15) +#define RA_PRI_RTC_WKUP (15) + +#include "ra_config.h" +#include "ra_adc.h" +#include "ra_dac.h" +#include "ra_flash.h" +#include "ra_gpio.h" +#include "ra_gpt.h" +#include "ra_i2c.h" +#include "ra_icu.h" +#include "ra_init.h" +#include "ra_int.h" +#include "ra_rtc.h" +#include "ra_sci.h" +#include "ra_spi.h" +#include "ra_timer.h" +#include "ra_utils.h" + +typedef enum { + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +#define __IO volatile + +#if defined(USE_DBG_PRINT) +#if !defined(DEBUG_CH) +#define DEBUG_CH SCI_CH +#endif +#if (DEBUG_CH == 7) +#define DEBUG_TX_PIN P613 +#define DEBUG_RX_PIN P614 +#endif +#if (DEBUG_CH == 8) +#define DEBUG_TX_PIN P105 +#define DEBUG_RX_PIN P104 +#endif +#if (DEBUG_CH == 9) +#define DEBUG_TX_PIN P109 +#define DEBUG_RX_PIN P110 +#endif +#define DEBUG_TXSTR(s) ra_sci_tx_str(DEBUG_CH, (unsigned char *)s) +#define DEBUG_TXCH(c) ra_sci_tx_ch(DEBUG_CH, c) +#else +#define DEBUG_TXSTR(s) +#define DEBUG_TXCH(c) +#endif + +#endif /* PORTS_RA_RA6M3_HAL_H_ */ diff --git a/ports/renesas-ra/boards/VK_RA6M3/README.md b/ports/renesas-ra/boards/VK_RA6M3/README.md new file mode 100644 index 0000000000000..3b3970eb34ba7 --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/README.md @@ -0,0 +1,2 @@ +In case you need to debug something in `VK_RA6M3` board, make sure the contents of +[project repo](https://github.com/Vekatech/VK_RA6M3) is cloned in to **this** directory. diff --git a/ports/renesas-ra/boards/VK_RA6M3/board.json b/ports/renesas-ra/boards/VK_RA6M3/board.json new file mode 100644 index 0000000000000..3387bb791d25c --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/board.json @@ -0,0 +1,23 @@ +{ + "deploy": [ + "../deploy.md" + ], + "docs": "https://vekatech.com/VK-RA6M3_docs/brochures/VK-RA6M3%20Flyer%20R2.pdf", + "features": [ + "DAC", + "USB", + "microSD", + "Ethernet", + "Camera", + "Display", + "External Flash" + ], + "images": [ + "VK-RA6M3.jpg" + ], + "mcu": "ra6m3", + "product": "VK-RA6M3", + "thumbnail": "", + "url": "https://vekatech.com", + "vendor": "Vekatech" +} diff --git a/ports/renesas-ra/boards/VK_RA6M3/manifest.py b/ports/renesas-ra/boards/VK_RA6M3/manifest.py new file mode 100644 index 0000000000000..8404415e1e901 --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/manifest.py @@ -0,0 +1,3 @@ +include("$(PORT_DIR)/boards/manifest.py") +# Networking +require("bundle-networking") diff --git a/ports/renesas-ra/boards/VK_RA6M3/mpconfigboard.h b/ports/renesas-ra/boards/VK_RA6M3/mpconfigboard.h new file mode 100644 index 0000000000000..dca6965c83271 --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/mpconfigboard.h @@ -0,0 +1,95 @@ +// MCU config +#define MICROPY_HW_BOARD_NAME "VK-RA6M3" +#define MICROPY_HW_MCU_NAME "RA6M3" +#define MICROPY_HW_MCU_SYSCLK 120000000 +#define MICROPY_HW_MCU_PCLK 120000000 + +// module config +#define MICROPY_EMIT_THUMB (1) +#define MICROPY_EMIT_INLINE_THUMB (1) +#define MICROPY_PY_BUILTINS_COMPLEX (1) +#define MICROPY_PY_GENERATOR_PEND_THROW (1) +#define MICROPY_PY_MATH (1) +#define MICROPY_PY_HEAPQ (1) +#define MICROPY_PY_THREAD (0) // disable ARM_THUMB_FP using vldr due to RA has single float only +#define MICROPY_HW_ETH_MDC (1) +#define MICROPY_PY_NETWORK (1) +#define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT MICROPY_HW_BOARD_NAME + +#define MODULE_LCD_ENABLED (1) +#define MODULE_CAM_ENABLED (1) + +// peripheral config +#define MICROPY_HW_ENABLE_RNG (1) +#define MICROPY_HW_ENABLE_RTC (1) +#define MICROPY_HW_RTC_SOURCE (1) // 0: subclock +#define MICROPY_HW_ENABLE_ADC (1) +#define MICROPY_HW_HAS_FLASH (1) +#define MICROPY_HW_ENABLE_USBDEV (1) +#define MICROPY_HW_ENABLE_UART_REPL (1) +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1) +#define MICROPY_HW_HAS_QSPI_FLASH (1) +#define MICROPY_HW_HAS_SDHI_CARD (1) + +// board config + +// UART +#define MICROPY_HW_UART7_TX (pin_P613) // D1 +#define MICROPY_HW_UART7_RX (pin_P614) // D0 +#define MICROPY_HW_UART8_TX (pin_P105) // Modbus (RS485) +#define MICROPY_HW_UART8_RX (pin_P104) // Modbus (RS485) +#define MICROPY_HW_UART9_TX (pin_P109) // REPL +#define MICROPY_HW_UART9_RX (pin_P110) // REPL +#define MICROPY_HW_UART_REPL HW_UART_9 +#define MICROPY_HW_UART_REPL_BAUD 115200 + +// I2C +#define MICROPY_HW_I2C1_SCL (pin_P205) +#define MICROPY_HW_I2C1_SDA (pin_P206) + +// SPI +#define MICROPY_HW_SPI1_SSL (pin_P301) // D10 +#define MICROPY_HW_SPI1_RSPCK (pin_P204) // D13 +#define MICROPY_HW_SPI1_MISO (pin_P202) // D12 +#define MICROPY_HW_SPI1_MOSI (pin_P203) // D11 + +// PWM +// #define MICROPY_HW_PWM_8A (pin_P107) // D7 +#define MICROPY_HW_PWM_8A (pin_P605) // LED_B +#define MICROPY_HW_PWM_2A (pin_P113) // D4 +#define MICROPY_HW_PWM_2B (pin_P114) // D5 +#define MICROPY_HW_PWM_4A (pin_P115) // D6 +// #define MICROPY_HW_PWM_4A (pin_P302) // D9 +#define MICROPY_HW_PWM_5B (pin_P202) // D12 +#define MICROPY_HW_PWM_5A (pin_P203) // D11 +// #define MICROPY_HW_PWM_4B (pin_P204) // D13 +// #define MICROPY_HW_PWM_4B (pin_P301) // D10 +#define MICROPY_HW_PWM_4B (pin_P608) // LED_Y +#define MICROPY_HW_PWM_7B (pin_P303) // D8 +// #define MICROPY_HW_PWM_7B (pin_P602) // PN4_3 +// #define MICROPY_HW_PWM_7A (pin_P304) // PN4_8 +#define MICROPY_HW_PWM_7A (pin_P603) // LED_R +#define MICROPY_HW_PWM_6B (pin_P600) // PN4_4 +#define MICROPY_HW_PWM_6A (pin_P601) // LED_G +#define MICROPY_HW_PWM_8B (pin_P604) // PN4_2 + +// DAC +#define MICROPY_HW_DAC0 (pin_P014) // A4 +#define MICROPY_HW_DAC1 (pin_P015) // A5 + +// Switch +#define MICROPY_HW_HAS_SWITCH (1) +#define MICROPY_HW_USRSW_PIN (pin_P008) +// #define MICROPY_HW_USRSW_PIN (pin_P009) +#define MICROPY_HW_USRSW_PULL (MP_HAL_PIN_PULL_NONE) +#define MICROPY_HW_USRSW_EXTI_MODE (MP_HAL_PIN_TRIGGER_FALLING) +#define MICROPY_HW_USRSW_PRESSED (0) + +// LEDs +#define MICROPY_HW_LED1 (pin_P603) +#define MICROPY_HW_LED2 (pin_P601) +#define MICROPY_HW_LED3 (pin_P605) +#define MICROPY_HW_LED4 (pin_P608) +#define MICROPY_HW_LED_ON(pin) mp_hal_pin_high(pin) +#define MICROPY_HW_LED_OFF(pin) mp_hal_pin_low(pin) +#define MICROPY_HW_LED_TOGGLE(pin) mp_hal_pin_toggle(pin) diff --git a/ports/renesas-ra/boards/VK_RA6M3/mpconfigboard.mk b/ports/renesas-ra/boards/VK_RA6M3/mpconfigboard.mk new file mode 100644 index 0000000000000..5069eb71e0c1e --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/mpconfigboard.mk @@ -0,0 +1,24 @@ +CMSIS_MCU = RA6M3 +MCU_SERIES = m4 +LD_FILES = boards/VK_RA6M3/vk_ra6m3.ld + +CFLAGS += -DCFG_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED \ + -DCFG_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED \ + -DCFG_TUSB_RHPORT0_MODE=OPT_MODE_DEVICE \ + -DCFG_TUSB_RHPORT1_MODE=0 + +# MicroPython settings +MICROPY_VFS_FAT = 1 +MICROPY_HW_ENABLE_RNG = 1 +MICROPY_PY_LWIP = 1 +MICROPY_PY_SSL = 1 +MICROPY_SSL_MBEDTLS = 1 + +# FSP settings +USE_FSP_QSPI = 1 +USE_FSP_SDHI = 1 +USE_FSP_ETH = 1 +USE_FSP_LCD = 1 +USE_FSP_CAM = 1 + +CFLAGS+=-DDEFAULT_DBG_CH=9 diff --git a/ports/renesas-ra/boards/VK_RA6M3/pins.csv b/ports/renesas-ra/boards/VK_RA6M3/pins.csv new file mode 100644 index 0000000000000..29d63b35cbe3e --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/pins.csv @@ -0,0 +1,168 @@ +P000,P000 +P001,P001 +P002,P002 +P003,P003 +P004,P004 +P005,P005 +P006,P006 +P007,P007 +P008,P008 +P009,P009 +P010,P010 +P014,P014 +P015,P015 +P100,P100 +P101,P101 +P102,P102 +P103,P103 +P104,P104 +P105,P105 +P106,P106 +P107,P107 +P108,P108 +P109,P109 +P110,P110 +P111,P111 +P112,P112 +P113,P113 +P114,P114 +P115,P115 +P200,P200 +P201,P201 +P202,P202 +P203,P203 +P204,P204 +P205,P205 +P206,P206 +P207,P207 +P208,P208 +P209,P209 +P210,P210 +P211,P211 +P212,P212 +P213,P213 +P214,P214 +P300,P300 +P301,P301 +P302,P302 +P303,P303 +P304,P304 +P305,P305 +P306,P306 +P307,P307 +P308,P308 +P309,P309 +P310,P310 +P311,P311 +P312,P312 +P313,P313 +P314,P314 +P315,P315 +P400,P400 +P401,P401 +P402,P402 +P403,P403 +P404,P404 +P405,P405 +P406,P406 +P407,P407 +P408,P408 +P409,P409 +P410,P410 +P411,P411 +P412,P412 +P413,P413 +P414,P414 +P415,P415 +P500,P500 +P501,P501 +P502,P502 +P503,P503 +P504,P504 +P505,P505 +P506,P506 +P507,P507 +P508,P508 +P511,P511 +P512,P512 +P513,P513 +P600,P600 +P601,P601 +P602,P602 +P603,P603 +P604,P604 +P605,P605 +P606,P606 +P607,P607 +P608,P608 +P609,P609 +P610,P610 +P611,P611 +P612,P612 +P613,P613 +P614,P614 +P615,P615 +P700,P700 +P701,P701 +P702,P702 +P703,P703 +P704,P704 +P705,P705 +P706,P706 +P707,P707 +P708,P708 +P800,P800 +P801,P801 +P802,P802 +P803,P803 +P804,P804 +P805,P805 +P806,P806 +P900,P900 +P901,P901 +P905,P905 +P906,P906 +P907,P907 +P908,P908 +PA00,PA00 +PA01,PA01 +PA08,PA08 +PA09,PA09 +PA10,PA10 +PB00,PB00 +PB01,PB01 +A0,P000 +A1,P001 +A2,P002 +A3,P003 +A4,P014 +A5,P015 +D0,P614 +D1,P613 +D2,P111 +D3,P112 +D4,P113 +D5,P114 +D6,P115 +D7,P107 +D8,P303 +D9,P302 +D10,P301 +D11,P203 +D12,P202 +D13,P204 +SW1,P008 +SW2,P009 +LED1,P605 +LED2,P601 +LED3,P603 +LED4,P608 +SDA1,P206 +SCL1,P205 +SWDIO,P108 +SWCLK,P300 +MD,P201 +LED_G,P601 +LED_R,P603 +LED_B,P605 +LED_Y,P608 diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/driver/r_qspi_cfg.h b/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/driver/r_qspi_cfg.h new file mode 100644 index 0000000000000..ff436867fae9d --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/driver/r_qspi_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_QSPI_CFG_H_ +#define R_QSPI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define QSPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM (1) + +#ifdef __cplusplus +} +#endif +#endif /* R_QSPI_CFG_H_ */ diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/board_cfg.h b/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/board_cfg.h new file mode 100644 index 0000000000000..a57cf3249e386 --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/board_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +void bsp_init(void *p_args); + +#ifdef __cplusplus +} +#endif +#endif /* BOARD_CFG_H_ */ diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 0000000000000..c848a269c3e99 --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,62 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (2) +#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (1) +#else +#define BSP_CFG_RTOS (0) +#endif +#endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (1) +#endif +#undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) +#define BSP_CFG_BOOT_IMAGE (1) +#endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x4000) +#define BSP_CFG_HEAP_BYTES (0xA000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (0) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 0000000000000..bd6a901c32d6e --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (6) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 0000000000000..385a922fb5729 --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA6M3AH3CFC +#define BSP_MCU_FEATURE_SET ('A') +#define BSP_ROM_SIZE_BYTES (2097152) +#define BSP_RAM_SIZE_BYTES (655360) +#define BSP_DATA_FLASH_SIZE_BYTES (65536) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (176) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 0000000000000..46766b49717d4 --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,83 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" +#define BSP_MCU_GROUP_RA6M3 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 +#define BSP_HOCO_HZ (18000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 +#define BSP_HOCO_HZ (20000000) +#else +#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif + +#define BSP_CFG_FLL_ENABLE (0) + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector) + +/* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ +#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) +#define BSP_CFG_ID_CODE_LONG_1 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_2 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_3 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_4 (0x00000000) +#else +/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 0000000000000..d490707ca166b --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,25 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define ET_nRST (BSP_IO_PORT_04_PIN_00) +#define LED_G (BSP_IO_PORT_06_PIN_01) +#define LED_R (BSP_IO_PORT_06_PIN_03) +#define LED_B (BSP_IO_PORT_06_PIN_05) +#define LED_Y (BSP_IO_PORT_06_PIN_08) +#define CMR_PWDN (BSP_IO_PORT_06_PIN_11) +#define CMR_RST (BSP_IO_PORT_06_PIN_12) +#define LCD_BLON (BSP_IO_PORT_08_PIN_01) +#define LCD_DISP (BSP_IO_PORT_08_PIN_06) +extern const ioport_cfg_t g_bsp_pin_cfg; /* VK_RA6M3.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* BSP_PIN_CFG_H_ */ diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_gen/bsp_clock_cfg.h b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/bsp_clock_cfg.h new file mode 100644 index 0000000000000..c998ad53ce842 --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,24 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(20U, 0U) /* PLL Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_SDCLK_OUTPUT (1) /* SDCLK Enabled */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_gen/common_data.c b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/common_data.c new file mode 100644 index 0000000000000..58bf7c1b8ec7e --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/common_data.c @@ -0,0 +1,91 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +icu_instance_ctrl_t g_external_irq13_ctrl; +const external_irq_cfg_t g_external_irq13_cfg = { .channel = 13, .trigger = + EXTERNAL_IRQ_TRIG_RISING, .filter_enable = false, .pclk_div = + EXTERNAL_IRQ_PCLK_DIV_BY_64, .p_callback = callback_icu, +/** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = NULL, .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ13) + .irq = VECTOR_NUMBER_ICU_IRQ13, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq13 = { .p_ctrl = + &g_external_irq13_ctrl, .p_cfg = &g_external_irq13_cfg, .p_api = + &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq12_ctrl; +const external_irq_cfg_t g_external_irq12_cfg = { .channel = 12, .trigger = + EXTERNAL_IRQ_TRIG_RISING, .filter_enable = false, .pclk_div = + EXTERNAL_IRQ_PCLK_DIV_BY_64, .p_callback = callback_icu, +/** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = NULL, .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ12) + .irq = VECTOR_NUMBER_ICU_IRQ12, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq12 = { .p_ctrl = + &g_external_irq12_ctrl, .p_cfg = &g_external_irq12_cfg, .p_api = + &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq11_ctrl; +const external_irq_cfg_t g_external_irq11_cfg = { .channel = 11, .trigger = + EXTERNAL_IRQ_TRIG_RISING, .filter_enable = false, .pclk_div = + EXTERNAL_IRQ_PCLK_DIV_BY_64, .p_callback = callback_icu, +/** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = NULL, .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ11) + .irq = VECTOR_NUMBER_ICU_IRQ11, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq11 = { .p_ctrl = + &g_external_irq11_ctrl, .p_cfg = &g_external_irq11_cfg, .p_api = + &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq7_ctrl; +const external_irq_cfg_t g_external_irq7_cfg = { .channel = 7, .trigger = + EXTERNAL_IRQ_TRIG_RISING, .filter_enable = false, .pclk_div = + EXTERNAL_IRQ_PCLK_DIV_BY_64, .p_callback = callback_icu, +/** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = NULL, .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ7) + .irq = VECTOR_NUMBER_ICU_IRQ7, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq7 = { .p_ctrl = + &g_external_irq7_ctrl, .p_cfg = &g_external_irq7_cfg, .p_api = + &g_external_irq_on_icu }; +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = { .p_api = &g_ioport_on_ioport, .p_ctrl = + &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, }; +void g_common_init(void) { +} diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_gen/common_data.h b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/common_data.h new file mode 100644 index 0000000000000..ad5ef95f4d797 --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/common_data.h @@ -0,0 +1,58 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_icu.h" +#include "r_external_irq_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq13; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq13_ctrl; +extern const external_irq_cfg_t g_external_irq13_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq12; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq12_ctrl; +extern const external_irq_cfg_t g_external_irq12_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq11; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq11_ctrl; +extern const external_irq_cfg_t g_external_irq11_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq7; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq7_ctrl; +extern const external_irq_cfg_t g_external_irq7_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_gen/hal_data.c b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/hal_data.c new file mode 100644 index 0000000000000..a8cbfd279fa53 --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/hal_data.c @@ -0,0 +1,1558 @@ +/* generated HAL source file - do not edit */ +#include "hal_data.h" + +/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */ +#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC +usb_instance_ctrl_t g_basic0_ctrl; + +#if !defined(g_usb_descriptor) +extern usb_descriptor_t g_usb_descriptor; +#endif +#define RA_NOT_DEFINED (1) +const usb_cfg_t g_basic0_cfg = { .usb_mode = USB_MODE_PERI, .usb_speed = + USB_SPEED_FS, .module_number = 0, .type = USB_CLASS_PCDC, + #if defined(g_usb_descriptor) + .p_usb_reg = g_usb_descriptor, + #else + .p_usb_reg = &g_usb_descriptor, + #endif + .usb_complience_cb = NULL, + #if defined(VECTOR_NUMBER_USBFS_INT) + .irq = VECTOR_NUMBER_USBFS_INT, + #else + .irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_USBFS_RESUME) + .irq_r = VECTOR_NUMBER_USBFS_RESUME, + #else + .irq_r = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_USBFS_FIFO_0) + .irq_d0 = VECTOR_NUMBER_USBFS_FIFO_0, + #else + .irq_d0 = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_USBFS_FIFO_1) + .irq_d1 = VECTOR_NUMBER_USBFS_FIFO_1, + #else + .irq_d1 = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_USBHS_USB_INT_RESUME) + .hsirq = VECTOR_NUMBER_USBHS_USB_INT_RESUME, + #else + .hsirq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_USBHS_FIFO_0) + .hsirq_d0 = VECTOR_NUMBER_USBHS_FIFO_0, + #else + .hsirq_d0 = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_USBHS_FIFO_1) + .hsirq_d1 = VECTOR_NUMBER_USBHS_FIFO_1, + #else + .hsirq_d1 = FSP_INVALID_VECTOR, + #endif + .ipl = (12), .ipl_r = (12), .ipl_d0 = (12), .ipl_d1 = (12), .hsipl = + (12), .hsipl_d0 = (12), .hsipl_d1 = (12), + #if (BSP_CFG_RTOS != 0) + .p_usb_apl_callback = NULL, + #else + .p_usb_apl_callback = NULL, + #endif + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +}; +#undef RA_NOT_DEFINED + +/* Instance structure to use this module. */ +const usb_instance_t g_basic0 = { .p_ctrl = &g_basic0_ctrl, .p_cfg = + &g_basic0_cfg, .p_api = &g_usb_on_usb, }; + +#if JPEG_CFG_ENCODE_ENABLE + +/* Luminance quantization table */ static const uint8_t quant_table_0[] = {16, 11, 10, 16, 24, 40, 51, 61, 12, 12, 14, 19, 26, 58, 60, 55, 14, 13, 16, 24, 40, 57, 69, 56, 14, 17, 22, 29, 51, 87, 80, 62, 18, 22, 37, 56, 68, 109, 103, 77, 24, 35, 55, 64, 81, 104, 113, 92, 49, 64, 78, 87, 103, 121, 120, 101, 72, 92, 95, 98, 112, 100, 103, 99, }; /* Chrominance quantization table */ static const uint8_t quant_table_1[] = {17, 18, 24, 47, 99, 99, 99, 99, 18, 21, 26, 66, 99, 99, 99, 99, 24, 26, 56, 99, 99, 99, 99, 99, 47, 66, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, }; + +/* Luminance DC coefficients */ +static const uint8_t huffm_dc_table_0[] = +{ + /* Table K.3 ITU-T81 specification */ + 0x00, 0x01, 0x05, 0x01, + 0x01, 0x01, 0x01, 0x01, + 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x02, 0x03, + 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, +}; + +/* Chrominance DC coefficients */ +static const uint8_t huffm_dc_table_1[] = +{ + /* Table K.4 ITU-T81 specification */ + 0x00, 0x03, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x02, 0x03, + 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, +}; + +/* Luminance AC coefficients */ +static const uint8_t huffm_ac_table_0[] = +{ + /* Table K.5 ITU-T81 specification */ + 0x00, 0x02, 0x01, 0x03, + 0x03, 0x02, 0x04, 0x03, + 0x05, 0x05, 0x04, 0x04, + 0x00, 0x00, 0x01, 0x7D, + 0x01, 0x02, 0x03, 0x00, + 0x04, 0x11, 0x05, 0x12, + 0x21, 0x31, 0x41, 0x06, + 0x13, 0x51, 0x61, 0x07, + 0x22, 0x71, 0x14, 0x32, + 0x81, 0x91, 0xA1, 0x08, + 0x23, 0x42, 0xB1, 0xC1, + 0x15, 0x52, 0xD1, 0xF0, + 0x24, 0x33, 0x62, 0x72, + 0x82, 0x09, 0x0A, 0x16, + 0x17, 0x18, 0x19, 0x1A, + 0x25, 0x26, 0x27, 0x28, + 0x29, 0x2A, 0x34, 0x35, + 0x36, 0x37, 0x38, 0x39, + 0x3A, 0x43, 0x44, 0x45, + 0x46, 0x47, 0x48, 0x49, + 0x4A, 0x53, 0x54, 0x55, + 0x56, 0x57, 0x58, 0x59, + 0x5A, 0x63, 0x64, 0x65, + 0x66, 0x67, 0x68, 0x69, + 0x6A, 0x73, 0x74, 0x75, + 0x76, 0x77, 0x78, 0x79, + 0x7A, 0x83, 0x84, 0x85, + 0x86, 0x87, 0x88, 0x89, + 0x8A, 0x92, 0x93, 0x94, + 0x95, 0x96, 0x97, 0x98, + 0x99, 0x9A, 0xA2, 0xA3, + 0xA4, 0xA5, 0xA6, 0xA7, + 0xA8, 0xA9, 0xAA, 0xB2, + 0xB3, 0xB4, 0xB5, 0xB6, + 0xB7, 0xB8, 0xB9, 0xBA, + 0xC2, 0xC3, 0xC4, 0xC5, + 0xC6, 0xC7, 0xC8, 0xC9, + 0xCA, 0xD2, 0xD3, 0xD4, + 0xD5, 0xD6, 0xD7, 0xD8, + 0xD9, 0xDA, 0xE1, 0xE2, + 0xE3, 0xE4, 0xE5, 0xE6, + 0xE7, 0xE8, 0xE9, 0xEA, + 0xF1, 0xF2, 0xF3, 0xF4, + 0xF5, 0xF6, 0xF7, 0xF8, + 0xF9, 0xFA, +}; + +/* Chrominance AC coefficients */ +static const uint8_t huffm_ac_table_1[] = +{ + /* Table K.6 ITU-T81 specification */ + 0x00, 0x02, 0x01, 0x02, + 0x04, 0x04, 0x03, 0x04, + 0x07, 0x05, 0x04, 0x04, + 0x00, 0x01, 0x02, 0x77, + 0x00, 0x01, 0x02, 0x03, + 0x11, 0x04, 0x05, 0x21, + 0x31, 0x06, 0x12, 0x41, + 0x51, 0x07, 0x61, 0x71, + 0x13, 0x22, 0x32, 0x81, + 0x08, 0x14, 0x42, 0x91, + 0xA1, 0xB1, 0xC1, 0x09, + 0x23, 0x33, 0x52, 0xF0, + 0x15, 0x62, 0x72, 0xD1, + 0x0A, 0x16, 0x24, 0x34, + 0xE1, 0x25, 0xF1, 0x17, + 0x18, 0x19, 0x1A, 0x26, + 0x27, 0x28, 0x29, 0x2A, + 0x35, 0x36, 0x37, 0x38, + 0x39, 0x3A, 0x43, 0x44, + 0x45, 0x46, 0x47, 0x48, + 0x49, 0x4A, 0x53, 0x54, + 0x55, 0x56, 0x57, 0x58, + 0x59, 0x5A, 0x63, 0x64, + 0x65, 0x66, 0x67, 0x68, + 0x69, 0x6A, 0x73, 0x74, + 0x75, 0x76, 0x77, 0x78, + 0x79, 0x7A, 0x82, 0x83, + 0x84, 0x85, 0x86, 0x87, + 0x88, 0x89, 0x8A, 0x92, + 0x93, 0x94, 0x95, 0x96, + 0x97, 0x98, 0x99, 0x9A, + 0xA2, 0xA3, 0xA4, 0xA5, + 0xA6, 0xA7, 0xA8, 0xA9, + 0xAA, 0xB2, 0xB3, 0xB4, + 0xB5, 0xB6, 0xB7, 0xB8, + 0xB9, 0xBA, 0xC2, 0xC3, + 0xC4, 0xC5, 0xC6, 0xC7, + 0xC8, 0xC9, 0xCA, 0xD2, + 0xD3, 0xD4, 0xD5, 0xD6, + 0xD7, 0xD8, 0xD9, 0xDA, + 0xE2, 0xE3, 0xE4, 0xE5, + 0xE6, 0xE7, 0xE8, 0xE9, + 0xEA, 0xF2, 0xF3, 0xF4, + 0xF5, 0xF6, 0xF7, 0xF8, + 0xF9, 0xFA, +}; +#endif + +jpeg_instance_ctrl_t g_jpeg0_ctrl; +const jpeg_cfg_t g_jpeg0_cfg = { .jedi_ipl = (12), .jdti_ipl = (12), + #if defined(VECTOR_NUMBER_JPEG_JEDI) + .jedi_irq = VECTOR_NUMBER_JPEG_JEDI, + #else + .jedi_irq = FSP_INVALID_VECTOR, + #endif + .jdti_irq = VECTOR_NUMBER_JPEG_JDTI, + + #if JPEG_CFG_DECODE_ENABLE && JPEG_CFG_ENCODE_ENABLE + .default_mode = (JPEG_MODE_ENCODE), + #endif + + #if JPEG_CFG_DECODE_ENABLE + .decode_input_data_order = JPEG_DATA_ORDER_NORMAL, + .decode_output_data_order = JPEG_DATA_ORDER_NORMAL, + .pixel_format = JPEG_DECODE_PIXEL_FORMAT_RGB565, + .alpha_value = 255, + .p_decode_callback = NULL, + .p_decode_context = NULL, + #endif + + #if JPEG_CFG_ENCODE_ENABLE + .encode_input_data_order = JPEG_DATA_ORDER_NORMAL, + .encode_output_data_order = JPEG_DATA_ORDER_NORMAL, + .dri_marker = 0, + .horizontal_resolution = 320, + .vertical_resolution = 240, + .horizontal_stride_pixels = 640, + .p_quant_luma_table = quant_table_0, + .p_quant_chroma_table = quant_table_1, + .p_huffman_luma_ac_table = huffm_ac_table_0, + .p_huffman_luma_dc_table = huffm_dc_table_0, + .p_huffman_chroma_ac_table = huffm_ac_table_1, + .p_huffman_chroma_dc_table = huffm_dc_table_1, + .p_encode_callback = jpg_ISR, + .p_encode_context = NULL, + #endif +}; + +const jpeg_instance_t g_jpeg0 = { .p_api = (jpeg_api_t const *)&g_jpeg_on_jpeg, + .p_ctrl = &g_jpeg0_ctrl, .p_cfg = &g_jpeg0_cfg }; +dtc_instance_ctrl_t g_transfer5_ctrl; + +transfer_info_t g_transfer5_info = { .transfer_settings_word_b.dest_addr_mode = + TRANSFER_ADDR_MODE_INCREMENTED, .transfer_settings_word_b.repeat_area = + TRANSFER_REPEAT_AREA_SOURCE, .transfer_settings_word_b.irq = + TRANSFER_IRQ_END, .transfer_settings_word_b.chain_mode = + TRANSFER_CHAIN_MODE_DISABLED, .transfer_settings_word_b.src_addr_mode = + TRANSFER_ADDR_MODE_FIXED, .transfer_settings_word_b.size = + TRANSFER_SIZE_4_BYTE, .transfer_settings_word_b.mode = + TRANSFER_MODE_BLOCK, .p_dest = (void *)NULL, + .p_src = (void const *)NULL, .num_blocks = 1, .length = 8, }; + +const dtc_extended_cfg_t g_transfer5_cfg_extend = { .activation_source = + VECTOR_NUMBER_PDC_RECEIVE_DATA_READY, }; +const transfer_cfg_t g_transfer5_cfg = { .p_info = &g_transfer5_info, + .p_extend = &g_transfer5_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer5 = { .p_ctrl = &g_transfer5_ctrl, .p_cfg = + &g_transfer5_cfg, .p_api = &g_transfer_on_dtc }; +#define RA_NOT_DEFINED (UINT32_MAX) +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void r_pdc_transfer_callback(pdc_instance_ctrl_t *p_ctrl); + +void g_cam0_transfer_callback(dmac_callback_args_t *p_args) { + r_pdc_transfer_callback((pdc_instance_ctrl_t *)p_args->p_context); +} +#endif +#undef RA_NOT_DEFINED +#if PDC_ON_PDC_BUFFER_USED_g_cam0 +uint8_t g_cam_buffer[1][320 * 240 * 2] BSP_ALIGN_VARIABLE(32) BSP_PLACE_IN_SECTION(".noinit"); +#endif +pdc_instance_ctrl_t g_cam0_ctrl; +pdc_cfg_t g_cam0_cfg = { .bytes_per_pixel = 2, .clock_division = + PDC_CLOCK_DIVISION_6, .endian = PDC_ENDIAN_LITTLE, .hsync_polarity = + PDC_HSYNC_POLARITY_HIGH, .vsync_polarity = PDC_VSYNC_POLARITY_LOW, + .p_buffer = (uint8_t *)g_cam_buffer, .p_callback = cam_ISR, + /** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = NULL, .p_lower_lvl_transfer = &g_transfer5, + .x_capture_pixels = 320, .y_capture_pixels = 240, + .x_capture_start_pixel = 192, .y_capture_start_pixel = 26, .pdc_ipl = + (1), .transfer_req_ipl = (1), + #if defined(VECTOR_NUMBER_PDC_INT) + .pdc_irq = VECTOR_NUMBER_PDC_INT, + #else + .pdc_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_PDC_RECEIVE_DATA_READY) + .transfer_req_irq = VECTOR_NUMBER_PDC_RECEIVE_DATA_READY, + #else + .transfer_req_irq = FSP_INVALID_VECTOR, + #endif +}; + +const pdc_instance_t g_cam0 = { .p_ctrl = &g_cam0_ctrl, .p_cfg = &g_cam0_cfg, + .p_api = &g_pdc_on_pdc, }; +dtc_instance_ctrl_t g_transfer4_ctrl; + +transfer_info_t g_transfer4_info = { .transfer_settings_word_b.dest_addr_mode = + TRANSFER_ADDR_MODE_INCREMENTED, .transfer_settings_word_b.repeat_area = + TRANSFER_REPEAT_AREA_DESTINATION, .transfer_settings_word_b.irq = + TRANSFER_IRQ_END, .transfer_settings_word_b.chain_mode = + TRANSFER_CHAIN_MODE_DISABLED, .transfer_settings_word_b.src_addr_mode = + TRANSFER_ADDR_MODE_FIXED, .transfer_settings_word_b.size = + TRANSFER_SIZE_1_BYTE, .transfer_settings_word_b.mode = + TRANSFER_MODE_NORMAL, .p_dest = (void *)NULL, .p_src = + (void const *)NULL, .num_blocks = 0, .length = 0, }; + +const dtc_extended_cfg_t g_transfer4_cfg_extend = { .activation_source = + VECTOR_NUMBER_SCI0_RXI, }; +const transfer_cfg_t g_transfer4_cfg = { .p_info = &g_transfer4_info, + .p_extend = &g_transfer4_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer4 = { .p_ctrl = &g_transfer4_ctrl, .p_cfg = + &g_transfer4_cfg, .p_api = &g_transfer_on_dtc }; +dtc_instance_ctrl_t g_transfer3_ctrl; + +transfer_info_t g_transfer3_info = { .transfer_settings_word_b.dest_addr_mode = + TRANSFER_ADDR_MODE_FIXED, .transfer_settings_word_b.repeat_area = + TRANSFER_REPEAT_AREA_SOURCE, .transfer_settings_word_b.irq = + TRANSFER_IRQ_END, .transfer_settings_word_b.chain_mode = + TRANSFER_CHAIN_MODE_DISABLED, .transfer_settings_word_b.src_addr_mode = + TRANSFER_ADDR_MODE_INCREMENTED, .transfer_settings_word_b.size = + TRANSFER_SIZE_1_BYTE, .transfer_settings_word_b.mode = + TRANSFER_MODE_NORMAL, .p_dest = (void *)NULL, .p_src = + (void const *)NULL, .num_blocks = 0, .length = 0, }; + +const dtc_extended_cfg_t g_transfer3_cfg_extend = { .activation_source = + VECTOR_NUMBER_SCI0_TXI, }; +const transfer_cfg_t g_transfer3_cfg = { .p_info = &g_transfer3_info, + .p_extend = &g_transfer3_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer3 = { .p_ctrl = &g_transfer3_ctrl, .p_cfg = + &g_transfer3_cfg, .p_api = &g_transfer_on_dtc }; +#include "r_sci_i2c_cfg.h" +sci_i2c_instance_ctrl_t g_i2c_touch_ctrl; +const sci_i2c_extended_cfg_t g_i2c_touch_cfg_extend = +{ + /* Actual calculated bitrate: 399693. Actual SDA delay: 300 ns. */ .clock_settings.clk_divisor_value = + 0, .clock_settings.brr_value = 6, + .clock_settings.mddr_value = 191, + .clock_settings.bitrate_modulation = true, + .clock_settings.cycles_value = 31, .clock_settings.snfr_value = + (1), +}; + +const i2c_master_cfg_t g_i2c_touch_cfg = { .channel = 0, .rate = + I2C_MASTER_RATE_FAST, .slave = 0x38, .addr_mode = + I2C_MASTER_ADDR_MODE_7BIT, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == g_transfer3) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &g_transfer3, + #endif + #if (RA_NOT_DEFINED == g_transfer4) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &g_transfer4, + #endif +#undef RA_NOT_DEFINED + .p_callback = touch_i2c_callback, .p_context = NULL, + #if defined(VECTOR_NUMBER_SCI0_RXI) && SCI_I2C_CFG_DTC_ENABLE + .rxi_irq = VECTOR_NUMBER_SCI0_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI0_TXI) + .txi_irq = VECTOR_NUMBER_SCI0_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI0_TEI) + .tei_irq = VECTOR_NUMBER_SCI0_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + .ipl = (6), /* (6) is unused */ + .p_extend = &g_i2c_touch_cfg_extend, }; +/* Instance structure to use this module. */ +const i2c_master_instance_t g_i2c_touch = { .p_ctrl = &g_i2c_touch_ctrl, + .p_cfg = &g_i2c_touch_cfg, .p_api = &g_i2c_master_on_sci }; +/** Display framebuffer */ +#if GLCDC_CFG_LAYER_1_ENABLE +uint8_t fb_background[1][DISPLAY_BUFFER_STRIDE_BYTES_INPUT0 * DISPLAY_VSIZE_INPUT0] BSP_ALIGN_VARIABLE(64) BSP_PLACE_IN_SECTION(".fb0"); +#else +/** Graphics Layer 1 is specified not to be used when starting */ +#endif +#if GLCDC_CFG_LAYER_2_ENABLE +uint8_t fb_foreground[2][DISPLAY_BUFFER_STRIDE_BYTES_INPUT1 * DISPLAY_VSIZE_INPUT1] BSP_ALIGN_VARIABLE(64) BSP_PLACE_IN_SECTION(".bss"); +#else +/** Graphics Layer 2 is specified not to be used when starting */ +#endif + +#if GLCDC_CFG_CLUT_ENABLE +/** Display CLUT buffer to be used for updating CLUT */ +static uint32_t CLUT_buffer[256]; + +/** Display CLUT configuration(only used if using CLUT format) */ +display_clut_cfg_t g_display0_clut_cfg_glcdc = +{ + .p_base = (uint32_t *)CLUT_buffer, + .start = 0, /* User have to update this setting when using */ + .size = 256 /* User have to update this setting when using */ +}; +#else +/** CLUT is specified not to be used */ +#endif + +#if (false) +#define GLCDC_CFG_CORRECTION_GAMMA_TABLE_CONST const +#define GLCDC_CFG_CORRECTION_GAMMA_TABLE_CAST (uint16_t *) +#define GLCDC_CFG_CORRECTION_GAMMA_CFG_CAST (display_gamma_correction_t *) +#else +#define GLCDC_CFG_CORRECTION_GAMMA_TABLE_CONST +#define GLCDC_CFG_CORRECTION_GAMMA_TABLE_CAST +#define GLCDC_CFG_CORRECTION_GAMMA_CFG_CAST +#endif + +#if ((GLCDC_CFG_CORRECTION_GAMMA_ENABLE_R | GLCDC_CFG_CORRECTION_GAMMA_ENABLE_G | GLCDC_CFG_CORRECTION_GAMMA_ENABLE_B) && GLCDC_CFG_COLOR_CORRECTION_ENABLE) +/** Gamma correction tables */ + #if GLCDC_CFG_CORRECTION_GAMMA_ENABLE_R +static GLCDC_CFG_CORRECTION_GAMMA_TABLE_CONST uint16_t glcdc_gamma_r_gain[DISPLAY_GAMMA_CURVE_ELEMENT_NUM] = {1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024}; +static GLCDC_CFG_CORRECTION_GAMMA_TABLE_CONST uint16_t glcdc_gamma_r_threshold[DISPLAY_GAMMA_CURVE_ELEMENT_NUM] = {0, 64, 128, 192, 256, 320, 384, 448, 512, 576, 640, 704, 768, 832, 896, 960}; + #endif + #if GLCDC_CFG_CORRECTION_GAMMA_ENABLE_G +static GLCDC_CFG_CORRECTION_GAMMA_TABLE_CONST uint16_t glcdc_gamma_g_gain[DISPLAY_GAMMA_CURVE_ELEMENT_NUM] = {1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024}; +static GLCDC_CFG_CORRECTION_GAMMA_TABLE_CONST uint16_t glcdc_gamma_g_threshold[DISPLAY_GAMMA_CURVE_ELEMENT_NUM] = {0, 64, 128, 192, 256, 320, 384, 448, 512, 576, 640, 704, 768, 832, 896, 960}; + #endif + #if GLCDC_CFG_CORRECTION_GAMMA_ENABLE_B +static GLCDC_CFG_CORRECTION_GAMMA_TABLE_CONST uint16_t glcdc_gamma_b_gain[DISPLAY_GAMMA_CURVE_ELEMENT_NUM] = {1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024}; +static GLCDC_CFG_CORRECTION_GAMMA_TABLE_CONST uint16_t glcdc_gamma_b_threshold[DISPLAY_GAMMA_CURVE_ELEMENT_NUM] = {0, 64, 128, 192, 256, 320, 384, 448, 512, 576, 640, 704, 768, 832, 896, 960}; + #endif +GLCDC_CFG_CORRECTION_GAMMA_TABLE_CONST display_gamma_correction_t g_display0_gamma_cfg = +{ + .r = + { + .enable = GLCDC_CFG_CORRECTION_GAMMA_ENABLE_R, + #if GLCDC_CFG_CORRECTION_GAMMA_ENABLE_R + .gain = GLCDC_CFG_CORRECTION_GAMMA_TABLE_CAST glcdc_gamma_r_gain, + .threshold = GLCDC_CFG_CORRECTION_GAMMA_TABLE_CAST glcdc_gamma_r_threshold + #else + .gain = NULL, + .threshold = NULL + #endif + }, + .g = + { + .enable = GLCDC_CFG_CORRECTION_GAMMA_ENABLE_G, + #if GLCDC_CFG_CORRECTION_GAMMA_ENABLE_G + .gain = GLCDC_CFG_CORRECTION_GAMMA_TABLE_CAST glcdc_gamma_g_gain, + .threshold = GLCDC_CFG_CORRECTION_GAMMA_TABLE_CAST glcdc_gamma_g_threshold + #else + .gain = NULL, + .threshold = NULL + #endif + }, + .b = + { + .enable = GLCDC_CFG_CORRECTION_GAMMA_ENABLE_B, + #if GLCDC_CFG_CORRECTION_GAMMA_ENABLE_B + .gain = GLCDC_CFG_CORRECTION_GAMMA_TABLE_CAST glcdc_gamma_b_gain, + .threshold = GLCDC_CFG_CORRECTION_GAMMA_TABLE_CAST glcdc_gamma_b_threshold + #else + .gain = NULL, + .threshold = NULL + #endif + } +}; +#endif + +/** Display device extended configuration */ +const glcdc_extended_cfg_t g_display0_extend_cfg = { .tcon_hsync = + GLCDC_TCON_PIN_0, .tcon_vsync = GLCDC_TCON_PIN_1, .tcon_de = + GLCDC_TCON_PIN_2, .correction_proc_order = + GLCDC_CORRECTION_PROC_ORDER_BRIGHTNESS_CONTRAST2GAMMA, .clksrc = + GLCDC_CLK_SRC_INTERNAL, .clock_div_ratio = GLCDC_PANEL_CLK_DIVISOR_24, + .dithering_mode = GLCDC_DITHERING_MODE_TRUNCATE, .dithering_pattern_A = + GLCDC_DITHERING_PATTERN_11, .dithering_pattern_B = + GLCDC_DITHERING_PATTERN_11, .dithering_pattern_C = + GLCDC_DITHERING_PATTERN_11, .dithering_pattern_D = + GLCDC_DITHERING_PATTERN_11 }; + +/** Display control block instance */ +glcdc_instance_ctrl_t g_display0_ctrl; + +/** Display interface configuration */ +const display_cfg_t g_display0_cfg = +{ + /** Input1(Graphics1 layer) configuration */ + .input[0] = + { + #if GLCDC_CFG_LAYER_1_ENABLE + .p_base = (uint32_t *)&fb_background[0], + #else + .p_base = NULL, + #endif + .hsize = DISPLAY_HSIZE_INPUT0, .vsize = DISPLAY_VSIZE_INPUT0, + .hstride = DISPLAY_BUFFER_STRIDE_PIXELS_INPUT0, .format = + DISPLAY_IN_FORMAT_16BITS_RGB565, + .line_descending_enable = false, .lines_repeat_enable = false, + .lines_repeat_times = 0 + }, + + /** Input2(Graphics2 layer) configuration */ + .input[1] = + { + #if GLCDC_CFG_LAYER_2_ENABLE + .p_base = (uint32_t *)&fb_foreground[0], + #else + .p_base = NULL, + #endif + .hsize = DISPLAY_HSIZE_INPUT1, .vsize = DISPLAY_VSIZE_INPUT1, + .hstride = DISPLAY_BUFFER_STRIDE_PIXELS_INPUT1, .format = + DISPLAY_IN_FORMAT_16BITS_RGB565, + .line_descending_enable = false, .lines_repeat_enable = false, + .lines_repeat_times = 0 + }, + + /** Input1(Graphics1 layer) layer configuration */ + .layer[0] = + { .coordinate = { .x = 0, .y = 0 }, .bg_color = { .byte = { .a = 255, + .r = 255, .g = 255, .b = 255 } }, .fade_control = + DISPLAY_FADE_CONTROL_NONE, .fade_speed = 0 }, + + /** Input2(Graphics2 layer) layer configuration */ + .layer[1] = + { .coordinate = { .x = 0, .y = 0 }, .bg_color = { .byte = { .a = 255, + .r = 255, .g = 255, .b = 255 } }, .fade_control = + DISPLAY_FADE_CONTROL_NONE, .fade_speed = 0 }, + + /** Output configuration */ + .output = + { .htiming = { .total_cyc = 525, .display_cyc = 480, + .back_porch = 40, .sync_width = 1, + .sync_polarity = + DISPLAY_SIGNAL_POLARITY_LOACTIVE }, + .vtiming = + { .total_cyc = 316, .display_cyc = 272, + .back_porch = 8, + .sync_width = 1, + .sync_polarity = + DISPLAY_SIGNAL_POLARITY_LOACTIVE }, + .format = DISPLAY_OUT_FORMAT_24BITS_RGB888, + .endian = DISPLAY_ENDIAN_LITTLE, .color_order = + DISPLAY_COLOR_ORDER_RGB, + .data_enable_polarity = + DISPLAY_SIGNAL_POLARITY_HIACTIVE, + .sync_edge = DISPLAY_SIGNAL_SYNC_EDGE_RISING, + .bg_color = { .byte = { .a = 255, .r = 0, .g = + 255, .b = 0 } }, + #if (GLCDC_CFG_COLOR_CORRECTION_ENABLE) + .brightness = + { + .enable = false, + .r = 512, + .g = 512, + .b = 512 + }, + .contrast = + { + .enable = false, + .r = 128, + .g = 128, + .b = 128 + }, + #if (GLCDC_CFG_CORRECTION_GAMMA_ENABLE_R | GLCDC_CFG_CORRECTION_GAMMA_ENABLE_G | GLCDC_CFG_CORRECTION_GAMMA_ENABLE_B) + #if false + .p_gamma_correction = GLCDC_CFG_CORRECTION_GAMMA_CFG_CAST(&g_display0_gamma_cfg), + #else + .p_gamma_correction = &g_display0_gamma_cfg, + #endif + #else + .p_gamma_correction = NULL, + #endif + #endif + .dithering_on = false }, + + /** Display device callback function pointer */ + .p_callback = lcd_Vsync_ISR, .p_context = NULL, + + /** Display device extended configuration */ + .p_extend = (void *)(&g_display0_extend_cfg), + + .line_detect_ipl = (2), .underflow_1_ipl = (BSP_IRQ_DISABLED), + .underflow_2_ipl = (BSP_IRQ_DISABLED), + + #if defined(VECTOR_NUMBER_GLCDC_LINE_DETECT) + .line_detect_irq = VECTOR_NUMBER_GLCDC_LINE_DETECT, + #else + .line_detect_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_GLCDC_UNDERFLOW_1) + .underflow_1_irq = VECTOR_NUMBER_GLCDC_UNDERFLOW_1, + #else + .underflow_1_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_GLCDC_UNDERFLOW_2) + .underflow_2_irq = VECTOR_NUMBER_GLCDC_UNDERFLOW_2, + #else + .underflow_2_irq = FSP_INVALID_VECTOR, + #endif +}; + +#if GLCDC_CFG_LAYER_1_ENABLE +/** Display on GLCDC run-time configuration(for the graphics1 layer) */ +display_runtime_cfg_t g_display0_runtime_cfg_bg = +{ + .input = + { + #if (true) + .p_base = (uint32_t *)&fb_background[0], + #else + .p_base = NULL, + #endif + .hsize = DISPLAY_HSIZE_INPUT0, + .vsize = DISPLAY_VSIZE_INPUT0, + .hstride = DISPLAY_BUFFER_STRIDE_PIXELS_INPUT0, + .format = DISPLAY_IN_FORMAT_16BITS_RGB565, + .line_descending_enable = false, + .lines_repeat_enable = false, + .lines_repeat_times = 0 + }, + .layer = + { + .coordinate = { + .x = 0, + .y = 0 + }, + .bg_color = + { + .byte = + { + .a = 255, + .r = 255, + .g = 255, + .b = 255 + } + }, + .fade_control = DISPLAY_FADE_CONTROL_NONE, + .fade_speed = 0 + } +}; +#endif +#if GLCDC_CFG_LAYER_2_ENABLE +/** Display on GLCDC run-time configuration(for the graphics2 layer) */ +display_runtime_cfg_t g_display0_runtime_cfg_fg = +{ + .input = + { + #if (false) + .p_base = (uint32_t *)&fb_foreground[0], + #else + .p_base = NULL, + #endif + .hsize = DISPLAY_HSIZE_INPUT1, + .vsize = DISPLAY_VSIZE_INPUT1, + .hstride = DISPLAY_BUFFER_STRIDE_PIXELS_INPUT1, + .format = DISPLAY_IN_FORMAT_16BITS_RGB565, + .line_descending_enable = false, + .lines_repeat_enable = false, + .lines_repeat_times = 0 + }, + .layer = + { + .coordinate = { + .x = 0, + .y = 0 + }, + .bg_color = + { + .byte = + { + .a = 255, + .r = 255, + .g = 255, + .b = 255 + } + }, + .fade_control = DISPLAY_FADE_CONTROL_NONE, + .fade_speed = 0 + } +}; +#endif + +/* Instance structure to use this module. */ +const display_instance_t g_display0 = { .p_ctrl = &g_display0_ctrl, .p_cfg = + (display_cfg_t *)&g_display0_cfg, .p_api = + (display_api_t *)&g_display_on_glcdc }; +ether_phy_instance_ctrl_t g_ether_phy0_ctrl; + +const ether_phy_cfg_t g_ether_phy0_cfg = { + + .channel = 0, .phy_lsi_address = 5, .phy_reset_wait_time = 0x00020000, + .mii_bit_access_wait_time = 8, .phy_lsi_type = + ETHER_PHY_LSI_TYPE_ICS1894, .flow_control = + ETHER_PHY_FLOW_CONTROL_DISABLE, .mii_type = + ETHER_PHY_MII_TYPE_RMII, .p_context = NULL, .p_extend = NULL, + +}; +/* Instance structure to use this module. */ +const ether_phy_instance_t g_ether_phy0 = { .p_ctrl = &g_ether_phy0_ctrl, + .p_cfg = &g_ether_phy0_cfg, .p_api = &g_ether_phy_on_ether_phy }; +ether_instance_ctrl_t g_ether0_ctrl; + +uint8_t g_ether0_mac_address[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 }; + +__attribute__((__aligned__(16))) ether_instance_descriptor_t g_ether0_tx_descriptors[4] ETHER_BUFFER_PLACE_IN_SECTION; +__attribute__((__aligned__(16))) ether_instance_descriptor_t g_ether0_rx_descriptors[4] ETHER_BUFFER_PLACE_IN_SECTION; + +__attribute__((__aligned__(32))) uint8_t g_ether0_ether_buffer0[1536] ETHER_BUFFER_PLACE_IN_SECTION; +__attribute__((__aligned__(32))) uint8_t g_ether0_ether_buffer1[1536] ETHER_BUFFER_PLACE_IN_SECTION; +__attribute__((__aligned__(32))) uint8_t g_ether0_ether_buffer2[1536] ETHER_BUFFER_PLACE_IN_SECTION; +__attribute__((__aligned__(32))) uint8_t g_ether0_ether_buffer3[1536] ETHER_BUFFER_PLACE_IN_SECTION; +__attribute__((__aligned__(32))) uint8_t g_ether0_ether_buffer4[1536] ETHER_BUFFER_PLACE_IN_SECTION; +__attribute__((__aligned__(32))) uint8_t g_ether0_ether_buffer5[1536] ETHER_BUFFER_PLACE_IN_SECTION; +__attribute__((__aligned__(32))) uint8_t g_ether0_ether_buffer6[1536] ETHER_BUFFER_PLACE_IN_SECTION; +__attribute__((__aligned__(32))) uint8_t g_ether0_ether_buffer7[1536] ETHER_BUFFER_PLACE_IN_SECTION; + +uint8_t *pp_g_ether0_ether_buffers[8] = { (uint8_t *)&g_ether0_ether_buffer0[0], + (uint8_t *)&g_ether0_ether_buffer1[0], + (uint8_t *)&g_ether0_ether_buffer2[0], + (uint8_t *)&g_ether0_ether_buffer3[0], + (uint8_t *)&g_ether0_ether_buffer4[0], + (uint8_t *)&g_ether0_ether_buffer5[0], + (uint8_t *)&g_ether0_ether_buffer6[0], + (uint8_t *)&g_ether0_ether_buffer7[0], }; + +const ether_extended_cfg_t g_ether0_extended_cfg_t = { .p_rx_descriptors = + g_ether0_rx_descriptors, .p_tx_descriptors = g_ether0_tx_descriptors, }; + +const ether_cfg_t g_ether0_cfg = { .channel = 0, .zerocopy = + ETHER_ZEROCOPY_DISABLE, .multicast = ETHER_MULTICAST_ENABLE, + .promiscuous = ETHER_PROMISCUOUS_DISABLE, .flow_control = + ETHER_FLOW_CONTROL_DISABLE, .padding = ETHER_PADDING_DISABLE, + .padding_offset = 1, .broadcast_filter = 0, .p_mac_address = + g_ether0_mac_address, + + .num_tx_descriptors = 4, .num_rx_descriptors = 4, + + .pp_ether_buffers = pp_g_ether0_ether_buffers, + + .ether_buffer_size = 1536, + + #if defined(VECTOR_NUMBER_EDMAC0_EINT) + .irq = VECTOR_NUMBER_EDMAC0_EINT, + #else + .irq = FSP_INVALID_VECTOR, + #endif + + .interrupt_priority = (12), + + .p_callback = ETH_IRQHandler, .p_ether_phy_instance = &g_ether_phy0, + .p_context = NULL, .p_extend = &g_ether0_extended_cfg_t, }; + +/* Instance structure to use this module. */ +const ether_instance_t g_ether0 = { .p_ctrl = &g_ether0_ctrl, .p_cfg = + &g_ether0_cfg, .p_api = &g_ether_on_ether }; +dtc_instance_ctrl_t g_transfer2_ctrl; + +transfer_info_t g_transfer2_info = { .transfer_settings_word_b.dest_addr_mode = + TRANSFER_ADDR_MODE_FIXED, .transfer_settings_word_b.repeat_area = + TRANSFER_REPEAT_AREA_SOURCE, .transfer_settings_word_b.irq = + TRANSFER_IRQ_END, .transfer_settings_word_b.chain_mode = + TRANSFER_CHAIN_MODE_DISABLED, .transfer_settings_word_b.src_addr_mode = + TRANSFER_ADDR_MODE_INCREMENTED, .transfer_settings_word_b.size = + TRANSFER_SIZE_4_BYTE, .transfer_settings_word_b.mode = + TRANSFER_MODE_NORMAL, .p_dest = (void *)NULL, .p_src = + (void const *)NULL, .num_blocks = 0, .length = 128, }; + +const dtc_extended_cfg_t g_transfer2_cfg_extend = { .activation_source = + VECTOR_NUMBER_SDHIMMC1_DMA_REQ, }; +const transfer_cfg_t g_transfer2_cfg = { .p_info = &g_transfer2_info, + .p_extend = &g_transfer2_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer2 = { .p_ctrl = &g_transfer2_ctrl, .p_cfg = + &g_transfer2_cfg, .p_api = &g_transfer_on_dtc }; +#define RA_NOT_DEFINED (UINT32_MAX) +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void r_sdhi_transfer_callback(sdhi_instance_ctrl_t *p_ctrl); + +void g_sdmmc0_dmac_callback(dmac_callback_args_t *p_args) { + r_sdhi_transfer_callback((sdhi_instance_ctrl_t *)p_args->p_context); +} +#endif +#undef RA_NOT_DEFINED + +sdhi_instance_ctrl_t g_sdmmc0_ctrl; +sdmmc_cfg_t g_sdmmc0_cfg = { .bus_width = SDMMC_BUS_WIDTH_4_BITS, .channel = 1, + .p_callback = sdhi_ISR, .p_context = NULL, .block_size = 512, + .card_detect = SDMMC_CARD_DETECT_CD, .write_protect = + SDMMC_WRITE_PROTECT_WP, + + .p_extend = NULL, .p_lower_lvl_transfer = &g_transfer2, + + .access_ipl = (12), .sdio_ipl = BSP_IRQ_DISABLED, .card_ipl = (12), + .dma_req_ipl = (12), + #if defined(VECTOR_NUMBER_SDHIMMC1_ACCS) + .access_irq = VECTOR_NUMBER_SDHIMMC1_ACCS, + #else + .access_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SDHIMMC1_CARD) + .card_irq = VECTOR_NUMBER_SDHIMMC1_CARD, + #else + .card_irq = FSP_INVALID_VECTOR, + #endif + .sdio_irq = FSP_INVALID_VECTOR, + #if defined(VECTOR_NUMBER_SDHIMMC1_DMA_REQ) + .dma_req_irq = VECTOR_NUMBER_SDHIMMC1_DMA_REQ, + #else + .dma_req_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const sdmmc_instance_t g_sdmmc0 = { .p_ctrl = &g_sdmmc0_ctrl, .p_cfg = + &g_sdmmc0_cfg, .p_api = &g_sdmmc_on_sdhi }; +qspi_instance_ctrl_t g_qspi0_ctrl; + +static const spi_flash_erase_command_t g_qspi0_erase_command_list[] = { + #if 4096 > 0 + { .command = 0x20, .size = 4096 }, + #endif + #if 32768 > 0 + { .command = 0x52, .size = 32768 }, + #endif + #if 65536 > 0 + { .command = 0xD8, .size = 65536 }, + #endif + #if 0xC7 > 0 + { .command = 0xC7, .size = SPI_FLASH_ERASE_SIZE_CHIP_ERASE }, + #endif +}; +static const qspi_extended_cfg_t g_qspi0_extended_cfg = { + .min_qssl_deselect_cycles = QSPI_QSSL_MIN_HIGH_LEVEL_9_QSPCLK, + .qspclk_div = QSPI_QSPCLK_DIV_2, +}; +const spi_flash_cfg_t g_qspi0_cfg = { .spi_protocol = + SPI_FLASH_PROTOCOL_EXTENDED_SPI, .read_mode = + SPI_FLASH_READ_MODE_FAST_READ_QUAD_IO, .address_bytes = + SPI_FLASH_ADDRESS_BYTES_3, .dummy_clocks = + SPI_FLASH_DUMMY_CLOCKS_DEFAULT, .page_program_address_lines = + SPI_FLASH_DATA_LINES_1, .page_size_bytes = 256, .page_program_command = + 0x32, .write_enable_command = 0x06, .status_command = 0x05, + .write_status_bit = 0, .xip_enter_command = 0x20, .xip_exit_command = + 0xFF, .p_erase_command_list = &g_qspi0_erase_command_list[0], + .erase_command_list_length = sizeof(g_qspi0_erase_command_list) + / sizeof(g_qspi0_erase_command_list[0]), .p_extend = + &g_qspi0_extended_cfg, }; +/** This structure encompasses everything that is needed to use an instance of this interface. */ +const spi_flash_instance_t g_qspi0 = { .p_ctrl = &g_qspi0_ctrl, .p_cfg = + &g_qspi0_cfg, .p_api = &g_qspi_on_spi_flash, }; +iic_master_instance_ctrl_t g_i2c_master1_ctrl; +const iic_master_extended_cfg_t g_i2c_master1_extend = +{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT, .timeout_scl_low = + IIC_MASTER_TIMEOUT_SCL_LOW_ENABLED, + /* Actual calculated bitrate: 98945. Actual calculated duty cycle: 51%. */ .clock_settings.brl_value = + 15, .clock_settings.brh_value = 16, + .clock_settings.cks_value = 4, }; +const i2c_master_cfg_t g_i2c_master1_cfg = { .channel = 1, .rate = + I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = + I2C_MASTER_ADDR_MODE_7BIT, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .p_callback = callback_iic, .p_context = NULL, + #if defined(VECTOR_NUMBER_IIC1_RXI) + .rxi_irq = VECTOR_NUMBER_IIC1_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC1_TXI) + .txi_irq = VECTOR_NUMBER_IIC1_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC1_TEI) + .tei_irq = VECTOR_NUMBER_IIC1_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC1_ERI) + .eri_irq = VECTOR_NUMBER_IIC1_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif + .ipl = (12), .p_extend = &g_i2c_master1_extend, }; +/* Instance structure to use this module. */ +const i2c_master_instance_t g_i2c_master1 = { .p_ctrl = &g_i2c_master1_ctrl, + .p_cfg = &g_i2c_master1_cfg, .p_api = &g_i2c_master_on_iic }; +adc_instance_ctrl_t g_adc1_ctrl; +const adc_extended_cfg_t g_adc1_cfg_extend = { .add_average_count = ADC_ADD_OFF, + .clearing = ADC_CLEAR_AFTER_READ_ON, .trigger_group_b = + ADC_TRIGGER_SYNC_ELC, .double_trigger_mode = + ADC_DOUBLE_TRIGGER_DISABLED, .adc_vref_control = + ADC_VREF_CONTROL_VREFH, .enable_adbuf = 0, + #if defined(VECTOR_NUMBER_ADC1_WINDOW_A) + .window_a_irq = VECTOR_NUMBER_ADC1_WINDOW_A, + #else + .window_a_irq = FSP_INVALID_VECTOR, + #endif + .window_a_ipl = (BSP_IRQ_DISABLED), + #if defined(VECTOR_NUMBER_ADC1_WINDOW_B) + .window_b_irq = VECTOR_NUMBER_ADC1_WINDOW_B, + #else + .window_b_irq = FSP_INVALID_VECTOR, + #endif + .window_b_ipl = (BSP_IRQ_DISABLED), }; +const adc_cfg_t g_adc1_cfg = { .unit = 1, .mode = ADC_MODE_SINGLE_SCAN, + .resolution = ADC_RESOLUTION_12_BIT, .alignment = + (adc_alignment_t)ADC_ALIGNMENT_RIGHT, .trigger = + ADC_TRIGGER_SOFTWARE, .p_callback = NULL, + /** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = &g_adc1_cfg_extend, + #if defined(VECTOR_NUMBER_ADC1_SCAN_END) + .scan_end_irq = VECTOR_NUMBER_ADC1_SCAN_END, + #else + .scan_end_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_ipl = (BSP_IRQ_DISABLED), + #if defined(VECTOR_NUMBER_ADC1_SCAN_END_B) + .scan_end_b_irq = VECTOR_NUMBER_ADC1_SCAN_END_B, + #else + .scan_end_b_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; +#if ((0) | (0)) +const adc_window_cfg_t g_adc1_window_cfg = +{ + .compare_mask = 0, + .compare_mode_mask = 0, + .compare_cfg = (0) | (0) | (0) | (ADC_COMPARE_CFG_EVENT_OUTPUT_OR), + .compare_ref_low = 0, + .compare_ref_high = 0, + .compare_b_channel = (ADC_WINDOW_B_CHANNEL_0), + .compare_b_mode = (ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE), + .compare_b_ref_low = 0, + .compare_b_ref_high = 0, +}; +#endif +const adc_channel_cfg_t g_adc1_channel_cfg = { .scan_mask = 0, + .scan_mask_group_b = 0, .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, + .add_mask = 0, .sample_hold_mask = 0, .sample_hold_states = 24, + #if ((0) | (0)) + .p_window_cfg = (adc_window_cfg_t *)&g_adc1_window_cfg, + #else + .p_window_cfg = NULL, + #endif +}; +/* Instance structure to use this module. */ +const adc_instance_t g_adc1 = { .p_ctrl = &g_adc1_ctrl, .p_cfg = &g_adc1_cfg, + .p_channel_cfg = &g_adc1_channel_cfg, .p_api = &g_adc_on_adc }; +adc_instance_ctrl_t g_adc0_ctrl; +const adc_extended_cfg_t g_adc0_cfg_extend = { .add_average_count = ADC_ADD_OFF, + .clearing = ADC_CLEAR_AFTER_READ_ON, .trigger_group_b = + ADC_TRIGGER_SYNC_ELC, .double_trigger_mode = + ADC_DOUBLE_TRIGGER_DISABLED, .adc_vref_control = + ADC_VREF_CONTROL_VREFH, .enable_adbuf = 0, + #if defined(VECTOR_NUMBER_ADC0_WINDOW_A) + .window_a_irq = VECTOR_NUMBER_ADC0_WINDOW_A, + #else + .window_a_irq = FSP_INVALID_VECTOR, + #endif + .window_a_ipl = (BSP_IRQ_DISABLED), + #if defined(VECTOR_NUMBER_ADC0_WINDOW_B) + .window_b_irq = VECTOR_NUMBER_ADC0_WINDOW_B, + #else + .window_b_irq = FSP_INVALID_VECTOR, + #endif + .window_b_ipl = (BSP_IRQ_DISABLED), }; +const adc_cfg_t g_adc0_cfg = { .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, + .resolution = ADC_RESOLUTION_12_BIT, .alignment = + (adc_alignment_t)ADC_ALIGNMENT_RIGHT, .trigger = + ADC_TRIGGER_SOFTWARE, .p_callback = NULL, + /** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = &g_adc0_cfg_extend, + #if defined(VECTOR_NUMBER_ADC0_SCAN_END) + .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, + #else + .scan_end_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_ipl = (BSP_IRQ_DISABLED), + #if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) + .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, + #else + .scan_end_b_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; +#if ((0) | (0)) +const adc_window_cfg_t g_adc0_window_cfg = +{ + .compare_mask = 0, + .compare_mode_mask = 0, + .compare_cfg = (0) | (0) | (0) | (ADC_COMPARE_CFG_EVENT_OUTPUT_OR), + .compare_ref_low = 0, + .compare_ref_high = 0, + .compare_b_channel = (ADC_WINDOW_B_CHANNEL_0), + .compare_b_mode = (ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE), + .compare_b_ref_low = 0, + .compare_b_ref_high = 0, +}; +#endif +const adc_channel_cfg_t g_adc0_channel_cfg = { .scan_mask = 0, + .scan_mask_group_b = 0, .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, + .add_mask = 0, .sample_hold_mask = 0, .sample_hold_states = 24, + #if ((0) | (0)) + .p_window_cfg = (adc_window_cfg_t *)&g_adc0_window_cfg, + #else + .p_window_cfg = NULL, + #endif +}; +/* Instance structure to use this module. */ +const adc_instance_t g_adc0 = { .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, + .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc }; +lpm_instance_ctrl_t g_lpm0_ctrl; + +const lpm_cfg_t g_lpm0_cfg = { .low_power_mode = LPM_MODE_SLEEP, + .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM + | (lpm_standby_wake_source_t)0, + #if BSP_FEATURE_LPM_HAS_SNOOZE + .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, + .snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING, + .snooze_end_sources = (lpm_snooze_end_t)0, + .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, + #endif + #if BSP_FEATURE_LPM_HAS_SBYCR_OPE + .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN, + #endif + #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + .io_port_state = LPM_IO_PORT_NO_CHANGE, + .power_supply_state = LPM_POWER_SUPPLY_DEEPCUT0, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, + #endif + #if BSP_FEATURE_LPM_HAS_PDRAMSCR + .ram_retention_cfg.ram_retention = (uint8_t)(0), + .ram_retention_cfg.tcm_retention = false, + #endif + #if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + .ram_retention_cfg.standby_ram_retention = false, + #endif + #if BSP_FEATURE_LPM_HAS_LDO_CONTROL + .ldo_standby_cfg.pll1_ldo = false, + .ldo_standby_cfg.pll2_ldo = false, + .ldo_standby_cfg.hoco_ldo = false, + #endif + .p_extend = NULL, }; + +const lpm_instance_t g_lpm0 = { .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, + .p_cfg = &g_lpm0_cfg }; +dtc_instance_ctrl_t g_transfer1_ctrl; + +transfer_info_t g_transfer1_info = { .transfer_settings_word_b.dest_addr_mode = + TRANSFER_ADDR_MODE_INCREMENTED, .transfer_settings_word_b.repeat_area = + TRANSFER_REPEAT_AREA_DESTINATION, .transfer_settings_word_b.irq = + TRANSFER_IRQ_END, .transfer_settings_word_b.chain_mode = + TRANSFER_CHAIN_MODE_DISABLED, .transfer_settings_word_b.src_addr_mode = + TRANSFER_ADDR_MODE_FIXED, .transfer_settings_word_b.size = + TRANSFER_SIZE_2_BYTE, .transfer_settings_word_b.mode = + TRANSFER_MODE_NORMAL, .p_dest = (void *)NULL, .p_src = + (void const *)NULL, .num_blocks = 0, .length = 0, }; + +const dtc_extended_cfg_t g_transfer1_cfg_extend = { .activation_source = + VECTOR_NUMBER_SPI1_RXI, }; +const transfer_cfg_t g_transfer1_cfg = { .p_info = &g_transfer1_info, + .p_extend = &g_transfer1_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer1 = { .p_ctrl = &g_transfer1_ctrl, .p_cfg = + &g_transfer1_cfg, .p_api = &g_transfer_on_dtc }; +dtc_instance_ctrl_t g_transfer0_ctrl; + +transfer_info_t g_transfer0_info = { .transfer_settings_word_b.dest_addr_mode = + TRANSFER_ADDR_MODE_FIXED, .transfer_settings_word_b.repeat_area = + TRANSFER_REPEAT_AREA_SOURCE, .transfer_settings_word_b.irq = + TRANSFER_IRQ_END, .transfer_settings_word_b.chain_mode = + TRANSFER_CHAIN_MODE_DISABLED, .transfer_settings_word_b.src_addr_mode = + TRANSFER_ADDR_MODE_INCREMENTED, .transfer_settings_word_b.size = + TRANSFER_SIZE_2_BYTE, .transfer_settings_word_b.mode = + TRANSFER_MODE_NORMAL, .p_dest = (void *)NULL, .p_src = + (void const *)NULL, .num_blocks = 0, .length = 0, }; + +const dtc_extended_cfg_t g_transfer0_cfg_extend = { .activation_source = + VECTOR_NUMBER_SPI1_TXI, }; +const transfer_cfg_t g_transfer0_cfg = { .p_info = &g_transfer0_info, + .p_extend = &g_transfer0_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer0 = { .p_ctrl = &g_transfer0_ctrl, .p_cfg = + &g_transfer0_cfg, .p_api = &g_transfer_on_dtc }; +#define RA_NOT_DEFINED (UINT32_MAX) +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void spi_tx_dmac_callback(spi_instance_ctrl_t const *const p_ctrl); + +void g_spi1_tx_transfer_callback(dmac_callback_args_t *p_args) { + FSP_PARAMETER_NOT_USED(p_args); + spi_tx_dmac_callback(&g_spi1_ctrl); +} +#endif + +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void spi_rx_dmac_callback(spi_instance_ctrl_t const *const p_ctrl); + +void g_spi1_rx_transfer_callback(dmac_callback_args_t *p_args) { + FSP_PARAMETER_NOT_USED(p_args); + spi_rx_dmac_callback(&g_spi1_ctrl); +} +#endif +#undef RA_NOT_DEFINED + +spi_instance_ctrl_t g_spi1_ctrl; + +/** SPI extended configuration for SPI HAL driver */ +const spi_extended_cfg_t g_spi1_ext_cfg = { .spi_clksyn = SPI_SSL_MODE_CLK_SYN, + .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, .ssl_polarity = SPI_SSLP_LOW, + .ssl_select = SPI_SSL_SELECT_SSL0, .mosi_idle = + SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, .parity = + SPI_PARITY_MODE_DISABLE, .byte_swap = SPI_BYTE_SWAP_DISABLE, + .spck_div = { + /* Actual calculated bitrate: 15000000. */ .spbr = 3, .brdv = 0 + }, + .spck_delay = SPI_DELAY_COUNT_1, + .ssl_negation_delay = SPI_DELAY_COUNT_1, .next_access_delay = + SPI_DELAY_COUNT_1 }; + +/** SPI configuration for SPI HAL driver */ +const spi_cfg_t g_spi1_cfg = { .channel = 1, + + #if defined(VECTOR_NUMBER_SPI1_RXI) + .rxi_irq = VECTOR_NUMBER_SPI1_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI1_TXI) + .txi_irq = VECTOR_NUMBER_SPI1_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI1_TEI) + .tei_irq = VECTOR_NUMBER_SPI1_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI1_ERI) + .eri_irq = VECTOR_NUMBER_SPI1_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif + + .rxi_ipl = (12), .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + + .operating_mode = SPI_MODE_MASTER, + + .clk_phase = SPI_CLK_PHASE_EDGE_ODD, .clk_polarity = + SPI_CLK_POLARITY_LOW, + + .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, .bit_order = + SPI_BIT_ORDER_MSB_FIRST, .p_transfer_tx = g_spi1_P_TRANSFER_TX, + .p_transfer_rx = g_spi1_P_TRANSFER_RX, .p_callback = spi_callback, + + .p_context = NULL, .p_extend = (void *)&g_spi1_ext_cfg, }; + +/* Instance structure to use this module. */ +const spi_instance_t g_spi1 = { .p_ctrl = &g_spi1_ctrl, .p_cfg = &g_spi1_cfg, + .p_api = &g_spi_on_spi }; +agt_instance_ctrl_t g_timer1_ctrl; +const agt_extended_cfg_t g_timer1_extend = +{ .count_source = AGT_CLOCK_PCLKB, .agto = AGT_PIN_CFG_DISABLED, + .agtoab_settings_b.agtoa = AGT_PIN_CFG_DISABLED, + .agtoab_settings_b.agtob = AGT_PIN_CFG_DISABLED, + .measurement_mode = AGT_MEASURE_DISABLED, .agtio_filter = + AGT_AGTIO_FILTER_NONE, .enable_pin = + AGT_ENABLE_PIN_NOT_USED, .trigger_edge = + AGT_TRIGGER_EDGE_RISING, }; +const timer_cfg_t g_timer1_cfg = +{ .mode = TIMER_MODE_PERIODIC, + /* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = + (uint32_t)0x10000, .duty_cycle_counts = 0x8000, + .source_div = (timer_source_div_t)0, .channel = 1, + .p_callback = callback_agt, + /** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = &g_timer1_extend, .cycle_end_ipl = (5), + #if defined(VECTOR_NUMBER_AGT1_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT1_INT, + #else + .cycle_end_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer1 = { .p_ctrl = &g_timer1_ctrl, .p_cfg = + &g_timer1_cfg, .p_api = &g_timer_on_agt }; +agt_instance_ctrl_t g_timer0_ctrl; +const agt_extended_cfg_t g_timer0_extend = +{ .count_source = AGT_CLOCK_PCLKB, .agto = AGT_PIN_CFG_DISABLED, + .agtoab_settings_b.agtoa = AGT_PIN_CFG_DISABLED, + .agtoab_settings_b.agtob = AGT_PIN_CFG_DISABLED, + .measurement_mode = AGT_MEASURE_DISABLED, .agtio_filter = + AGT_AGTIO_FILTER_NONE, .enable_pin = + AGT_ENABLE_PIN_NOT_USED, .trigger_edge = + AGT_TRIGGER_EDGE_RISING, }; +const timer_cfg_t g_timer0_cfg = +{ .mode = TIMER_MODE_PERIODIC, + /* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = + (uint32_t)0x10000, .duty_cycle_counts = 0x8000, + .source_div = (timer_source_div_t)0, .channel = 0, + .p_callback = callback_agt, + /** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = &g_timer0_extend, .cycle_end_ipl = (5), + #if defined(VECTOR_NUMBER_AGT0_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, + #else + .cycle_end_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer0 = { .p_ctrl = &g_timer0_ctrl, .p_cfg = + &g_timer0_cfg, .p_api = &g_timer_on_agt }; +flash_hp_instance_ctrl_t g_flash0_ctrl; +const flash_cfg_t g_flash0_cfg = { .data_flash_bgo = false, .p_callback = NULL, + .p_context = NULL, + #if defined(VECTOR_NUMBER_FCU_FRDYI) + .irq = VECTOR_NUMBER_FCU_FRDYI, + #else + .irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_FCU_FIFERR) + .err_irq = VECTOR_NUMBER_FCU_FIFERR, + #else + .err_irq = FSP_INVALID_VECTOR, + #endif + .err_ipl = (BSP_IRQ_DISABLED), .ipl = (BSP_IRQ_DISABLED), }; +/* Instance structure to use this module. */ +const flash_instance_t g_flash0 = { .p_ctrl = &g_flash0_ctrl, .p_cfg = + &g_flash0_cfg, .p_api = &g_flash_on_flash_hp }; +rtc_instance_ctrl_t g_rtc0_ctrl; +const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = { .adjustment_mode = + RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, .adjustment_period = + RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, .adjustment_type = + RTC_ERROR_ADJUSTMENT_NONE, .adjustment_value = 0, }; +const rtc_cfg_t g_rtc0_cfg = { .clock_source = RTC_CLOCK_SOURCE_LOCO, + .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, + .p_callback = NULL, .p_context = NULL, .alarm_ipl = (14), + .periodic_ipl = (14), .carry_ipl = (14), + #if defined(VECTOR_NUMBER_RTC_ALARM) + .alarm_irq = VECTOR_NUMBER_RTC_ALARM, + #else + .alarm_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_RTC_PERIOD) + .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, + #else + .periodic_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_RTC_CARRY) + .carry_irq = VECTOR_NUMBER_RTC_CARRY, + #else + .carry_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const rtc_instance_t g_rtc0 = { .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, + .p_api = &g_rtc_on_rtc }; +sci_uart_instance_ctrl_t g_uart9_ctrl; + +baud_setting_t g_uart9_baud_setting = { +/* Baud rate calculated with 0.160% error. */ .semr_baudrate_bits_b.abcse = 0, + .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, + .cks = 0, .brr = 64, .mddr = (uint8_t)256, .semr_baudrate_bits_b.brme = + false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart9_cfg_extend = { + .clock = SCI_UART_CLOCK_INT, .rx_edge_start = + SCI_UART_START_BIT_FALLING_EDGE, .noise_cancel = + SCI_UART_NOISE_CANCELLATION_DISABLE, .rx_fifo_trigger = + SCI_UART_RX_FIFO_TRIGGER_MAX, .p_baud_setting = + &g_uart9_baud_setting, + .flow_control = SCI_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t)UINT16_MAX, + #endif + .rs485_setting = { .enable = SCI_UART_RS485_DISABLE, .polarity = + SCI_UART_RS485_DE_POLARITY_HIGH, + #if 0xFF != 0xFF + .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .de_control_pin = (bsp_io_port_pin_t)UINT16_MAX, + #endif + }, +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart9_cfg = { .channel = 9, .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, .p_context = NULL, .p_extend = + &g_uart9_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI9_RXI) + .rxi_irq = VECTOR_NUMBER_SCI9_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI9_TXI) + .txi_irq = VECTOR_NUMBER_SCI9_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI9_TEI) + .tei_irq = VECTOR_NUMBER_SCI9_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI9_ERI) + .eri_irq = VECTOR_NUMBER_SCI9_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart9 = { .p_ctrl = &g_uart9_ctrl, + .p_cfg = &g_uart9_cfg, .p_api = &g_uart_on_sci }; +sci_uart_instance_ctrl_t g_uart8_ctrl; + +baud_setting_t g_uart8_baud_setting = { +/* Baud rate calculated with 0.160% error. */ .semr_baudrate_bits_b.abcse = 0, + .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, + .cks = 0, .brr = 64, .mddr = (uint8_t)256, .semr_baudrate_bits_b.brme = + false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart8_cfg_extend = { + .clock = SCI_UART_CLOCK_INT, .rx_edge_start = + SCI_UART_START_BIT_FALLING_EDGE, .noise_cancel = + SCI_UART_NOISE_CANCELLATION_DISABLE, .rx_fifo_trigger = + SCI_UART_RX_FIFO_TRIGGER_MAX, .p_baud_setting = + &g_uart8_baud_setting, + .flow_control = SCI_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t)UINT16_MAX, + #endif + .rs485_setting = { .enable = SCI_UART_RS485_DISABLE, .polarity = + SCI_UART_RS485_DE_POLARITY_HIGH, + #if 0xFF != 0xFF + .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .de_control_pin = (bsp_io_port_pin_t)UINT16_MAX, + #endif + }, +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart8_cfg = { .channel = 8, .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, .p_context = NULL, .p_extend = + &g_uart8_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI8_RXI) + .rxi_irq = VECTOR_NUMBER_SCI8_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI8_TXI) + .txi_irq = VECTOR_NUMBER_SCI8_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI8_TEI) + .tei_irq = VECTOR_NUMBER_SCI8_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI8_ERI) + .eri_irq = VECTOR_NUMBER_SCI8_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart8 = { .p_ctrl = &g_uart8_ctrl, + .p_cfg = &g_uart8_cfg, .p_api = &g_uart_on_sci }; +sci_uart_instance_ctrl_t g_uart7_ctrl; + +baud_setting_t g_uart7_baud_setting = { +/* Baud rate calculated with 0.160% error. */ .semr_baudrate_bits_b.abcse = 0, + .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, + .cks = 0, .brr = 64, .mddr = (uint8_t)256, .semr_baudrate_bits_b.brme = + false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart7_cfg_extend = { + .clock = SCI_UART_CLOCK_INT, .rx_edge_start = + SCI_UART_START_BIT_FALLING_EDGE, .noise_cancel = + SCI_UART_NOISE_CANCELLATION_DISABLE, .rx_fifo_trigger = + SCI_UART_RX_FIFO_TRIGGER_MAX, .p_baud_setting = + &g_uart7_baud_setting, + .flow_control = SCI_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t)UINT16_MAX, + #endif + .rs485_setting = { .enable = SCI_UART_RS485_DISABLE, .polarity = + SCI_UART_RS485_DE_POLARITY_HIGH, + #if 0xFF != 0xFF + .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .de_control_pin = (bsp_io_port_pin_t)UINT16_MAX, + #endif + }, +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart7_cfg = { .channel = 7, .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, .p_context = NULL, .p_extend = + &g_uart7_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI7_RXI) + .rxi_irq = VECTOR_NUMBER_SCI7_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI7_TXI) + .txi_irq = VECTOR_NUMBER_SCI7_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI7_TEI) + .tei_irq = VECTOR_NUMBER_SCI7_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI7_ERI) + .eri_irq = VECTOR_NUMBER_SCI7_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart7 = { .p_ctrl = &g_uart7_ctrl, + .p_cfg = &g_uart7_cfg, .p_api = &g_uart_on_sci }; +void g_hal_init(void) { + g_common_init(); +} diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_gen/hal_data.h b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/hal_data.h new file mode 100644 index 0000000000000..d7fd29cb854e6 --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/hal_data.h @@ -0,0 +1,393 @@ +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include +#include "bsp_api.h" +#include "common_data.h" +#include "r_usb_basic.h" +#include "r_usb_basic_api.h" +#include "r_usb_pcdc_api.h" +#include "r_jpeg.h" +#include "r_dtc.h" +#include "r_transfer_api.h" +#include "r_pdc.h" +#include "r_pdc_api.h" +#include "r_sci_i2c.h" +#include "r_i2c_master_api.h" +#include "r_glcdc.h" +#include "r_display_api.h" +#include "r_ether_phy.h" +#include "r_ether_phy_api.h" +#include "r_ether.h" +#include "r_ether_api.h" +#include "r_sdhi.h" +#include "r_sdmmc_api.h" +#include "r_qspi.h" +#include "r_spi_flash_api.h" +#include "r_iic_master.h" +#include "r_i2c_master_api.h" +#include "r_adc.h" +#include "r_adc_api.h" +#include "r_lpm.h" +#include "r_lpm_api.h" +#include "r_spi.h" +#include "r_agt.h" +#include "r_timer_api.h" +#include "r_flash_hp.h" +#include "r_flash_api.h" +#include "r_rtc.h" +#include "r_rtc_api.h" +#include "r_sci_uart.h" +#include "r_uart_api.h" +FSP_HEADER +/* Basic on USB Instance. */ +extern const usb_instance_t g_basic0; + +/** Access the USB instance using these structures when calling API functions directly (::p_api is not used). */ +extern usb_instance_ctrl_t g_basic0_ctrl; +extern const usb_cfg_t g_basic0_cfg; + +#ifndef NULL +void NULL(void *); +#endif + +#if 2 == BSP_CFG_RTOS +#ifndef NULL +void NULL(usb_event_info_t *, usb_hdl_t, usb_onoff_t); +#endif +#endif +/** CDC Driver on USB Instance. */ +extern const jpeg_instance_t g_jpeg0; + +/** Access the JPEG instance using these structures when calling API functions directly (::p_api is not used). */ +extern jpeg_instance_ctrl_t g_jpeg0_ctrl; +extern const jpeg_cfg_t g_jpeg0_cfg; + +#if JPEG_CFG_DECODE_ENABLE +#ifndef NULL +void NULL(jpeg_callback_args_t *p_args); +#endif +#endif + +#if JPEG_CFG_ENCODE_ENABLE +#ifndef jpg_ISR +void jpg_ISR(jpeg_callback_args_t *p_args); +#endif +#endif +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer5; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer5_ctrl; +extern const transfer_cfg_t g_transfer5_cfg; +/** PDC on PDC instance */ +extern const pdc_instance_t g_cam0; +/** Access the PDC instance using these structures when calling API functions directly (::p_api is not used). */ +extern pdc_instance_ctrl_t g_cam0_ctrl; +extern pdc_cfg_t g_cam0_cfg; +#ifndef cam_ISR +void cam_ISR(pdc_callback_args_t *p_args); +#endif +#ifdef g_cam_buffer +#define PDC_ON_PDC_BUFFER_USED_g_cam0 (0) +#else +#define PDC_ON_PDC_BUFFER_USED_g_cam0 (1) +#endif +#if PDC_ON_PDC_BUFFER_USED_g_cam0 +/** Buffer where captured image will be stored for application usage */ +extern uint8_t g_cam_buffer[1][320 * 240 * 2]; +#endif +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer4; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer4_ctrl; +extern const transfer_cfg_t g_transfer4_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer3; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer3_ctrl; +extern const transfer_cfg_t g_transfer3_cfg; +extern const i2c_master_cfg_t g_i2c_touch_cfg; +/* I2C on SCI Instance. */ +extern const i2c_master_instance_t g_i2c_touch; +#ifndef touch_i2c_callback +void touch_i2c_callback(i2c_master_callback_args_t *p_args); +#endif + +extern const sci_i2c_extended_cfg_t g_i2c_touch_cfg_extend; +extern sci_i2c_instance_ctrl_t g_i2c_touch_ctrl; +#define GLCDC_CFG_LAYER_1_ENABLE (true) +#define GLCDC_CFG_LAYER_2_ENABLE (false) + +#define GLCDC_CFG_CLUT_ENABLE (false) + +#define GLCDC_CFG_CORRECTION_GAMMA_ENABLE_R (false) +#define GLCDC_CFG_CORRECTION_GAMMA_ENABLE_G (false) +#define GLCDC_CFG_CORRECTION_GAMMA_ENABLE_B (false) + +/* Display on GLCDC Instance. */ +extern const display_instance_t g_display0; +extern display_runtime_cfg_t g_display0_runtime_cfg_fg; +extern display_runtime_cfg_t g_display0_runtime_cfg_bg; + +/** Access the GLCDC instance using these structures when calling API functions directly (::p_api is not used). */ +extern glcdc_instance_ctrl_t g_display0_ctrl; +extern const display_cfg_t g_display0_cfg; + +#if ((GLCDC_CFG_CORRECTION_GAMMA_ENABLE_R | GLCDC_CFG_CORRECTION_GAMMA_ENABLE_G | GLCDC_CFG_CORRECTION_GAMMA_ENABLE_B) && GLCDC_CFG_COLOR_CORRECTION_ENABLE && !(false)) +extern display_gamma_correction_t g_display0_gamma_cfg; +#endif + +#if GLCDC_CFG_CLUT_ENABLE +extern display_clut_cfg_t g_display0_clut_cfg_glcdc; +#endif + +#ifndef lcd_Vsync_ISR +void lcd_Vsync_ISR(display_callback_args_t *p_args); +#endif + +#define DISPLAY_IN_FORMAT_16BITS_RGB565_0 +#if defined(DISPLAY_IN_FORMAT_32BITS_RGB888_0) || defined(DISPLAY_IN_FORMAT_32BITS_ARGB8888_0) +#define DISPLAY_BITS_PER_PIXEL_INPUT0 (32) +#elif defined(DISPLAY_IN_FORMAT_16BITS_RGB565_0) || defined(DISPLAY_IN_FORMAT_16BITS_ARGB1555_0) || defined(DISPLAY_IN_FORMAT_16BITS_ARGB4444_0) +#define DISPLAY_BITS_PER_PIXEL_INPUT0 (16) +#elif defined(DISPLAY_IN_FORMAT_CLUT8_0) +#define DISPLAY_BITS_PER_PIXEL_INPUT0 (8) +#elif defined(DISPLAY_IN_FORMAT_CLUT4_0) +#define DISPLAY_BITS_PER_PIXEL_INPUT0 (4) +#else +#define DISPLAY_BITS_PER_PIXEL_INPUT0 (1) +#endif +#define DISPLAY_HSIZE_INPUT0 (480) +#define DISPLAY_VSIZE_INPUT0 (272) +#define DISPLAY_BUFFER_STRIDE_BYTES_INPUT0 (((DISPLAY_HSIZE_INPUT0 * DISPLAY_BITS_PER_PIXEL_INPUT0 + 0x1FF) >> 9) << 6) +#define DISPLAY_BUFFER_STRIDE_PIXELS_INPUT0 ((DISPLAY_BUFFER_STRIDE_BYTES_INPUT0 * 8) / DISPLAY_BITS_PER_PIXEL_INPUT0) +#if GLCDC_CFG_LAYER_1_ENABLE +extern uint8_t fb_background[1][DISPLAY_BUFFER_STRIDE_BYTES_INPUT0 * DISPLAY_VSIZE_INPUT0]; +#endif + +#define DISPLAY_IN_FORMAT_16BITS_RGB565_1 +#if defined(DISPLAY_IN_FORMAT_32BITS_RGB888_1) || defined(DISPLAY_IN_FORMAT_32BITS_ARGB8888_1) +#define DISPLAY_BITS_PER_PIXEL_INPUT1 (32) +#elif defined(DISPLAY_IN_FORMAT_16BITS_RGB565_1) || defined(DISPLAY_IN_FORMAT_16BITS_ARGB1555_1) || defined(DISPLAY_IN_FORMAT_16BITS_ARGB4444_1) +#define DISPLAY_BITS_PER_PIXEL_INPUT1 (16) +#elif defined(DISPLAY_IN_FORMAT_CLUT8_1) +#define DISPLAY_BITS_PER_PIXEL_INPUT1 (8) +#elif defined(DISPLAY_IN_FORMAT_CLUT4_1) +#define DISPLAY_BITS_PER_PIXEL_INPUT1 (4) +#else +#define DISPLAY_BITS_PER_PIXEL_INPUT1 (1) +#endif +#define DISPLAY_HSIZE_INPUT1 (480) +#define DISPLAY_VSIZE_INPUT1 (272) +#define DISPLAY_BUFFER_STRIDE_BYTES_INPUT1 (((DISPLAY_HSIZE_INPUT1 * DISPLAY_BITS_PER_PIXEL_INPUT1 + 0x1FF) >> 9) << 6) +#define DISPLAY_BUFFER_STRIDE_PIXELS_INPUT1 ((DISPLAY_BUFFER_STRIDE_BYTES_INPUT1 * 8) / DISPLAY_BITS_PER_PIXEL_INPUT1) +#if GLCDC_CFG_LAYER_2_ENABLE +extern uint8_t fb_foreground[2][DISPLAY_BUFFER_STRIDE_BYTES_INPUT1 * DISPLAY_VSIZE_INPUT1]; +#endif +#ifndef ETHER_PHY_LSI_TYPE_KIT_COMPONENT +#define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_DEFAULT +#endif + +/** ether_phy on ether_phy Instance. */ +extern const ether_phy_instance_t g_ether_phy0; + +/** Access the Ethernet PHY instance using these structures when calling API functions directly (::p_api is not used). */ +extern ether_phy_instance_ctrl_t g_ether_phy0_ctrl; +extern const ether_phy_cfg_t g_ether_phy0_cfg; +#if (BSP_FEATURE_TZ_HAS_TRUSTZONE == 1) && (BSP_TZ_SECURE_BUILD != 1) && (BSP_TZ_NONSECURE_BUILD != 1) && (BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE == 0) +#define ETHER_BUFFER_PLACE_IN_SECTION BSP_PLACE_IN_SECTION(".ns_buffer.eth") +#else +#define ETHER_BUFFER_PLACE_IN_SECTION +#endif + +/** ether on ether Instance. */ +extern const ether_instance_t g_ether0; + +/** Access the Ethernet instance using these structures when calling API functions directly (::p_api is not used). */ +extern ether_instance_ctrl_t g_ether0_ctrl; +extern const ether_cfg_t g_ether0_cfg; + +#ifndef ETH_IRQHandler +void ETH_IRQHandler(ether_callback_args_t *p_args); +#endif +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer2; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer2_ctrl; +extern const transfer_cfg_t g_transfer2_cfg; +/** SDMMC on SDMMC Instance. */ +extern const sdmmc_instance_t g_sdmmc0; + +/** Access the SDMMC instance using these structures when calling API functions directly (::p_api is not used). */ +extern sdhi_instance_ctrl_t g_sdmmc0_ctrl; +extern sdmmc_cfg_t g_sdmmc0_cfg; + +#ifndef sdhi_ISR +void sdhi_ISR(sdmmc_callback_args_t *p_args); +#endif +extern const spi_flash_instance_t g_qspi0; +extern qspi_instance_ctrl_t g_qspi0_ctrl; +extern const spi_flash_cfg_t g_qspi0_cfg; +/* I2C Master on IIC Instance. */ +extern const i2c_master_instance_t g_i2c_master1; + +/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */ +extern iic_master_instance_ctrl_t g_i2c_master1_ctrl; +extern const i2c_master_cfg_t g_i2c_master1_cfg; + +#ifndef callback_iic +void callback_iic(i2c_master_callback_args_t *p_args); +#endif +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc1; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc1_ctrl; +extern const adc_cfg_t g_adc1_cfg; +extern const adc_channel_cfg_t g_adc1_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t *p_args); +#endif + +#ifndef NULL +#define ADC_DMAC_CHANNELS_PER_BLOCK_NULL 0 +#endif +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc0; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc0_ctrl; +extern const adc_cfg_t g_adc0_cfg; +extern const adc_channel_cfg_t g_adc0_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t *p_args); +#endif + +#ifndef NULL +#define ADC_DMAC_CHANNELS_PER_BLOCK_NULL 0 +#endif +/** lpm Instance */ +extern const lpm_instance_t g_lpm0; + +/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ +extern lpm_instance_ctrl_t g_lpm0_ctrl; +extern const lpm_cfg_t g_lpm0_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer1; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer1_ctrl; +extern const transfer_cfg_t g_transfer1_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer0; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer0_ctrl; +extern const transfer_cfg_t g_transfer0_cfg; +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi1; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_instance_ctrl_t g_spi1_ctrl; +extern const spi_cfg_t g_spi1_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi_callback +void spi_callback(spi_callback_args_t *p_args); +#endif + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer0) +#define g_spi1_P_TRANSFER_TX (NULL) +#else +#define g_spi1_P_TRANSFER_TX (&g_transfer0) +#endif +#if (RA_NOT_DEFINED == g_transfer1) +#define g_spi1_P_TRANSFER_RX (NULL) +#else +#define g_spi1_P_TRANSFER_RX (&g_transfer1) +#endif +#undef RA_NOT_DEFINED +/** AGT Timer Instance */ +extern const timer_instance_t g_timer1; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer1_ctrl; +extern const timer_cfg_t g_timer1_cfg; + +#ifndef callback_agt +void callback_agt(timer_callback_args_t *p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer0; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer0_ctrl; +extern const timer_cfg_t g_timer0_cfg; + +#ifndef callback_agt +void callback_agt(timer_callback_args_t *p_args); +#endif +/* Flash on Flash HP Instance */ +extern const flash_instance_t g_flash0; + +/** Access the Flash HP instance using these structures when calling API functions directly (::p_api is not used). */ +extern flash_hp_instance_ctrl_t g_flash0_ctrl; +extern const flash_cfg_t g_flash0_cfg; + +#ifndef NULL +void NULL(flash_callback_args_t *p_args); +#endif +/* RTC Instance. */ +extern const rtc_instance_t g_rtc0; + +/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern rtc_instance_ctrl_t g_rtc0_ctrl; +extern const rtc_cfg_t g_rtc0_cfg; + +#ifndef NULL +void NULL(rtc_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart9; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart9_ctrl; +extern const uart_cfg_t g_uart9_cfg; +extern const sci_uart_extended_cfg_t g_uart9_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart8; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart8_ctrl; +extern const uart_cfg_t g_uart8_cfg; +extern const sci_uart_extended_cfg_t g_uart8_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart7; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart7_ctrl; +extern const uart_cfg_t g_uart7_cfg; +extern const sci_uart_extended_cfg_t g_uart7_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_gen/pin_data.c b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/pin_data.c new file mode 100644 index 0000000000000..5e63b4d20a70a --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/pin_data.c @@ -0,0 +1,414 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport_api.h" + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { { .pin = BSP_IO_PORT_00_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) }, + { .pin = BSP_IO_PORT_00_PIN_01, .pin_cfg = + ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) }, { .pin = + BSP_IO_PORT_00_PIN_02, .pin_cfg = + ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) }, { .pin = + BSP_IO_PORT_00_PIN_03, .pin_cfg = + ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) }, { .pin = + BSP_IO_PORT_00_PIN_08, .pin_cfg = + ((uint32_t)IOPORT_CFG_IRQ_ENABLE + | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) }, { + .pin = BSP_IO_PORT_00_PIN_09, .pin_cfg = + ((uint32_t)IOPORT_CFG_IRQ_ENABLE + | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { .pin = BSP_IO_PORT_00_PIN_14, .pin_cfg = + ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) }, { .pin = + BSP_IO_PORT_00_PIN_15, .pin_cfg = + ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) }, { .pin = + BSP_IO_PORT_01_PIN_00, .pin_cfg = + ((uint32_t)IOPORT_CFG_NMOS_ENABLE + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, { .pin = + BSP_IO_PORT_01_PIN_01, .pin_cfg = + ((uint32_t)IOPORT_CFG_NMOS_ENABLE + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, { .pin = + BSP_IO_PORT_01_PIN_04, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, { .pin = + BSP_IO_PORT_01_PIN_05, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, { .pin = + BSP_IO_PORT_01_PIN_06, .pin_cfg = + ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, { .pin = + BSP_IO_PORT_01_PIN_08, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, { .pin = + BSP_IO_PORT_01_PIN_09, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, { .pin = + BSP_IO_PORT_01_PIN_10, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, { .pin = + BSP_IO_PORT_02_PIN_02, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, { .pin = + BSP_IO_PORT_02_PIN_03, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, { .pin = + BSP_IO_PORT_02_PIN_04, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, { .pin = + BSP_IO_PORT_02_PIN_05, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_MID + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_IIC) }, { .pin = + BSP_IO_PORT_02_PIN_06, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_MID + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_IIC) }, { .pin = + BSP_IO_PORT_02_PIN_07, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_02_PIN_08, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_02_PIN_09, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_02_PIN_10, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_02_PIN_11, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_02_PIN_12, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_CLKOUT_COMP_RTC) }, { + .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) + }, + { .pin = BSP_IO_PORT_03_PIN_00, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, { .pin = + BSP_IO_PORT_03_PIN_01, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, { .pin = + BSP_IO_PORT_03_PIN_05, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_QSPI) }, { .pin = + BSP_IO_PORT_03_PIN_06, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_QSPI) }, { .pin = + BSP_IO_PORT_03_PIN_07, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_QSPI) }, { .pin = + BSP_IO_PORT_03_PIN_08, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_QSPI) }, { .pin = + BSP_IO_PORT_03_PIN_09, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_QSPI) }, { .pin = + BSP_IO_PORT_03_PIN_10, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_QSPI) }, { .pin = + BSP_IO_PORT_03_PIN_13, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_03_PIN_14, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_03_PIN_15, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_04_PIN_00, .pin_cfg = + ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, { .pin = + BSP_IO_PORT_04_PIN_01, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin = + BSP_IO_PORT_04_PIN_02, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin = + BSP_IO_PORT_04_PIN_03, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_PDC) }, { .pin = + BSP_IO_PORT_04_PIN_04, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_PDC) }, { .pin = + BSP_IO_PORT_04_PIN_05, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin = + BSP_IO_PORT_04_PIN_06, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin = + BSP_IO_PORT_04_PIN_07, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_USB_FS) }, { .pin = + BSP_IO_PORT_04_PIN_08, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_PDC) }, { .pin = + BSP_IO_PORT_04_PIN_09, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_PDC) }, { .pin = + BSP_IO_PORT_04_PIN_10, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_PDC) }, { .pin = + BSP_IO_PORT_04_PIN_11, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_PDC) }, { .pin = + BSP_IO_PORT_04_PIN_12, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_PDC) }, { .pin = + BSP_IO_PORT_04_PIN_13, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_PDC) }, { .pin = + BSP_IO_PORT_04_PIN_14, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_PDC) }, { .pin = + BSP_IO_PORT_04_PIN_15, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_PDC) }, { .pin = + BSP_IO_PORT_05_PIN_00, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin = + BSP_IO_PORT_05_PIN_01, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin = + BSP_IO_PORT_05_PIN_02, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin = + BSP_IO_PORT_05_PIN_03, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin = + BSP_IO_PORT_05_PIN_04, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin = + BSP_IO_PORT_05_PIN_05, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin = + BSP_IO_PORT_05_PIN_06, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin = + BSP_IO_PORT_05_PIN_07, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin = + BSP_IO_PORT_05_PIN_12, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_PDC) }, { .pin = + BSP_IO_PORT_05_PIN_13, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_06_PIN_01, .pin_cfg = + ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, { .pin = + BSP_IO_PORT_06_PIN_03, .pin_cfg = + ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, { .pin = + BSP_IO_PORT_06_PIN_05, .pin_cfg = + ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, { .pin = + BSP_IO_PORT_06_PIN_06, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_06_PIN_07, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_06_PIN_08, .pin_cfg = + ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, { .pin = + BSP_IO_PORT_06_PIN_09, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_CAN) }, { .pin = + BSP_IO_PORT_06_PIN_10, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_CAN) }, { .pin = + BSP_IO_PORT_06_PIN_11, .pin_cfg = + ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, { .pin = + BSP_IO_PORT_06_PIN_12, .pin_cfg = + ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, { .pin = + BSP_IO_PORT_06_PIN_13, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, { .pin = + BSP_IO_PORT_06_PIN_14, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, { .pin = + BSP_IO_PORT_06_PIN_15, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_07_PIN_00, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin = + BSP_IO_PORT_07_PIN_01, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin = + BSP_IO_PORT_07_PIN_02, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin = + BSP_IO_PORT_07_PIN_03, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin = + BSP_IO_PORT_07_PIN_04, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin = + BSP_IO_PORT_07_PIN_05, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin = + BSP_IO_PORT_07_PIN_06, .pin_cfg = + ((uint32_t)IOPORT_CFG_IRQ_ENABLE + | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) }, { + .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_USB_HS) + }, { + .pin = BSP_IO_PORT_07_PIN_08, .pin_cfg = + ((uint32_t)IOPORT_CFG_IRQ_ENABLE + | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { .pin = BSP_IO_PORT_08_PIN_01, .pin_cfg = + ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, { .pin = + BSP_IO_PORT_08_PIN_02, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_08_PIN_03, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_08_PIN_04, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_08_PIN_05, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_08_PIN_06, .pin_cfg = + ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, { .pin = + BSP_IO_PORT_09_PIN_00, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_09_PIN_01, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_09_PIN_05, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_09_PIN_06, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_09_PIN_07, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_09_PIN_08, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_10_PIN_00, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_10_PIN_01, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_10_PIN_08, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_10_PIN_09, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_10_PIN_10, .pin_cfg = + ((uint32_t)IOPORT_CFG_DRIVE_HIGH + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_LCD_GRAPHICS) }, { .pin = + BSP_IO_PORT_11_PIN_00, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_USB_HS) }, { .pin = + BSP_IO_PORT_11_PIN_01, .pin_cfg = + ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_USB_HS) }, }; + +const ioport_cfg_t g_bsp_pin_cfg = { .number_of_pins = + sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = + &g_bsp_pin_cfg_data[0], }; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for (uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t)pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_gen/vector_data.c b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/vector_data.c new file mode 100644 index 0000000000000..ad01c7b538b1a --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/vector_data.c @@ -0,0 +1,107 @@ +/* generated vector source file - do not edit */ +#include "bsp_api.h" +/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ +#if VECTOR_DATA_IRQ_COUNT > 0 +BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = +{ + [0] = sci_uart_rxi_isr, /* SCI7 RXI (Received data full) */ + [1] = sci_uart_txi_isr, /* SCI7 TXI (Transmit data empty) */ + [2] = sci_uart_tei_isr, /* SCI7 TEI (Transmit end) */ + [3] = sci_uart_eri_isr, /* SCI7 ERI (Receive error) */ + [4] = sci_uart_rxi_isr, /* SCI8 RXI (Received data full) */ + [5] = sci_uart_txi_isr, /* SCI8 TXI (Transmit data empty) */ + [6] = sci_uart_tei_isr, /* SCI8 TEI (Transmit end) */ + [7] = sci_uart_eri_isr, /* SCI8 ERI (Receive error) */ + [8] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */ + [9] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */ + [10] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */ + [11] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */ + [12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ + [13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ + [14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ + [16] = agt_int_isr, /* AGT1 INT (AGT interrupt) */ + [17] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */ + [18] = r_icu_isr, /* ICU IRQ11 (External pin interrupt 11) */ + [19] = r_icu_isr, /* ICU IRQ12 (External pin interrupt 12) */ + [20] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */ + [21] = spi_rxi_isr, /* SPI1 RXI (Receive buffer full) */ + [22] = spi_txi_isr, /* SPI1 TXI (Transmit buffer empty) */ + [23] = spi_tei_isr, /* SPI1 TEI (Transmission complete event) */ + [24] = spi_eri_isr, /* SPI1 ERI (Error) */ + [25] = iic_master_rxi_isr, /* IIC1 RXI (Receive data full) */ + [26] = iic_master_txi_isr, /* IIC1 TXI (Transmit data empty) */ + [27] = iic_master_tei_isr, /* IIC1 TEI (Transmit end) */ + [28] = iic_master_eri_isr, /* IIC1 ERI (Transfer error) */ + [29] = sdhimmc_accs_isr, /* SDHIMMC1 ACCS (Card access) */ + [30] = sdhimmc_card_isr, /* SDHIMMC1 CARD (Card detect) */ + [31] = sdhimmc_dma_req_isr, /* SDHIMMC1 DMA REQ (DMA transfer request) */ + [32] = ether_eint_isr, /* EDMAC0 EINT (EDMAC 0 interrupt) */ + [33] = glcdc_line_detect_isr, /* GLCDC LINE DETECT (Specified line) */ + [34] = sci_i2c_txi_isr, /* SCI0 TXI (Transmit data empty) */ + [35] = sci_i2c_tei_isr, /* SCI0 TEI (Transmit end) */ + [36] = sci_i2c_rxi_isr, /* SCI0 RXI (Receive data full) */ + [37] = pdc_int_isr, /* PDC INT (Error interrupt) */ + [38] = pdc_transfer_req_isr, /* PDC RECEIVE DATA READY (Receive data ready interrupt) */ + [39] = jpeg_jedi_isr, /* JPEG JEDI (Compression/decompression process interrupt) */ + [40] = jpeg_jdti_isr, /* JPEG JDTI (Data transfer interrupt) */ + [41] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */ + [42] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */ + [43] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */ + [44] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */ + [45] = usbhs_interrupt_handler, /* USBHS USB INT RESUME (USBHS interrupt) */ + [46] = usbhs_d0fifo_handler, /* USBHS FIFO 0 (DMA transfer request 0) */ + [47] = usbhs_d1fifo_handler, /* USBHS FIFO 1 (DMA transfer request 1) */ +}; +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = +{ + [0] = BSP_PRV_IELS_ENUM(EVENT_SCI7_RXI), /* SCI7 RXI (Received data full) */ + [1] = BSP_PRV_IELS_ENUM(EVENT_SCI7_TXI), /* SCI7 TXI (Transmit data empty) */ + [2] = BSP_PRV_IELS_ENUM(EVENT_SCI7_TEI), /* SCI7 TEI (Transmit end) */ + [3] = BSP_PRV_IELS_ENUM(EVENT_SCI7_ERI), /* SCI7 ERI (Receive error) */ + [4] = BSP_PRV_IELS_ENUM(EVENT_SCI8_RXI), /* SCI8 RXI (Received data full) */ + [5] = BSP_PRV_IELS_ENUM(EVENT_SCI8_TXI), /* SCI8 TXI (Transmit data empty) */ + [6] = BSP_PRV_IELS_ENUM(EVENT_SCI8_TEI), /* SCI8 TEI (Transmit end) */ + [7] = BSP_PRV_IELS_ENUM(EVENT_SCI8_ERI), /* SCI8 ERI (Receive error) */ + [8] = BSP_PRV_IELS_ENUM(EVENT_SCI9_RXI), /* SCI9 RXI (Received data full) */ + [9] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */ + [10] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */ + [11] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */ + [12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ + [13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ + [14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ + [15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ + [16] = BSP_PRV_IELS_ENUM(EVENT_AGT1_INT), /* AGT1 INT (AGT interrupt) */ + [17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ7), /* ICU IRQ7 (External pin interrupt 7) */ + [18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ11), /* ICU IRQ11 (External pin interrupt 11) */ + [19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ12), /* ICU IRQ12 (External pin interrupt 12) */ + [20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ13), /* ICU IRQ13 (External pin interrupt 13) */ + [21] = BSP_PRV_IELS_ENUM(EVENT_SPI1_RXI), /* SPI1 RXI (Receive buffer full) */ + [22] = BSP_PRV_IELS_ENUM(EVENT_SPI1_TXI), /* SPI1 TXI (Transmit buffer empty) */ + [23] = BSP_PRV_IELS_ENUM(EVENT_SPI1_TEI), /* SPI1 TEI (Transmission complete event) */ + [24] = BSP_PRV_IELS_ENUM(EVENT_SPI1_ERI), /* SPI1 ERI (Error) */ + [25] = BSP_PRV_IELS_ENUM(EVENT_IIC1_RXI), /* IIC1 RXI (Receive data full) */ + [26] = BSP_PRV_IELS_ENUM(EVENT_IIC1_TXI), /* IIC1 TXI (Transmit data empty) */ + [27] = BSP_PRV_IELS_ENUM(EVENT_IIC1_TEI), /* IIC1 TEI (Transmit end) */ + [28] = BSP_PRV_IELS_ENUM(EVENT_IIC1_ERI), /* IIC1 ERI (Transfer error) */ + [29] = BSP_PRV_IELS_ENUM(EVENT_SDHIMMC1_ACCS), /* SDHIMMC1 ACCS (Card access) */ + [30] = BSP_PRV_IELS_ENUM(EVENT_SDHIMMC1_CARD), /* SDHIMMC1 CARD (Card detect) */ + [31] = BSP_PRV_IELS_ENUM(EVENT_SDHIMMC1_DMA_REQ), /* SDHIMMC1 DMA REQ (DMA transfer request) */ + [32] = BSP_PRV_IELS_ENUM(EVENT_EDMAC0_EINT), /* EDMAC0 EINT (EDMAC 0 interrupt) */ + [33] = BSP_PRV_IELS_ENUM(EVENT_GLCDC_LINE_DETECT), /* GLCDC LINE DETECT (Specified line) */ + [34] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TXI), /* SCI0 TXI (Transmit data empty) */ + [35] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TEI), /* SCI0 TEI (Transmit end) */ + [36] = BSP_PRV_IELS_ENUM(EVENT_SCI0_RXI), /* SCI0 RXI (Receive data full) */ + [37] = BSP_PRV_IELS_ENUM(EVENT_PDC_INT), /* PDC INT (Error interrupt) */ + [38] = BSP_PRV_IELS_ENUM(EVENT_PDC_RECEIVE_DATA_READY), /* PDC RECEIVE DATA READY (Receive data ready interrupt) */ + [39] = BSP_PRV_IELS_ENUM(EVENT_JPEG_JEDI), /* JPEG JEDI (Compression/decompression process interrupt) */ + [40] = BSP_PRV_IELS_ENUM(EVENT_JPEG_JDTI), /* JPEG JDTI (Data transfer interrupt) */ + [41] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */ + [42] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */ + [43] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */ + [44] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1), /* USBFS FIFO 1 (DMA transfer request 1) */ + [45] = BSP_PRV_IELS_ENUM(EVENT_USBHS_USB_INT_RESUME), /* USBHS USB INT RESUME (USBHS interrupt) */ + [46] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_0), /* USBHS FIFO 0 (DMA transfer request 0) */ + [47] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_1), /* USBHS FIFO 1 (DMA transfer request 1) */ +}; +#endif diff --git a/ports/renesas-ra/boards/VK_RA6M3/ra_gen/vector_data.h b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/vector_data.h new file mode 100644 index 0000000000000..6dc5cf6bffc4a --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/ra_gen/vector_data.h @@ -0,0 +1,148 @@ +/* generated vector header file - do not edit */ +#ifndef VECTOR_DATA_H +#define VECTOR_DATA_H +#ifdef __cplusplus +extern "C" { +#endif +/* Number of interrupts allocated */ +#ifndef VECTOR_DATA_IRQ_COUNT +#define VECTOR_DATA_IRQ_COUNT (48) +#endif +/* ISR prototypes */ +void sci_uart_rxi_isr(void); +void sci_uart_txi_isr(void); +void sci_uart_tei_isr(void); +void sci_uart_eri_isr(void); +void rtc_alarm_periodic_isr(void); +void rtc_carry_isr(void); +void agt_int_isr(void); +void r_icu_isr(void); +void spi_rxi_isr(void); +void spi_txi_isr(void); +void spi_tei_isr(void); +void spi_eri_isr(void); +void iic_master_rxi_isr(void); +void iic_master_txi_isr(void); +void iic_master_tei_isr(void); +void iic_master_eri_isr(void); +void sdhimmc_accs_isr(void); +void sdhimmc_card_isr(void); +void sdhimmc_dma_req_isr(void); +void ether_eint_isr(void); +void glcdc_line_detect_isr(void); +void sci_i2c_txi_isr(void); +void sci_i2c_tei_isr(void); +void sci_i2c_rxi_isr(void); +void pdc_int_isr(void); +void pdc_transfer_req_isr(void); +void jpeg_jedi_isr(void); +void jpeg_jdti_isr(void); +void usbfs_interrupt_handler(void); +void usbfs_resume_handler(void); +void usbfs_d0fifo_handler(void); +void usbfs_d1fifo_handler(void); +void usbhs_interrupt_handler(void); +void usbhs_d0fifo_handler(void); +void usbhs_d1fifo_handler(void); + +/* Vector table allocations */ +#define VECTOR_NUMBER_SCI7_RXI ((IRQn_Type)0) /* SCI7 RXI (Received data full) */ +#define SCI7_RXI_IRQn ((IRQn_Type)0) /* SCI7 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI7_TXI ((IRQn_Type)1) /* SCI7 TXI (Transmit data empty) */ +#define SCI7_TXI_IRQn ((IRQn_Type)1) /* SCI7 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI7_TEI ((IRQn_Type)2) /* SCI7 TEI (Transmit end) */ +#define SCI7_TEI_IRQn ((IRQn_Type)2) /* SCI7 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI7_ERI ((IRQn_Type)3) /* SCI7 ERI (Receive error) */ +#define SCI7_ERI_IRQn ((IRQn_Type)3) /* SCI7 ERI (Receive error) */ +#define VECTOR_NUMBER_SCI8_RXI ((IRQn_Type)4) /* SCI8 RXI (Received data full) */ +#define SCI8_RXI_IRQn ((IRQn_Type)4) /* SCI8 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI8_TXI ((IRQn_Type)5) /* SCI8 TXI (Transmit data empty) */ +#define SCI8_TXI_IRQn ((IRQn_Type)5) /* SCI8 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI8_TEI ((IRQn_Type)6) /* SCI8 TEI (Transmit end) */ +#define SCI8_TEI_IRQn ((IRQn_Type)6) /* SCI8 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI8_ERI ((IRQn_Type)7) /* SCI8 ERI (Receive error) */ +#define SCI8_ERI_IRQn ((IRQn_Type)7) /* SCI8 ERI (Receive error) */ +#define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type)8) /* SCI9 RXI (Received data full) */ +#define SCI9_RXI_IRQn ((IRQn_Type)8) /* SCI9 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */ +#define SCI9_TXI_IRQn ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */ +#define SCI9_TEI_IRQn ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type)11) /* SCI9 ERI (Receive error) */ +#define SCI9_ERI_IRQn ((IRQn_Type)11) /* SCI9 ERI (Receive error) */ +#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ +#define RTC_ALARM_IRQn ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ +#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ +#define RTC_PERIOD_IRQn ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ +#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ +#define RTC_CARRY_IRQn ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ +#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ +#define AGT0_INT_IRQn ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ +#define VECTOR_NUMBER_AGT1_INT ((IRQn_Type)16) /* AGT1 INT (AGT interrupt) */ +#define AGT1_INT_IRQn ((IRQn_Type)16) /* AGT1 INT (AGT interrupt) */ +#define VECTOR_NUMBER_ICU_IRQ7 ((IRQn_Type)17) /* ICU IRQ7 (External pin interrupt 7) */ +#define ICU_IRQ7_IRQn ((IRQn_Type)17) /* ICU IRQ7 (External pin interrupt 7) */ +#define VECTOR_NUMBER_ICU_IRQ11 ((IRQn_Type)18) /* ICU IRQ11 (External pin interrupt 11) */ +#define ICU_IRQ11_IRQn ((IRQn_Type)18) /* ICU IRQ11 (External pin interrupt 11) */ +#define VECTOR_NUMBER_ICU_IRQ12 ((IRQn_Type)19) /* ICU IRQ12 (External pin interrupt 12) */ +#define ICU_IRQ12_IRQn ((IRQn_Type)19) /* ICU IRQ12 (External pin interrupt 12) */ +#define VECTOR_NUMBER_ICU_IRQ13 ((IRQn_Type)20) /* ICU IRQ13 (External pin interrupt 13) */ +#define ICU_IRQ13_IRQn ((IRQn_Type)20) /* ICU IRQ13 (External pin interrupt 13) */ +#define VECTOR_NUMBER_SPI1_RXI ((IRQn_Type)21) /* SPI1 RXI (Receive buffer full) */ +#define SPI1_RXI_IRQn ((IRQn_Type)21) /* SPI1 RXI (Receive buffer full) */ +#define VECTOR_NUMBER_SPI1_TXI ((IRQn_Type)22) /* SPI1 TXI (Transmit buffer empty) */ +#define SPI1_TXI_IRQn ((IRQn_Type)22) /* SPI1 TXI (Transmit buffer empty) */ +#define VECTOR_NUMBER_SPI1_TEI ((IRQn_Type)23) /* SPI1 TEI (Transmission complete event) */ +#define SPI1_TEI_IRQn ((IRQn_Type)23) /* SPI1 TEI (Transmission complete event) */ +#define VECTOR_NUMBER_SPI1_ERI ((IRQn_Type)24) /* SPI1 ERI (Error) */ +#define SPI1_ERI_IRQn ((IRQn_Type)24) /* SPI1 ERI (Error) */ +#define VECTOR_NUMBER_IIC1_RXI ((IRQn_Type)25) /* IIC1 RXI (Receive data full) */ +#define IIC1_RXI_IRQn ((IRQn_Type)25) /* IIC1 RXI (Receive data full) */ +#define VECTOR_NUMBER_IIC1_TXI ((IRQn_Type)26) /* IIC1 TXI (Transmit data empty) */ +#define IIC1_TXI_IRQn ((IRQn_Type)26) /* IIC1 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_IIC1_TEI ((IRQn_Type)27) /* IIC1 TEI (Transmit end) */ +#define IIC1_TEI_IRQn ((IRQn_Type)27) /* IIC1 TEI (Transmit end) */ +#define VECTOR_NUMBER_IIC1_ERI ((IRQn_Type)28) /* IIC1 ERI (Transfer error) */ +#define IIC1_ERI_IRQn ((IRQn_Type)28) /* IIC1 ERI (Transfer error) */ +#define VECTOR_NUMBER_SDHIMMC1_ACCS ((IRQn_Type)29) /* SDHIMMC1 ACCS (Card access) */ +#define SDHIMMC1_ACCS_IRQn ((IRQn_Type)29) /* SDHIMMC1 ACCS (Card access) */ +#define VECTOR_NUMBER_SDHIMMC1_CARD ((IRQn_Type)30) /* SDHIMMC1 CARD (Card detect) */ +#define SDHIMMC1_CARD_IRQn ((IRQn_Type)30) /* SDHIMMC1 CARD (Card detect) */ +#define VECTOR_NUMBER_SDHIMMC1_DMA_REQ ((IRQn_Type)31) /* SDHIMMC1 DMA REQ (DMA transfer request) */ +#define SDHIMMC1_DMA_REQ_IRQn ((IRQn_Type)31) /* SDHIMMC1 DMA REQ (DMA transfer request) */ +#define VECTOR_NUMBER_EDMAC0_EINT ((IRQn_Type)32) /* EDMAC0 EINT (EDMAC 0 interrupt) */ +#define EDMAC0_EINT_IRQn ((IRQn_Type)32) /* EDMAC0 EINT (EDMAC 0 interrupt) */ +#define VECTOR_NUMBER_GLCDC_LINE_DETECT ((IRQn_Type)33) /* GLCDC LINE DETECT (Specified line) */ +#define GLCDC_LINE_DETECT_IRQn ((IRQn_Type)33) /* GLCDC LINE DETECT (Specified line) */ +#define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)34) /* SCI0 TXI (Transmit data empty) */ +#define SCI0_TXI_IRQn ((IRQn_Type)34) /* SCI0 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)35) /* SCI0 TEI (Transmit end) */ +#define SCI0_TEI_IRQn ((IRQn_Type)35) /* SCI0 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)36) /* SCI0 RXI (Receive data full) */ +#define SCI0_RXI_IRQn ((IRQn_Type)36) /* SCI0 RXI (Receive data full) */ +#define VECTOR_NUMBER_PDC_INT ((IRQn_Type)37) /* PDC INT (Error interrupt) */ +#define PDC_INT_IRQn ((IRQn_Type)37) /* PDC INT (Error interrupt) */ +#define VECTOR_NUMBER_PDC_RECEIVE_DATA_READY ((IRQn_Type)38) /* PDC RECEIVE DATA READY (Receive data ready interrupt) */ +#define PDC_RECEIVE_DATA_READY_IRQn ((IRQn_Type)38) /* PDC RECEIVE DATA READY (Receive data ready interrupt) */ +#define VECTOR_NUMBER_JPEG_JEDI ((IRQn_Type)39) /* JPEG JEDI (Compression/decompression process interrupt) */ +#define JPEG_JEDI_IRQn ((IRQn_Type)39) /* JPEG JEDI (Compression/decompression process interrupt) */ +#define VECTOR_NUMBER_JPEG_JDTI ((IRQn_Type)40) /* JPEG JDTI (Data transfer interrupt) */ +#define JPEG_JDTI_IRQn ((IRQn_Type)40) /* JPEG JDTI (Data transfer interrupt) */ +#define VECTOR_NUMBER_USBFS_INT ((IRQn_Type)41) /* USBFS INT (USBFS interrupt) */ +#define USBFS_INT_IRQn ((IRQn_Type)41) /* USBFS INT (USBFS interrupt) */ +#define VECTOR_NUMBER_USBFS_RESUME ((IRQn_Type)42) /* USBFS RESUME (USBFS resume interrupt) */ +#define USBFS_RESUME_IRQn ((IRQn_Type)42) /* USBFS RESUME (USBFS resume interrupt) */ +#define VECTOR_NUMBER_USBFS_FIFO_0 ((IRQn_Type)43) /* USBFS FIFO 0 (DMA transfer request 0) */ +#define USBFS_FIFO_0_IRQn ((IRQn_Type)43) /* USBFS FIFO 0 (DMA transfer request 0) */ +#define VECTOR_NUMBER_USBFS_FIFO_1 ((IRQn_Type)44) /* USBFS FIFO 1 (DMA transfer request 1) */ +#define USBFS_FIFO_1_IRQn ((IRQn_Type)44) /* USBFS FIFO 1 (DMA transfer request 1) */ +#define VECTOR_NUMBER_USBHS_USB_INT_RESUME ((IRQn_Type)45) /* USBHS USB INT RESUME (USBHS interrupt) */ +#define USBHS_USB_INT_RESUME_IRQn ((IRQn_Type)45) /* USBHS USB INT RESUME (USBHS interrupt) */ +#define VECTOR_NUMBER_USBHS_FIFO_0 ((IRQn_Type)46) /* USBHS FIFO 0 (DMA transfer request 0) */ +#define USBHS_FIFO_0_IRQn ((IRQn_Type)46) /* USBHS FIFO 0 (DMA transfer request 0) */ +#define VECTOR_NUMBER_USBHS_FIFO_1 ((IRQn_Type)47) /* USBHS FIFO 1 (DMA transfer request 1) */ +#define USBHS_FIFO_1_IRQn ((IRQn_Type)47) /* USBHS FIFO 1 (DMA transfer request 1) */ +#ifdef __cplusplus +} +#endif +#endif /* VECTOR_DATA_H */ diff --git a/ports/renesas-ra/boards/VK_RA6M3/vk_ra6m3.ld b/ports/renesas-ra/boards/VK_RA6M3/vk_ra6m3.ld new file mode 100644 index 0000000000000..a25e5121e2f17 --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/vk_ra6m3.ld @@ -0,0 +1,315 @@ +/* + Linker File for RA6M3 MCU +*/ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 /* 1MB/2MB */ + FLASH_FS (r) : ORIGIN = 0x00100000, LENGTH = 0x00100000 /* 1MB/2MB */ + RAM (rwx) : ORIGIN = 0x1FFE0000, LENGTH = 0x000A0000 /* 640KB */ + FB0 (rwx) : ORIGIN = 0x20040000, LENGTH = 0x003FC00 /* 255K */ + DATA_FLASH (rx) : ORIGIN = 0x40100000, LENGTH = 0x00010000 /* 64KB */ + QSPI_FLASH (rx) : ORIGIN = 0x60000000, LENGTH = 0x01000000 /* 16MB/64MB */ + ID_CODE (rx) : ORIGIN = 0x0100A150, LENGTH = 0x00000010 /* 32bytes */ +} + +/* Library configurations */ +/*GROUP(libgcc.a libc.a libm.a libnosys.a) */ + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + _stext = .; + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + __end__ = .; + + /* ROM Registers start at address 0x00000400 */ + . = __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = __ROM_Start + 0x500; + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + _etext = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + _sidata = .; + _sdata = .; + __data_start__ = .; + *(vtable) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM AT > FLASH + + + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + __noinit_end = .; + } > RAM + + .fb0 : + { + . = ALIGN(64); + __fb0_start = .; + *(.fb0*); + __fb0_end = .; + } > FB0 + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + _estack = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* Data flash. */ + .data_flash : + { + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + } > DATA_FLASH + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE +} +/* produce a link error if there is not this amount of RAM for these sections */ +/* _minimum_stack_size = 2K; */ +/* _minimum_heap_size = 16K; */ + +/* Define tho top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_start = __HeapBase; /* heap starts just after statically allocated memory */ +_heap_end = __HeapLimit; /* tunable */ + +_micropy_hw_internal_flash_storage_start = ORIGIN(FLASH_FS); +_micropy_hw_internal_flash_storage_end = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS); + +_micropy_hw_external_flash_storage_start = ORIGIN(QSPI_FLASH); +_micropy_hw_external_flash_storage_end = ORIGIN(QSPI_FLASH) + LENGTH(QSPI_FLASH); diff --git a/ports/renesas-ra/boards/VK_RA6M3/vk_ra6m3_conf.h b/ports/renesas-ra/boards/VK_RA6M3/vk_ra6m3_conf.h new file mode 100644 index 0000000000000..8391b4f2d2cff --- /dev/null +++ b/ports/renesas-ra/boards/VK_RA6M3/vk_ra6m3_conf.h @@ -0,0 +1,30 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Vekatech Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef VK_RA6M3_CONF_H +#define VK_RA6M3_CONF_H + +#define DEBUG_CH 7 + +#endif /* VK_RA6M3_CONF_H */ diff --git a/ports/renesas-ra/boards/VK_RA6M5/board.json b/ports/renesas-ra/boards/VK_RA6M5/board.json index 48371138b19f6..6cf1a34f831cb 100644 --- a/ports/renesas-ra/boards/VK_RA6M5/board.json +++ b/ports/renesas-ra/boards/VK_RA6M5/board.json @@ -2,9 +2,14 @@ "deploy": [ "../deploy.md" ], - "docs": "", + "docs": "https://vekatech.com/VK-RA6M5_docs/brochures/VK-RA6M5%20Flyer%20R2.pdf", "features": [ - "DAC" + "DAC", + "USB", + "microSD", + "Ethernet", + "Camera", + "Display" ], "images": [ "VK-RA6M5.jpg" @@ -12,6 +17,6 @@ "mcu": "ra6m5", "product": "VK-RA6M5", "thumbnail": "", - "url": "https://vekatech.com/VK-RA6M5_docs/brochures/VK-RA6M5%20Flyer%20R2.pdf", + "url": "https://vekatech.com", "vendor": "Vekatech" } diff --git a/ports/renesas-ra/boards/ra6m3_af.csv b/ports/renesas-ra/boards/ra6m3_af.csv new file mode 100644 index 0000000000000..f08975038150b --- /dev/null +++ b/ports/renesas-ra/boards/ra6m3_af.csv @@ -0,0 +1,193 @@ +CPU_PIN,PORT_IDX,PORT_BIT,Analog,IRQ,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,AF16,AF17,AF18,AF19,AF20,AF21,AF22,AF23,AF24,AF25,AF26, +P000,0,0,AN000,IRQ6-DS,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P001,0,1,AN001,IRQ7-DS,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P002,0,2,AN002,IRQ8-DS,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P003,0,3,AN007,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P004,0,4,AN100,IRQ9-DS,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P005,0,5,AN101,RQ10-DS,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P006,0,6,AN102,IRQ11-DS,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P007,0,7,AN107,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P008,0,8,AN003,IRQ12-DS,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,, +P009,0,9,AN004,IRQ13-DS,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,, +P010,0,10,AN103,IRQ14-DS,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,0,11,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,0,12,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,0,13,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P014,0,14,AN005,,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,, +P015,0,15,AN006,IRQ13,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,, +P100,1,0,,IRQ2,Hi-Z,AGTIO0,GTETRGA,GTIOC5B,RXD0/MISO0/SCL0,SCK1,MISOA_A,SCL1_B,KR00,,,D00[A00/D00],,,,,,,,,,,,,,LCD_EXTCLK_A,, +P101,1,1,,IRQ1,Hi-Z,AGTEE0,GTETRGB,GTIOC5A,TXD0/MOSI0/SDA0,CTS1_RTS1/SS1,MOSIA_A,SDA1_B,KR01,,,D01[A01/D01],,,,,,,,,,,,,,LCD_CLK_A,, +P102,1,2,,,Hi-Z,AGTO0,GTOWLO,GTIOC2B_A,SCK0,,RSPCKA_A,,KR02,,ADTRG0,D02[A02/D02],,,,,CRX0,,,,,,,,,LCD_TCON0_A,, +P103,1,3,,,Hi-Z,,GTOWUP,GTIOC2A_A,CTS0_RTS0/SS0,,SSLA0_A,,KR03,,,D03[A03/D03],,,,,CTX0,,,,,,,,,LCD_TCON1_A,, +P104,1,4,,IRQ1,Hi-Z,,GTETRGB,GTIOC1B,RXD8/MISO8/SCL8,,SSLA1_A,,KR04,,,D04[A04/D04],,,,,,,,,,,,,,LCD_TCON2_A,, +P105,1,5,,IRQ0,Hi-Z,,GTETRGA,GTIOC1A,TXD8/MOSI8/SDA8,,SSLA2_A,,KR05,,,D05[A05/D05],,,,,,,,,,,,,,LCD_TCON3_A,, +P106,1,6,,,Hi-Z,AGTOB0,,GTIOC8B,SCK8,,SSLA3_A,,KR06,,,D06[A06/D06],,,,,,,,,,,,,,LCD_DATA00_A,, +P107,1,7,,,Hi-Z,AGTOA0,,GTIOC8A,CTS8_RTS8/SS8,,,,KR07,,,D07[A07/D07],,,,,,,,,,,,,,LCD_DATA01_A,, +P108,1,8,,,TMS/SWDIO,,GTOULO,GTIOC0B_A,,CTS9_RTS9/SS9,SSLB0_B,,,,,,,,,,,,,,,,,,,,, +P109,1,9,,,TDO/SWO,,GTOVUP,GTIOC1A_A,,TXD9/MOSI9/SDA9,MOSIB_B,,,CLKOUT,,,,,,,CTX1,,,,,,,,,,, +P110,1,10,,IRQ3,TDI,,GTOVLO,GTIOC1B_A,CTS2_RTS2/SS2,RXD9/MISO9/SCL9,MISOB_B,,,VCOUT,,,,,,,CRX1,,,,,,,,,,, +P111,1,11,,IRQ4,Hi-Z,,,GTIOC3A_A,SCK2,SCK9,RSPCKB_B,,,,,A05,,,,,,,,,,,,,,LCD_DATA12_A,, +P112,1,12,,,Hi-Z,,,GTIOC3B_A,TXD2/MOSI2/SDA2,SCK1,SSLB0_B,,,,,A04,,,,,,,SSIBCK0_B,,,,,,,LCD_DATA11_A,, +P113,1,13,,,Hi-Z,,,GTIOC2A,RXD2/MISO2/SCL2,,,,,,,A03,,,,,,,SSILRCK0/SSIFS0_B,,,,,,,LCD_DATA10_A,, +P114,1,14,,,Hi-Z,,,GTIOC2B,,,,,,,,A02,,,,,,,SSIRXD0_B,,,,,,,LCD_DATA09_A,, +P115,1,15,,,Hi-Z,,,GTIOC4A,,,,,,,,A01,,,,,,,SSITXD0_B,,,,,,,LCD_DATA08_A,, +P200,2,0,,NMI,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,, +P201,2,1,,,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,, +P202,2,2,,IRQ3-DS,Hi-Z,,,GTIOC5B,SCK2,RXD9/MISO9/SCL9,MISOB_A,,,,,WR1/BC1,,,,,CRX0,,,,,SD0DAT6_A,ET0_ERXD2,,,LCD_TCON3_B,, +P203,2,3,,IRQ2-DS,Hi-Z,,,GTIOC5A,CTS2_RTS2/SS2,TXD9/MOSI9/SDA9,MOSIB_A,,,,,A19,TSCAP,,,,CTX0,,,,,SD0DAT5_A,ET0_COL,,,,, +P204,2,4,,,Hi-Z,AGTIO1,GTIW,GTIOC4B,SCK4,SCK9,RSPCKB_A,SCL0_B,,,CACREF,A18,TS00,,,,,,SSIBCK1_A,USB_OVRCURB-DS,,SD0DAT4_A ,ET0_RX_DV,,,,, +P205,2,5,,IRQ1-DS,Hi-Z,AGTO1,GTIV,GTIOC4A,TXD4/MOSI4/SDA4,CTS9_RTS9/SS9,SSLB0_A,SCL1_A,,CLKOUT,,A16,TSCAP,,,,,,SSILRCK1/SSIFS1_A,USB_OVRCURA-DS,,SD0DAT3_A,ET0_WOL,ET0_WOL,,,, +P206,2,6,,IRQ0-DS,Hi-Z,,GTIU,,RXD4/MISO4/SCL4,,SSLB1_A,SDA1_A,,,,WAIT,TS01,,,,,,SSIDATA1_A,USB_VBUSEN,,SD0DAT2_A,ET0_LINKSTA,ET0_LINKSTA,,,, +P207,2,7,,,Hi-Z,,,,,,SSLB2_A,,,,,A17,TS02,,,,,QSSL,,,,,,,,LCD_DATA23_B,, +P208,2,8,,,Hi-Z,,GTOVL0,,,,,,,,,,,,,,,QIO3,,,,SD0DAT0_B,ET0_LINKST,ET0_LINKST,,LCD_DATA18_B,TDATA3, +P209,2,9,,,Hi-Z,,GTOVUP,,,,,,,,,,,,,,,QIO2,,,,SD0WP,ET0_EXOUT,ET0_EXOUT,,LCD_DATA19_B,TDATA2, +P210,2,10,,,Hi-Z,,GTIW,,,,,,,,,,,,,,,QIO1,,,,SD0CD,ET0_WOL,ET0_WOL,,LCD_DATA20_B,TDATA1, +P211,2,11,,,Hi-Z,,GTIV,,,,,,,,,,,,,,,QIO0,,,,SD0CMD_B,ET0_MDIO,ET0_MDIO,,LCD_DATA21_B,TDATA0, +P212,2,12,,IRQ3,Hi-Z,AGTEE1,GTETRGD,GTIOC0B,,RXD1/MISO1/SCL1,,,,,,,,,,,,,,,,,,,,,, +P213,2,13,,IRQ2,Hi-Z,,GTETRGC,GTIOC0A,,TXD1/MOSI1/SDA1,,,,,ADTRG1,,,,,,,,,,,,,,,,, +P214,2,14,,,Hi-Z,,GTIU,,,,,,,,,,,,,,,QSPCLK,,,,SD0CLK_B,ET0_MDC,ET0_MDC,,LCD_DATA22_B, TCLK, +-,2,15,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P300,3,0,,,TCK/SWCLK,,,GTIOC0A_A,,,SSLB1_B,,,,,,,,,,,,,,,,,,,,, +P301,3,1,,IRQ6,Hi-Z,AGTIO0,GTOULO,GTIOC4B,RXD2/MISO2/SCL2,CTS9_RTS9/SS9,SSLB2_B,,,,,A06,,,,,,,,,,,,,,LCD_DATA13_A,, +P302,3,2,,IRQ5,Hi-Z,,GTOUUP,GTIOC4A,TXD2/MOSI2/SDA2,,SSLB3_B,,,,,A07,,,,,,,,,,,,,,LCD_DATA14_A,, +P303,3,3,,,Hi-Z,,,GTIOC7B,,,,,,,,A08,,,,,,,,,,,,,,LCD_DATA15_A,, +P304,3,4,,IRQ9,Hi-Z,,GTOWLO,GTIOC7A,RXD6/MISO6/SCL6,,,,,,,A09,,,,,,,,,,,,,,LCD_DATA16_A,, +P305,3,5,,IRQ8,Hi-Z,,GTOWUP,,TXD6/MOSI6/SDA6,,,,,,,A10,,,,,,QSPCLK,,,,,,,,LCD_DATA17_A,, +P306,3,6,,,Hi-Z,,GTOULO,,SCK6,,,,,,,A11,,,,,,QSSL,,,,,,,,LCD_DATA18_A,, +P307,3,7,,,Hi-Z,,GTOUUP,,CTS6_RTS6/SS6,,,,,,,A12,,,,,,QIO0,,,,,,,,LCD_DATA19_A,, +P308,3,8,,,Hi-Z,,,,,,,,,,,A13,,,,,,QIO1,,,,,,,,LCD_DATA20_A,, +P309,3,9,,,Hi-Z,,,,,RXD3,,,,,,A14,,,,,,QIO2,,,,,,,,LCD_DATA21_A,, +P310,3,10,,,Hi-Z,AGTEE1,,,,TXD3,,,,,,A15,,,,,,QIO3,,,,,,,,LCD_DATA22_A,, +P311,3,11,,,Hi-Z,AGTOB1,,,,SCK3,,,,,,CS2/RAS,,,,,,,,,,,,,,LCD_DATA23_A,, +P312,3,12,,,Hi-Z,AGTOA1,,,,CTS3_RTS3/SS3,,,,,,CS3/CAS,,,,,,,,,,,,,,,, +P313,3,13,,,Hi-Z,,,,,,,,,,,A20,,,,,,,,,,SD0DAT7_A,ET0_ERXD3,,,LCD_TCON2_B,, +P314,3,14,,,Hi-Z,,,,,,,,,,ADTRG0,A21,,,,,,,,,,,,,,LCD_TCON1_B,, +P315,3,15,,,Hi-Z,,,,RXD4,,,,,,,A22,,,,,,,,,,,,,,LCD_TCON0_B,, +P400,4,0,,IRQ0,Hi-Z,AGTIO1,,GTIOC6A,SCK4,SCK7,,SCL0_A,,,ADTRG1,,,,,,,,AUDIO_CLK,,,,ET0_WOL,ET0_WOL,,,, +P401,4,1,,IRQ5-DS,Hi-Z,,GTETRGA,GTIOC6B,CTS4_RTS4/SS4,TXD7/MOSI7/SDA7,,SDA0_A,,,,,,,,,CTX0,,,,,,ET0_MDC,ET0_MDC,,,, +P402,4,2,,IRQ4-DS,Hi-Z,,,,,RXD7/MISO7/SCL7,,,,,CACREF,,,,,,CRX0,,AUDIO_CLK,,,,ET0_MDIO,ET0_MDIO,VSYNC,,, +P403,4,3,,,Hi-Z,,,GTIOC3A,,CTS7_RTS7/SS7,,,,,,,,,,,,,SSIBCK0_A,,,SD1DAT7_B,ET0_LINKSTA,ET0_LINKSTA,PIXD7,,, +P404,4,4,,,Hi-Z,,,GTIOC3B,,,,,,,,,,,,,,,SSILRCK0/SSIFS0_A,,,SD1DAT6_B,ET0_EXOUT,ET0_EXOUT,PIXD6,,, +P405,4,5,,,Hi-Z,,,GTIOC1A,,,,,,,,,,,,,,,SSITXD0_A,,,SD1DAT5_B,ET0_TX_EN,RMII0_TXD_EN_B,PIXD5,,, +P406,4,6,,,Hi-Z,,,GTIOC1B,,,SSLB3_C,,,,,,,,,,,,SSIRXD0_A,,,SD1DAT4_B,ET0_RX_ER,RMII0_TXD1_B,PIXD4,,, +P407,4,7,,,Hi-Z,AGTIO0,,,CTS4_RTS4/SS4,,SSLB3_A,SDA0_B,,RTCOUT,ADTRG0,,TS03,,,,,,,USB_VBUS,,,ET0_EXOUT,ET0_EXOUT,,,, +P408,4,8,,IRQ7,Hi-Z,,GTOWLO,GTIOC10B,,RXD3/MISO3/SCL3,,SCL0_B,,,,,TS04,,,,,,,USB_ID,,,ET0_CRS,RMII0_CRS_DV_A,PIXCLK,,, +P409,4,9,,IRQ6,Hi-Z,,GTOWUP,GTIOC10A,,TXD3/MOSI3/SDA3,,,,,,,TS05,,,,,,,USB_EXICEN,,,ET0_RX_CLK,RMII0_RX_ER_A,HSYNC,,, +P410,4,10,,IRQ5,Hi-Z,AGTOB1,GTOVLO,GTIOC9B,RXD0/MISO0/SCL0,SCK3,MISOA_B,,,,,,TS06,,,,,,,,,SD0DAT1_A,ET0_ERXD0,RMII0_RXD1_A,PIXD0,,, +P411,4,11,,IRQ4,Hi-Z,AGTOA1,GTOVUP,GTIOC9A,TXD0/MOSI0/SDA0,CTS3_RTS3/SS3,MOSIA_B,,,,,,TS07,,,,,,,,,SD0DAT0_A,ET0_ERXD1,RMII0_RXD0_A,PIXD1,,, +P412,4,12,,,Hi-Z,AGTEE1,GTOULO,,SCK0,,RSPCKA_B,,,,,,TS08,,,,,,,,,SD0CMD_A,ET0_ETXD0,REF50CK0_A,PIXD2,,, +P413,4,13,,,Hi-Z,,GTOUUP,,CTS0_RTS0/SS0,,SSLA0_B,,,,,,TS09,,,,,,,,,SD0CLK_A,ET0_ETXD1,RMII0_TXD0_A,PIXD3,,, +P414,4,14,,IRQ9,Hi-Z,,,GTIOC0B,,,SSLA1_B,,,,,,TS10,,,,,,,,,SD0WP,,RMII0_TXD1_A,PIXD4,,, +P415,4,15,,IRQ8,Hi-Z,,,GTIOC0A,,,SSLA2_B,,,,,,TS11,,,,,,,USB_VBUSEN,,SD0CD,ET0_TX_EN,RMII0_TXD_EN_A,PIXD5,,, +P500,5,0,AN016,,Hi-Z,AGTOA0,GTIU,GTIOC11A,,,,,,,,,,,,,,QSPCLK,,USB_VBUSEN,,SD1CLK_A ,,,,,, +P501,5,1,AN116,IRQ11,Hi-Z,AGTOB0,GTIV,GTIOC11B,,TXD5/MOSI5/SDA5,,,,,,,,,,,,QSSL,,USB_OVRCURA,,SD1CMD_A,,,,,, +P502,5,2,AN017,IRQ12,Hi-Z,,GTIW,GTIOC12A,,RXD5/MISO5/SCL5,,,,,,,,,,,,QIO0,,USB_OVRCURB,,SD1DAT0_A,,,,,, +P503,5,3,AN117,,Hi-Z,,GTETRGC,GTIOC12B,CTS6_RTS6/SS6,SCK5,,,,,,,,,,,,QIO1,,USB_EXICEN,,SD1DAT1_A,,,,,, +P504,5,4,AN018,,Hi-Z,,GTETRGD,GTIOC13A,SCK6,CTS5_RTS5/SS5,,,,,,ALE,,,,,,QIO2,,USB_ID,,SD1DAT2_A,,,,,, +P505,5,5,AN118,IRQ14,Hi-Z,,,GTIOC13B,RXD6/MISO6/SCL6,,,,,,,,,,,,,QIO3,,,,SD1DAT3_A,,,,,, +P506,5,6,AN019,IRQ15,Hi-Z,,,,TXD6/MOSI6/SDA6,,,,,,,,,,,,,,,,,SD1CD,,,,,, +P507,5,7,AN119,,Hi-Z,,,,,CTS5_RTS5/SS5,,,,,,,,,,,,,,,,SD1WP_A,,,,,, +P508,5,8,AN020,,Hi-Z,,,,SCK6,SCK5,,,,,,,,,,,,,,,,,,,,,, +-,5,9,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,5,10,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P511,5,11,,IRQ15,Hi-Z,,,GTIOC0B,RXD4/MISO4/SCL4,,,SDA2,,,,,,,,,CRX1,,,,,,,,PCKO,,, +P512,5,12,,IRQ14,Hi-Z,,,GTIOC0A,TXD4/MOSI4/SDA4,,,SCL2,,,,,,,,,CTX1,,,,,,,,VSYNC,,, +P513,5,13,,,Hi-Z,,,,,RXD5,,,,,,,,,,,,,,,,,,,,LCD_DATA16_B,, +-,5,14,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,5,15,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P600,6,0,,,Hi-Z,,,GTIOC6B,,SCK9,,,,CLKOUT,CACREF,RD,,,,,,,,,,,,,,LCD_DATA02_A,, +P601,6,1,,,Hi-Z,,,GTIOC6A,,RXD9,,,,,,WR/WR0/DQM00,,,,,,,,,,,,,,LCD_DATA03_A,, +P602,6,2,,,Hi-Z,,,GTIOC7B,,TXD9,,,,,,EBCLK/SDCLK,,,,,,,,,,,,,,LCD_DATA04_A,, +P603,6,3,,,Hi-Z,,,GTIOC7A,,CTS9_RTS9/SS9,,,,,,D13[A13/D13]/DQ13,,,,,,,,,,,,,,,, +P604,6,4,,,Hi-Z,,,GTIOC8B,,,,,,,,D12[A12/D12]/DQ12,,,,,,,,,,,,,,,, +P605,6,5,,,Hi-Z,,,GTIOC8A,,,,,,,,D11[A11/D11]/DQ11,,,,,,,,,,,,,,,, +P606,6,6,,,Hi-Z,,,,CTS8_RTS8/SS8,,,,,RTCOUT,,,,,,,,,,,,,,,,LCD_DATA03_B,, +P607,6,7,,,Hi-Z,,,,RXD8,,,,,,,,,,,,,,,,,,,,,LCD_DATA04_B,, +P608,6,8,,,Hi-Z,,,GTIOC4B,,,,,,,,A00/BC0/DQM1,,,,,,,,,,,,,,LCD_DATA07_A,, +P609,6,9,,,Hi-Z,,,GTIOC5A,,,,,,,,CS1/CKE ,,,,,CTX1,,,,,,,,,LCD_DATA06_A,, +P610,6,10,,,Hi-Z,,,GTIOC5B,,,,,,,,CS0/WE,,,,,CRX1,,,,,,,,,LCD_DATA05_A,, +P611,6,11,,,Hi-Z,,,,,CTS7_RTS7/SS7,,,,CLKOUT,CACREF,SDCS,,,,,,,,,,,,,,,, +P612,6,12,,,Hi-Z,,,,,SCK7,,,,,,D08[A08/D08]/DQ08,,,,,,,,,,,,,,,, +P613,6,13,,,Hi-Z,,,,,TXD7,,,,,,D09[A09/D09]/DQ09,,,,,,,,,,,,,,,, +P614,6,14,,,Hi-Z,,,,,RXD7,,,,,,D10[A10/D10]/DQ10,,,,,,,,,,,,,,,, +P615,6,15,,,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,LCD_DATA10_B,, +P700,7,0,,,Hi-Z,,,GTIOC5A,,,MISOB_C,,,,,,,,,,,,,,,SD1DAT3_B,ET0_ETXD1,RMII0_TXD0_B,PIXD3,,, +P701,7,1,,,Hi-Z,,,GTIOC5B,,,MOSIB_C,,,,,,,,,,,,,,,SD1DAT2_B,ET0_ETXD0,REF50CK0_B,PIXD2,,, +P702,7,2,,,Hi-Z,,,GTIOC6A,,,RSPCKB_C,,,,,,,,,,,,,,,SD1DAT1_B,ET0_ERXD1,RMII0_RXD0_B,PIXD1,,, +P703,7,3,,,Hi-Z,,,GTIOC6B,,,SSLB0_C,,,VCOUT,,,,,,,,,,,,SD1DAT0_B,ET0_ERXD0,RMII0_RXD1_B,PIXD0,,, +P704,7,4,,,Hi-Z,AGTO0,,,,,SSLB1_C,,,,,,,,,,CTX0,,,,,SD1CLK_B,ET0_RX_CLK,RMII0_RX_ER_B,HSYNC,,, +P705,7,5,,,Hi-Z,AGTIO0,,,,,SSLB2_C,,,,,,,,,,CRX0,,,,,SD1CMD_B,ET0_CRS,RMII0_CRS_DV_B,PIXCLK,,, +P706,7,6,,IRQ7,Hi-Z,,,,,RXD3/MISO3/SCL3,,,,,,,,,,,,,,,USBHS_OVRCURB,SD1CD_B,,,,,, +P707,7,7,,IRQ8,Hi-Z,,,,,TXD3/MOSI3/SDA3,,,,,,,,,,,,,,,USBHS_OVRCURA,SD1WP_B,,,,,, +P708,7,8,,IRQ11,Hi-Z,,,,,RXD1/MISO1/SCL1,SSLA3_B,,,,CACREF,,TS12,,,,,,AUDIO_CLK,,,,ET0_ETXD3,,PCKO,,, +P709,7,9,,IRQ10,Hi-Z,,,,,TXD1/MOSI1/SDA1,,,,,,,TS13,,,,,,,,,,ET0_ETXD2,,,,, +P710,7,10,,,Hi-Z,,,,,SCK1,,,,,,,TS14,,,,,,,,,,ET0_TX_ER,,,,, +P711,7,11,,,Hi-Z,AGTEE0,,,,CTS1_RTS1/SS1,,,,,,,TS15,,,,,,,,,,ET0_TX_CLK,,,,, +P712,7,12,,,Hi-Z,AGTOB0,,GTIOC2B,,,,,,,,,TS16,,,,,,,,,,,,,,, +P713,7,13,,,Hi-Z,AGTOA0,,GTIOC2A,,,,,,,,,TS17,,,,,,,,,,,,,,, +-,7,14,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,15,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P800,8,0,,,Hi-Z,,,,,,,,,,,D14[A14/D14]/DQ14,,,,,,,,,,,,,,,, +P801,8,1,,,Hi-Z,,,,,,,,,,,D15[A15/D15]/DQ15,,,,,,,,,,SD1DAT4_A,,,,,, +P802,8,2,,,Hi-Z,,,,,,,,,,,,,,,,,,,,,SD1DAT5_A,,,,LCD_DATA02_B,, +P803,8,3,,,Hi-Z,,,,,,,,,,,,,,,,,,,,,SD1DAT6_A,,,,LCD_DATA01_B,, +P804,8,4,,,Hi-Z,,,,,,,,,,,,,,,,,,,,,SD1DAT7_A,,,,LCD_DATA00_B,, +P805,8,5,,,Hi-Z,,,,,TXD5,,,,,,,,,,,,,,,,,,,,LCD_DATA17_B,, +P806,8,6,,,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,LCD_EXTCLK_B,, +-,8,7,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,8,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,9,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,10,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,11,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,12,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,13,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,14,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,15,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P900,9,0,,,Hi-Z,,,,TXD4,,,,,,,A23,,,,,,,,,,,,,,LCD_CLK_B,, +P901,9,1,,,Hi-Z,AGTIO1,,,SCK4,,,,,,,,,,,,,,,,,,,,,LCD_DATA15_B,, +-,9,2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,3,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P905,9,5,,,Hi-Z,,,GTIOC13B,,,,,,,,CS4,,,,,,,,,,,,,,LCD_DATA11_B,, +P906,9,6,,,Hi-Z,,,GTIOC13A,,,,,,,,CS5,,,,,,,,,,,,,,LCD_DATA12_B,, +P907,9,7,,,Hi-Z,,,GTIOC12B,,,,,,,,CS6,,,,,,,,,,,,,,LCD_DATA13_B,, +P908,9,8,,,Hi-Z,,,GTIOC12A,,,,,,,,CS7,,,,,,,,,,,,,,LCD_DATA14_B,, +-,9,9,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,10,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,11,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,12,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,13,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,14,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,15,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +PA00,A,0,,,Hi-Z,,,,TXD8,,,,,,,,,,,,,,,,,,,,,LCD_DATA05_B,, +PA01,A,1,,,Hi-Z,,,,SCK8,,,,,,,,,,,,,,,,,,,,,LCD_DATA06_B,, +-,A,2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,A,3,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,A,4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,A,5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,A,6,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,A,7,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +PA08,A,8,,,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,LCD_DATA09_B,, +PA09,A,9,,,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,LCD_DATA08_B,, +PA10,A,10,,,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,LCD_DATA07_B,, +-,A,11,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,A,12,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,A,13,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,A,14,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,A,15,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +PB00,B,0,,,Hi-Z,,,,,SCK3,,,,,,,,,,,,,,,USBHS_VBUSEN,,,,,,, +PB01,B,1,,,Hi-Z,,,,,CTS3_RTS3/SS3,,,,,,,,,,,,,,,USBHS_VBUS,,,,,,, +-,B,2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,B,3,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,B,4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,B,5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,B,6,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,B,7,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,B,8,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,B,9,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,B,10,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,B,11,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,B,12,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,B,13,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,B,14,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,B,15,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, diff --git a/ports/renesas-ra/eth.c b/ports/renesas-ra/eth.c new file mode 100644 index 0000000000000..40a7c7d2c3446 --- /dev/null +++ b/ports/renesas-ra/eth.c @@ -0,0 +1,291 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Damien P. George + * Copyright (c) 2023 Vekatech Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include "py/mphal.h" +#include "py/mperrno.h" +#include "shared/netutils/netutils.h" +#include "extmod/modnetwork.h" +#include "hal_data.h" +#include "eth.h" + +#if defined(MICROPY_HW_ETH_MDC) + +#include "lwip/etharp.h" +#include "lwip/dns.h" +#include "lwip/dhcp.h" +#include "netif/ethernet.h" + + +#define ETHER_EXAMPLE_ETHER_ISR_EE_FR_MASK (1UL << 18) +#define ETHER_EXAMPLE_ETHER_ISR_EE_TC_MASK (1UL << 21) +#define ETHER_EXAMPLE_ETHER_ISR_EC_MPD_MASK (1UL << 1) + +typedef struct _eth_t { + uint32_t trace_flags; + struct netif netif; + struct dhcp dhcp_struct; +} eth_t; + +uint8_t tx_TMPbuf[1536] __attribute__((aligned(4))); /* g_ether0_cfg.ether_buffer_size */ +uint8_t rx_TMPbuf[1536] __attribute__((aligned(4))); /* g_ether0_cfg.ether_buffer_size */ + +eth_t eth_instance; +uint8_t phy_link_status = 0; +const machine_pin_obj_t *phy_RST = pin_P400; + +// ETH-LwIP bindings + +#define TRACE_ASYNC_EV (0x0001) +#define TRACE_ETH_TX (0x0002) +#define TRACE_ETH_RX (0x0004) +#define TRACE_ETH_FULL (0x0008) + +STATIC void eth_trace(eth_t *self, size_t len, const void *data, unsigned int flags) { + if (((flags & NETUTILS_TRACE_IS_TX) && (self->trace_flags & TRACE_ETH_TX)) + || (!(flags & NETUTILS_TRACE_IS_TX) && (self->trace_flags & TRACE_ETH_RX))) { + const uint8_t *buf; + if (len == (size_t)-1) { + // data is a pbuf + const struct pbuf *pbuf = data; + buf = pbuf->payload; + len = pbuf->len; // restricted to print only the first chunk of the pbuf + } else { + // data is actual data buffer + buf = data; + } + if (self->trace_flags & TRACE_ETH_FULL) { + flags |= NETUTILS_TRACE_PAYLOAD; + } + netutils_ethernet_trace(MP_PYTHON_PRINTER, len, buf, flags); + } +} + +STATIC void eth_process_frame(eth_t *self, size_t len, const uint8_t *buf) { + eth_trace(self, len, buf, NETUTILS_TRACE_NEWLINE); + + struct netif *netif = &self->netif; + if (netif->flags & NETIF_FLAG_LINK_UP) { + struct pbuf *p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + if (p != NULL) { + pbuf_take(p, buf, len); + if (netif->input(p, netif) != ERR_OK) { + pbuf_free(p); + } + } + } +} + +STATIC err_t eth_netif_output(struct netif *netif, struct pbuf *p) { + // This function should always be called from a context where PendSV-level IRQs are disabled + + LINK_STATS_INC(link.xmit); + eth_trace(netif->state, (size_t)-1, p, NETUTILS_TRACE_IS_TX | NETUTILS_TRACE_NEWLINE); + + pbuf_copy_partial(p, tx_TMPbuf, p->tot_len, 0); + if (FSP_SUCCESS == R_ETHER_Write(&g_ether0_ctrl, tx_TMPbuf, p->tot_len)) { + return ERR_OK; + } else { + return ERR_BUF; + } +} + +STATIC err_t eth_netif_init(struct netif *netif) { + netif->linkoutput = eth_netif_output; + netif->output = etharp_output; + netif->mtu = 1500; + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP; + // Checksums only need to be checked on incoming frames, not computed on outgoing frames + /*NETIF_SET_CHECKSUM_CTRL(netif, + NETIF_CHECKSUM_CHECK_IP + | NETIF_CHECKSUM_CHECK_UDP + | NETIF_CHECKSUM_CHECK_TCP + | NETIF_CHECKSUM_CHECK_ICMP + | NETIF_CHECKSUM_CHECK_ICMP6); + */ + return ERR_OK; +} + +STATIC void eth_lwip_init(eth_t *self) { + // err_t e; + + ip_addr_t ipconfig[4]; + // IP4_ADDR(&ipconfig[0], 0, 0, 0, 0); + // IP4_ADDR(&ipconfig[0], 192, 168, 0, 100); + // IP4_ADDR(&ipconfig[2], 192, 168, 0, 1); + IP4_ADDR(&ipconfig[0], 192, 168, 2, 188); + IP4_ADDR(&ipconfig[2], 192, 168, 2, 254); + IP4_ADDR(&ipconfig[1], 255, 255, 255, 0); + IP4_ADDR(&ipconfig[3], 8, 8, 8, 8); + + MICROPY_PY_LWIP_ENTER + + struct netif *n = &self->netif; + n->name[0] = 'e'; + n->name[1] = '0'; + netif_add(n, &ipconfig[0], &ipconfig[1], &ipconfig[2], self, eth_netif_init, ethernet_input); + netif_set_hostname(n, (const char*)mod_network_hostname); + netif_set_default(n); + netif_set_up(n); + + dns_setserver(0, &ipconfig[3]); + dhcp_set_struct(n, &self->dhcp_struct); + dhcp_start(n); + + netif_set_link_up(n); + + // Wait for DHCP to get IP address + uint32_t start = mp_hal_ticks_ms(); + while (!dhcp_supplied_address(n)) { + if (mp_hal_ticks_ms() - start > 20000) { + mp_raise_msg(&mp_type_OSError, MP_ERROR_TEXT("DHCP failed to get IP address in 10 sec.")); + } + mp_hal_delay_ms(200); + } + + MICROPY_PY_LWIP_EXIT +} + +STATIC void eth_lwip_deinit(eth_t *self) { + MICROPY_PY_LWIP_ENTER + for (struct netif *netif = netif_list; netif != NULL; netif = netif->next) { + if (netif == &self->netif) { + netif_remove(netif); + netif->ip_addr.addr = 0; + netif->flags = 0; + } + } + MICROPY_PY_LWIP_EXIT +} + +void ETH_IRQHandler(ether_callback_args_t *p_args) { + + switch (p_args->event) + { + case ETHER_EVENT_WAKEON_LAN: + break; + case ETHER_EVENT_LINK_ON: + phy_link_status = 1; + break; + case ETHER_EVENT_LINK_OFF: + phy_link_status = 0; + break; + + case ETHER_EVENT_INTERRUPT: { + if (ETHER_EXAMPLE_ETHER_ISR_EE_FR_MASK == (p_args->status_eesr & ETHER_EXAMPLE_ETHER_ISR_EE_FR_MASK)) { + uint32_t len = 0; + + if (FSP_SUCCESS == R_ETHER_Read(&g_ether0_ctrl, rx_TMPbuf, &len)) { + eth_process_frame(ð_instance, len, rx_TMPbuf); + } + } + + if (ETHER_EXAMPLE_ETHER_ISR_EE_TC_MASK == (p_args->status_eesr & ETHER_EXAMPLE_ETHER_ISR_EE_TC_MASK)) { + } + + if (ETHER_EXAMPLE_ETHER_ISR_EC_MPD_MASK == (p_args->status_ecsr & ETHER_EXAMPLE_ETHER_ISR_EC_MPD_MASK)) { + } + } + break; + + default: { + } + } +} + +// ------------------------------------------------------------------------------ + +void eth_init(eth_t *self, int mac_idx) { + fsp_err_t err; + + mp_hal_pin_output(phy_RST); + + mp_hal_pin_low(phy_RST); + mp_hal_delay_us(200); + mp_hal_pin_high(phy_RST); + mp_hal_delay_us(200); + + if ((err = R_ETHER_Open(&g_ether0_ctrl, &g_ether0_cfg)) == FSP_SUCCESS) { + self->netif.hwaddr_len = 6; // self->netif. + // mp_hal_get_mac(mac_idx, &self->netif.hwaddr[0]); + memcpy(self->netif.hwaddr, g_ether0_cfg.p_mac_address, self->netif.hwaddr_len); + } +} + +void eth_set_trace(eth_t *self, uint32_t value) { + self->trace_flags = value; +} + +struct netif *eth_netif(eth_t *self) { + return &self->netif; +} + +int eth_link_status(eth_t *self) { + + struct netif *netif = &self->netif; + if ((netif->flags & (NETIF_FLAG_UP | NETIF_FLAG_LINK_UP)) + == (NETIF_FLAG_UP | NETIF_FLAG_LINK_UP)) { + if (netif->ip_addr.addr != 0) { + return 3; // link up + } else { + return 2; // link no-ip; + } + } else { + return phy_link_status; // 1: link up | 0: link down + } +} + +int eth_start(eth_t *self) { + fsp_err_t err; + + eth_lwip_deinit(self); + + do + { + /* When the Ethernet link status read from the PHY-LSI Basic Status register is link-up, + * Initializes the module and make auto negotiation. */ + err = R_ETHER_LinkProcess(&g_ether0_ctrl); + } while (FSP_SUCCESS != err); + + // while(!phy_link_status); + + eth_lwip_init(self); + + return 0; +} + +int eth_stop(eth_t *self) { + eth_lwip_deinit(self); + return 0; +} + +void eth_low_power_mode(eth_t *self, bool enable) { + (void)self; + printf("eth_low_power_mode() not implemented \r\n"); +} + +#endif // defined(MICROPY_HW_ETH_MDC) diff --git a/ports/renesas-ra/eth.h b/ports/renesas-ra/eth.h new file mode 100644 index 0000000000000..df2c6090e6eb9 --- /dev/null +++ b/ports/renesas-ra/eth.h @@ -0,0 +1,42 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Damien P. George + * Copyright (c) 2023 Vekatech Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RA_ETH_H +#define MICROPY_INCLUDED_RA_ETH_H + +typedef struct _eth_t eth_t; +extern eth_t eth_instance; +extern uint8_t g_ether0_mac_address[6]; + +void eth_init(eth_t *self, int mac_idx); +void eth_set_trace(eth_t *self, uint32_t value); +struct netif *eth_netif(eth_t *self); +int eth_link_status(eth_t *self); +int eth_start(eth_t *self); +int eth_stop(eth_t *self); +void eth_low_power_mode(eth_t *self, bool enable); + +#endif // MICROPY_INCLUDED_RA_ETH_H diff --git a/ports/renesas-ra/fsp_cfg/r_ether_cfg.h b/ports/renesas-ra/fsp_cfg/r_ether_cfg.h new file mode 100644 index 0000000000000..d253894e1cba0 --- /dev/null +++ b/ports/renesas-ra/fsp_cfg/r_ether_cfg.h @@ -0,0 +1,15 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ETHER_CFG_H_ +#define R_ETHER_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ETHER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define ETHER_CFG_LINK_PRESENT (0) +#define ETHER_CFG_USE_LINKSTA (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_ETHER_CFG_H_ */ diff --git a/ports/renesas-ra/fsp_cfg/r_ether_phy_cfg.h b/ports/renesas-ra/fsp_cfg/r_ether_phy_cfg.h new file mode 100644 index 0000000000000..01e02c6884ff8 --- /dev/null +++ b/ports/renesas-ra/fsp_cfg/r_ether_phy_cfg.h @@ -0,0 +1,26 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ETHER_PHY_CFG_H_ +#define R_ETHER_PHY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ETHER_PHY_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#ifndef ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE +#define ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE +#define ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_DP83620_ENABLE +#define ETHER_PHY_CFG_TARGET_DP83620_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_ICS1894_ENABLE +#define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (1) +#endif +#define ETHER_PHY_CFG_USE_REF_CLK (BOARD_PHY_REF_CLK) + +#ifdef __cplusplus +} +#endif +#endif /* R_ETHER_PHY_CFG_H_ */ diff --git a/ports/renesas-ra/fsp_cfg/r_glcdc_cfg.h b/ports/renesas-ra/fsp_cfg/r_glcdc_cfg.h new file mode 100644 index 0000000000000..0c732efe679ae --- /dev/null +++ b/ports/renesas-ra/fsp_cfg/r_glcdc_cfg.h @@ -0,0 +1,13 @@ +#ifndef R_GLCDC_CFG_H_ +#define R_GLCDC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define GLCDC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define GLCDC_CFG_COLOR_CORRECTION_ENABLE (false) + +#ifdef __cplusplus +} +#endif +#endif /* R_GLCDC_CFG_H_ */ diff --git a/ports/renesas-ra/fsp_cfg/r_jpeg_cfg.h b/ports/renesas-ra/fsp_cfg/r_jpeg_cfg.h new file mode 100644 index 0000000000000..e486eaf9b103f --- /dev/null +++ b/ports/renesas-ra/fsp_cfg/r_jpeg_cfg.h @@ -0,0 +1,14 @@ +#ifndef R_JPEG_CFG_H_ +#define R_JPEG_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define JPEG_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define JPEG_CFG_DECODE_ENABLE (0) +#define JPEG_CFG_ENCODE_ENABLE (1) + +#ifdef __cplusplus +} +#endif +#endif /* R_JPEG_CFG_H_ */ diff --git a/ports/renesas-ra/fsp_cfg/r_pdc_cfg.h b/ports/renesas-ra/fsp_cfg/r_pdc_cfg.h new file mode 100644 index 0000000000000..c8ecc4d5d555e --- /dev/null +++ b/ports/renesas-ra/fsp_cfg/r_pdc_cfg.h @@ -0,0 +1,12 @@ +#ifndef R_PDC_CFG_H_ +#define R_PDC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define PDC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_PDC_CFG_H_ */ diff --git a/ports/renesas-ra/fsp_cfg/r_sci_i2c_cfg.h b/ports/renesas-ra/fsp_cfg/r_sci_i2c_cfg.h new file mode 100644 index 0000000000000..f2f398ebbacca --- /dev/null +++ b/ports/renesas-ra/fsp_cfg/r_sci_i2c_cfg.h @@ -0,0 +1,15 @@ +#ifndef R_SCI_I2C_CFG_H_ +#define R_SCI_I2C_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SCI_SIIC_CFG_PREREQUISITE_CHECKING_ENABLE 1 +#define SCI_I2C_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCI_I2C_CFG_DTC_ENABLE (1) +#define SCI_I2C_CFG_ADDR_MODE_10_BIT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_SCI_I2C_CFG_H_ */ diff --git a/ports/renesas-ra/lwip_inc/arch/cc.h b/ports/renesas-ra/lwip_inc/arch/cc.h index c31e54e9d69b7..6510a48e57cb0 100644 --- a/ports/renesas-ra/lwip_inc/arch/cc.h +++ b/ports/renesas-ra/lwip_inc/arch/cc.h @@ -1,5 +1,5 @@ -#ifndef MICROPY_INCLUDED_RP2_LWIP_ARCH_CC_H -#define MICROPY_INCLUDED_RP2_LWIP_ARCH_CC_H +#ifndef MICROPY_INCLUDED_RA_LWIP_ARCH_CC_H +#define MICROPY_INCLUDED_RA_LWIP_ARCH_CC_H #include #define LWIP_PLATFORM_DIAG(x) @@ -7,4 +7,4 @@ #define LWIP_NO_CTYPE_H 1 -#endif // MICROPY_INCLUDED_RP2_LWIP_ARCH_CC_H +#endif // MICROPY_INCLUDED_RA_LWIP_ARCH_CC_H diff --git a/ports/renesas-ra/machine_cam.c b/ports/renesas-ra/machine_cam.c new file mode 100644 index 0000000000000..805876fce9cb9 --- /dev/null +++ b/ports/renesas-ra/machine_cam.c @@ -0,0 +1,1020 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2023 Vekatech Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/mpconfig.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "py/stream.h" +#include "extmod/machine_i2c.h" +#include "extmod/vfs.h" +#include "modmachine.h" +#include "hal_data.h" + + + +#if MODULE_CAM_ENABLED + +// White Balance +#define WB_NONE 0 +#define WB_SUNNY 1 +#define WB_CLOUDY 2 +#define WB_OFFICE 3 +#define WB_HOME 4 + +// Special Effect +#define EFFECT_NONE 0 +#define EFFECT_NEG 1 +#define EFFECT_BW 2 +#define EFFECT_RED 3 +#define EFFECT_GREEN 4 +#define EFFECT_BLUE 5 +#define EFFECT_RETRO 6 + +#define CAM OV7725 + +#define COM3_V_FLIP (1 << 7) +#define COM3_H_MIRROR (1 << 6) + +#define COM7_RESET (1 << 7) +#define COM7_QVGA (1 << 6) +#define COM7_RGB565 (3 << 1) +#define ETBL 0xFFu + +#define __3(a, b, c) a##b##c +#define _3(a, b, c) __3(a, b, c) + +#define CCD(item) _3(CAM, _, item) + +enum CCD (REGs) +{ + CCD(GAIN) = 0x00, + CCD(BLUE), // 0x01 + CCD(RED), // 0x02 + CCD(GREEN), // 0x03 + CCD(BAVG) = 0x05, + CCD(GAVG), // 0x06 + CCD(RAVG), // 0x07 + CCD(AECH), // 0x08 + CCD(COM2), // 0x09 + CCD(PID), // 0x0A + CCD(VER), // 0x0B + CCD(COM3), // 0x0C + CCD(COM4), // 0x0D + CCD(COM5), // 0x0E + CCD(COM6), // 0x0F + CCD(AEC), // 0x10 + CCD(CLKRC), // 0x11 + CCD(COM7), // 0x12 + CCD(COM8), // 0x13 + CCD(COM9), // 0x14 + CCD(COM10), // 0x15 + CCD(REG16), // 0x16 + CCD(HSTART), // 0x17 + CCD(HSIZE), // 0x18 + CCD(VSTRT), // 0x19 + CCD(VSIZE), // 0x1A + CCD(PSHFT), // 0x1B + CCD(MIDH), // 0x1C + CCD(MIDL), // 0x1D + CCD(LAEC) = 0x1F, + CCD(COM11), // 0x20 + CCD(BDBase) = 0x22, + CCD(BDMStep), // 0x23 + CCD(AEW), // 0x24 + CCD(AEB), // 0x25 + CCD(VPT), // 0x26 + CCD(REG28) = 0x28, + CCD(HOutSize), // 0x29 + CCD(EXHCH), // 0x2A + CCD(EXHCL), // 0x2B + CCD(VOutSize), // 0x2C + CCD(ADVFL), // 0x2D + CCD(ADVFH), // 0x2E + CCD(YAVE), // 0x2F + CCD(LumHTh), // 0x30 + CCD(LumLTh), // 0x31 + CCD(HREF), // 0x32 + CCD(DM_LNL), // 0x33 + CCD(DM_LNH), // 0x34 Dummy Row High 8 Bits + CCD(ADoff_B), // 0x35 AD Offset Compensation Value for B Channel + CCD(ADoff_R), // 0x36 AD Offset Compensation Value for R Channel + CCD(ADoff_Gb), // 0x37 AD Offset Compensation Value for Gb Channel + CCD(ADoff_Gr), // 0x38 AD Offset Compensation Value for Gr Channel + CCD(Off_B), // 0x39 Analog Process B Channel Offset Compensation Value + CCD(Off_R), // 0x3A Analog Process R Channel Offset Compensation Value + CCD(Off_Gb), // 0x3B Analog Process Gb Channel Offset Compensation Value + CCD(Off_Gr), // 0x3C Analog Process Gr Channel Offset Compensation Valu + CCD(COM12), // 0x3D + CCD(TGT_B) = 0x42, + CCD(FixGain) = 0x4D, + CCD(UFix) = 0x60, // U Channel Fixed Value Output + CCD(VFix), // 0x61 //V Channel Fixed Value Outpu + CCD(AWBb_blk), // 0x62 //AWB Option for Advanced AWB + CCD(AWB_Ctrl0), // 0x63 + CCD(DSP_Ctrl1), // 0x64 + CCD(DSP_Ctrl2), // 0x65 + CCD(DSP_Ctrl3), // 0x66 + CCD(DSP_Ctrl4), // 0x67 + CCD(AWBCtrl3) = 0x6B, + CCD(GAM1) = 0x7E, + CCD(GAM2), // 0x7F + CCD(GAM3), // 0x80 + CCD(GAM4), // 0x81 + CCD(GAM5), // 0x82 + CCD(GAM6), // 0x83 + CCD(GAM7), // 0x84 + CCD(GAM8), // 0x85 + CCD(GAM9), // 0x86 + CCD(GAM10), // 0x87 + CCD(GAM11), // 0x88 + CCD(GAM12), // 0x89 + CCD(GAM13), // 0x8A + CCD(GAM14), // 0x8B + CCD(GAM15), // 0x8C + CCD(SLOP), // 0x8D + CCD(EDGE1) = 0x90, + CCD(DNSOff), // 0x91 + CCD(EDGE2), // 0x92 + CCD(EDGE3), // 0x93 + CCD(MTX1), // 0x94 + CCD(MTX2), // 0x95 + CCD(MTX3), // 0x96 + CCD(MTX4), // 0x97 + CCD(MTX5), // 0x98 + CCD(MTX6), // 0x99 + CCD(MTX_Ctrl), // 0x9A + CCD(BRIGHT), // 0x9B + CCD(CNST), // 0x9C + CCD(UVADJ0) = 0x9E, + CCD(SDE) = 0xA6, + CCD(USAT) = 0xA7, + CCD(VSAT) = 0xA8, + CCD(SIGN) = 0xAB +}; + +// Video buffer components +typedef union +{ + struct + { + uint16_t B : 5; + uint16_t G : 6; + uint16_t R : 5; + } CLR; + uint8_t dat[2]; + uint16_t data; +} RGB_pixel_t; + +typedef union +{ + struct + { + uint8_t Y0; // Y + uint8_t U; // Cb + uint8_t Y1; // Y + uint8_t V; // Cr + } CMP; + uint8_t dat[4]; + uint16_t luma[2]; + uint32_t chroma; + uint32_t data; +} YUY2_macropixel_t; + +#define VIDEO_FRAME(name, w, h, p) \ + union \ + { \ + uint8_t frameBUF[w * h * p]; \ + RGB_pixel_t RGB[w * h]; \ + RGB_pixel_t RGB_2D[h][w]; \ + YUY2_macropixel_t YUY2[(w * h) / 2]; \ + YUY2_macropixel_t YUY2_2D[h][w / 2]; \ + uint16_t lumaPLANE[w * h]; \ + uint16_t lumaPLANE_2D[h][w]; \ + uint32_t chromaPLANE[(w * h) / 2]; \ + uint32_t chromaPLANE_2D[h][w / 2]; \ + } name + +typedef VIDEO_FRAME(VideoBuffer_t, 320, 240, 2); +typedef VIDEO_FRAME(DisplayBuffer_t, 480, 272, 2); + +const uint8_t CCD(InitRegTable)[][2] = { + {CCD(COM2), 0x02}, + {CCD(COM4), 0x41}, + {CCD(COM6), 0xC5}, + #if 1 /* 30fps(24MHz) */ + {CCD(CLKRC), 0x04}, + #else /* 60fps(48MHz) */ + {CCD(CLKRC), 0x00}, + #endif + {CCD(COM7), COM7_QVGA}, + {CCD(COM9), 0x1F}, + {CCD(COM10), 0x40}, + + // {CCD(HSTART) , 0x23}, //0x22 23 VGA + // {CCD(HSIZE) , 0xA0}, //0xA4 A0 VGA + // {CCD(VSTRT) , 0x07}, // VGA + // {CCD(VSIZE) , 0xF0}, // VGA + + {CCD(HSTART), 0x3F}, // 3E 3F QVGA + {CCD(HSIZE), 0x54}, // 54 50 QVGA + {CCD(VSTRT), 0x03}, // QVGA + {CCD(VSIZE), 0x78}, // QVGA + + {CCD(BDBase), 0x99}, + {CCD(BDMStep), 0x02}, + {CCD(AEW), 0x60}, + {CCD(AEB), 0x50}, + {CCD(VPT), 0xA1}, + + // {CCD(HOutSize) , 0xA0}, // VGA + {CCD(HOutSize), 0x50}, // QVGA + + {CCD(EXHCH), 0x00}, + {CCD(EXHCL), 0x00}, + + // {CCD(VOutSize) , 0xF0}, // VGA + {CCD(VOutSize), 0x78}, // 0x3C QVGA + + {CCD(HREF), 0x00}, + {CCD(DM_LNL), 0x01}, + + // {ADoff_Gb , 0x00}, + // {ADoff_Gr , 0x00}, + // {Off_Gb , 0x00}, + // {Off_Gr , 0x00}, + + {CCD(COM12), 0x03}, + {CCD(TGT_B), 0x7F}, + {CCD(FixGain), 0x09}, + + // {UFix , 0x00}, //U Channel Fixed Value Output + // {VFix , 0x00}, //0x61 //V Channel Fixed Value Outpu + + {CCD(AWB_Ctrl0), 0xE0}, + {CCD(DSP_Ctrl1), 0xFF}, + {CCD(DSP_Ctrl2), 0x20}, + {CCD(DSP_Ctrl3), 0x00}, + {CCD(DSP_Ctrl4), 0x48}, + {CCD(AWBCtrl3), 0xAA}, + {CCD(GAM1), 0x04}, + {CCD(GAM2), 0x0E}, + {CCD(GAM3), 0x20}, + {CCD(GAM4), 0x43}, + {CCD(GAM5), 0x53}, + {CCD(GAM6), 0x61}, + {CCD(GAM7), 0x6D}, + {CCD(GAM8), 0x76}, + {CCD(GAM9), 0x7E}, + {CCD(GAM10), 0x86}, + {CCD(GAM11), 0x94}, + {CCD(GAM12), 0xA1}, + {CCD(GAM13), 0xBA}, + {CCD(GAM14), 0xCF}, + {CCD(GAM15), 0xE3}, + {CCD(SLOP), 0x26}, + {CCD(EDGE1), 0x05}, + {CCD(DNSOff), 0x01}, + {CCD(EDGE2), 0x05}, + {CCD(EDGE3), 0x00}, + {CCD(MTX1), 0x80}, + {CCD(MTX2), 0x7B}, + {CCD(MTX3), 0x06}, + {CCD(MTX4), 0x1E}, + {CCD(MTX5), 0x69}, + {CCD(MTX6), 0x86}, + {CCD(MTX_Ctrl), 0x1E}, + {CCD(BRIGHT), 0x00}, + {CCD(CNST), 0x20}, + {CCD(UVADJ0), 0x81}, + {CCD(SDE), 0x04}, + // {SIGN , 0x07}, + {ETBL, ETBL} +}; + +typedef struct _machine_cam_obj_t { + mp_obj_base_t base; + mp_buffer_info_t fb; + mp_obj_base_t *i2c; // machine_i2c_obj_t* i2c; + uint32_t jpeg_size; + uint8_t isinited; + uint8_t isshowing; + mp_hal_pin_obj_t pwr; // backlight ctr (ON OFF) + mp_hal_pin_obj_t rst; // enable ctr (ON OFF) +} machine_cam_obj_t; + +volatile uint8_t CAM_rdy = 0; +static volatile uint8_t CAM_capture = 0; +static volatile uint8_t JPEG_complete = 0; + +uint8_t g_JPEG[64 * 1024] BSP_ALIGN_VARIABLE(8) BSP_PLACE_IN_SECTION(".noinit"); + +STATIC machine_cam_obj_t machine_cam_obj = {{&machine_cam_type}, {NULL, 0, 0}, MP_OBJ_NULL, 0, 0, 0, pin_P611, pin_P612}; + +void SWP(void) { + VideoBuffer_t *Vid = (VideoBuffer_t *)g_cam_buffer[0]; + + for (int i = 0, UV = (g_cam0_cfg.x_capture_pixels * g_cam0_cfg.y_capture_pixels) / 2; i < UV; i++) + { + Vid->YUY2[i].CMP.U -= 128; + Vid->YUY2[i].CMP.V -= 128; + } +} + +void SnapShot() { + VideoBuffer_t *Vid = (VideoBuffer_t *)g_cam_buffer[0]; + DisplayBuffer_t *Dis = (DisplayBuffer_t *)machine_cam_obj.fb.buf; + + for (int y = 0; y < g_cam0_cfg.y_capture_pixels; y++) { + for (int x = 0; x < g_cam0_cfg.x_capture_pixels; x++) + { + // Dis->RGB_2D[y][x] = Vid->RGB_2D[y][x]; + Dis->RGB_2D[y][x].dat[0] = (Vid->RGB_2D[y][x].dat[0] >> 3); + Dis->RGB_2D[y][x].dat[1] = (Vid->RGB_2D[y][x].dat[1] << 3); + Dis->RGB_2D[y][x].dat[0] |= (Vid->RGB_2D[y][x].dat[1] & 0xE0); + Dis->RGB_2D[y][x].dat[1] |= (Vid->RGB_2D[y][x].dat[0] & 0x07); + } + } +} + +void next_img() { + CAM_rdy = 0; + if (machine_cam_obj.isshowing) { + R_PDC_CaptureStart(&g_cam0_ctrl, g_cam_buffer[0]); + } +} + +void cam_ISR(pdc_callback_args_t *p_args) { + if (p_args->event == PDC_EVENT_TRANSFER_COMPLETE) { + if (machine_cam_obj.isshowing) { + CAM_rdy = 1; + } else { + CAM_capture = 1; + } + } +} + +void jpg_ISR(jpeg_callback_args_t *p_args) { + if (NULL != p_args) { + if (p_args->status == (JPEG_STATUS_IDLE | JPEG_STATUS_OPERATION_COMPLETE)) { + machine_cam_obj.jpeg_size = p_args->image_size; + JPEG_complete = 1; + } + } +} + +STATIC mp_obj_t machine_cam_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + machine_cam_obj_t *self = &machine_cam_obj; + + enum { ARG_i2c }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_i2c, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} } + }; + + mp_arg_check_num(n_args, n_kw, 1, 1, false); + mp_arg_val_t init_args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, args, MP_ARRAY_SIZE(allowed_args), allowed_args, init_args); + + self->i2c = MP_OBJ_TO_PTR(init_args[ARG_i2c].u_obj); + return MP_OBJ_FROM_PTR(self); +} + +STATIC mp_obj_t cam_init(mp_obj_t self_in) { + machine_cam_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t *)MP_OBJ_TYPE_GET_SLOT(self->i2c->type, protocol); + + if (!self->isinited) { + if (FSP_SUCCESS == R_PDC_Open(&g_cam0_ctrl, &g_cam0_cfg)) { + // int e; + uint8_t regs[2] = {CCD(COM7), COM7_RESET}; + mp_machine_i2c_buf_t buff = {sizeof(regs), regs}; + + self->isinited = 1; + ra_gpio_config(self->pwr->pin, GPIO_MODE_OUTPUT_PP, GPIO_NOPULL, GPIO_LOW_POWER, 0); + ra_gpio_config(self->rst->pin, GPIO_MODE_OUTPUT_PP, GPIO_NOPULL, GPIO_LOW_POWER, 0); + /* De-assert Camera Power Down */ + ra_gpio_write(self->pwr->pin, 0); + ra_gpio_write(self->rst->pin, 0); + + mp_hal_delay_ms(2); + ra_gpio_write(self->rst->pin, 1); + + mp_hal_delay_ms(2); + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + mp_hal_delay_ms(2); + + buff.buf = (uint8_t *)CCD(InitRegTable)[0]; + + do + { + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + break; + } + buff.buf += buff.len; + } while (buff.buf[0] != ETBL); + + mp_hal_delay_ms(2); + + if (FSP_SUCCESS == R_JPEG_Open(&g_jpeg0_ctrl, &g_jpeg0_cfg)) { + R_JPEG_OutputBufferSet(&g_jpeg0_ctrl, g_JPEG, sizeof(g_JPEG)); + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Can't init R_JPEG")); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Can't init R_PDC")); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Olready inited!")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_cam_init_obj, cam_init); + +STATIC mp_obj_t cam_deinit(mp_obj_t self_in) { + machine_cam_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (self->isinited) { + if (FSP_SUCCESS == R_PDC_Close(&g_cam0_ctrl)) { + self->isinited = 0; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Can't close R_PDC")); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not inited! call CAM.init() first")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_cam_deinit_obj, cam_deinit); + +STATIC mp_obj_t cam_YUYV(mp_obj_t self_in, mp_obj_t file_name) { + machine_cam_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (self->isinited) { + if (!self->isshowing) { + CAM_capture = 0; + if (FSP_SUCCESS == R_PDC_CaptureStart(&g_cam0_ctrl, g_cam_buffer[0])) { + // save in flash + mp_obj_t file = MP_OBJ_NULL; + mp_obj_t args[2] = {MP_OBJ_NEW_QSTR(MP_QSTR__slash_flash), MP_OBJ_NULL}; + mp_obj_list_t *list = mp_vfs_listdir(1, args); + mp_uint_t len = 0; + + mp_obj_list_append(list, file_name); + args[0] = file_name; + args[1] = MP_OBJ_NEW_QSTR(MP_QSTR_wb); + file = mp_vfs_open(MP_ARRAY_SIZE(args), &args[0], (mp_map_t *)&mp_const_empty_map); + + if (file == MP_OBJ_NULL) { + mp_raise_ValueError(MP_ERROR_TEXT("Can't create file")); + } else { + int errcode; + + while (!CAM_capture) { + ; + } + + len = mp_stream_rw(file, g_cam_buffer[0], sizeof(g_cam_buffer[0]), &errcode, MP_STREAM_RW_WRITE | MP_STREAM_RW_ONCE); + if (errcode != 0) { + mp_raise_OSError(errcode); + } + + if (len != sizeof(g_cam_buffer[0])) { + mp_raise_ValueError(MP_ERROR_TEXT("Can't write YUY2 file")); + } + + mp_stream_close(file); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Can't Start Capture R_PDC")); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not in YUV2 mode. Stop showing first!")); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not inited! call CAM.init() first")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_cam_yuyv_obj, cam_YUYV); + +STATIC mp_obj_t cam_JPEG(mp_obj_t self_in, mp_obj_t file_name) { + machine_cam_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (self->isinited) { + if (!self->isshowing) { + CAM_capture = 0; + if (FSP_SUCCESS == R_PDC_CaptureStart(&g_cam0_ctrl, g_cam_buffer[0])) { + // save in flash + mp_obj_t file = MP_OBJ_NULL; + mp_obj_t args[2] = {MP_OBJ_NEW_QSTR(MP_QSTR__slash_flash), MP_OBJ_NULL}; + mp_obj_list_t *list = mp_vfs_listdir(1, args); + mp_uint_t len = 0; + + mp_obj_list_append(list, file_name); + args[0] = file_name; + args[1] = MP_OBJ_NEW_QSTR(MP_QSTR_wb); + file = mp_vfs_open(MP_ARRAY_SIZE(args), &args[0], (mp_map_t *)&mp_const_empty_map); + + if (file == MP_OBJ_NULL) { + mp_raise_ValueError(MP_ERROR_TEXT("Can't create file")); + } else { + int errcode; + + while (!CAM_capture) { + ; + } + SWP(); + JPEG_complete = 0; + R_JPEG_InputBufferSet(&g_jpeg0_ctrl, g_cam_buffer[0], sizeof(g_cam_buffer[0]) * 2); + while (!JPEG_complete) { + ; + } + + len = mp_stream_rw(file, g_JPEG, self->jpeg_size, &errcode, MP_STREAM_RW_WRITE | MP_STREAM_RW_ONCE); + if (errcode != 0) { + mp_raise_OSError(errcode); + } + + if (len != self->jpeg_size) { + mp_raise_ValueError(MP_ERROR_TEXT("Can't write JPEG file")); + } + + mp_stream_close(file); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Can't Start Capture R_PDC")); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not in YUV2 mode. Stop showing first!")); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not inited! call CAM.init() first")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_cam_jpeg_obj, cam_JPEG); + +STATIC mp_obj_t cam_show_start(mp_obj_t self_in, mp_obj_t lcd) { + machine_cam_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (self->isinited) { + uint8_t regs[2] = {CCD(COM7), 0}; + mp_machine_i2c_buf_t buff = {sizeof(regs), regs}; + mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t *)MP_OBJ_TYPE_GET_SLOT(self->i2c->type, protocol); + + buff.len--; + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + buff.buf += buff.len; + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_READ | MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + buff.buf -= buff.len; + buff.len++; + + regs[1] &= 0xF0; + regs[1] |= COM7_RGB565; + + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + mp_hal_delay_ms(2); + + CAM_capture = 0; + mp_get_buffer_raise(lcd, &self->fb, MP_BUFFER_WRITE); + self->isshowing = 1; + CAM_rdy = 1; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not inited! call CAM.init() first")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_cam_show_start_obj, cam_show_start); + +STATIC mp_obj_t cam_show_stop(mp_obj_t self_in) { + machine_cam_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (self->isinited) { + uint8_t regs[2] = {CCD(COM7), 0}; + mp_machine_i2c_buf_t buff = {sizeof(regs), regs}; + mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t *)MP_OBJ_TYPE_GET_SLOT(self->i2c->type, protocol); + + buff.len--; + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + buff.buf += buff.len; + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_READ | MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + buff.buf -= buff.len; + buff.len++; + + regs[1] &= 0xF0; + + self->isshowing = 0; + self->fb.buf = NULL; + self->fb.len = 0; + self->fb.typecode = 0; + + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not inited! call CAM.init() first")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_cam_show_stop_obj, cam_show_stop); + +STATIC mp_obj_t camera_flip(mp_obj_t self_in, mp_obj_t onoff) { + machine_cam_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (self->isinited) { + int flg = mp_obj_get_int(onoff); + uint8_t regs[2] = {CCD(COM3), 0x10}; + mp_machine_i2c_buf_t buff = {sizeof(regs), regs}; + mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t *)MP_OBJ_TYPE_GET_SLOT(self->i2c->type, protocol); + + buff.len--; + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + buff.buf += buff.len; + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_READ | MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + buff.buf -= buff.len; + buff.len++; + regs[1] = flg? (regs[1] | COM3_V_FLIP) : (regs[1] & ~COM3_V_FLIP); + + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + mp_hal_delay_ms(2); + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not inited! call CAM.init() first")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_cam_flip_obj, camera_flip); + +STATIC mp_obj_t camera_mirror(mp_obj_t self_in, mp_obj_t onoff) { + machine_cam_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (self->isinited) { + int flg = mp_obj_get_int(onoff); + uint8_t regs[2] = {CCD(COM3), 0x10}; + mp_machine_i2c_buf_t buff = {sizeof(regs), regs}; + mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t *)MP_OBJ_TYPE_GET_SLOT(self->i2c->type, protocol); + + buff.len--; + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + buff.buf += buff.len; + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_READ | MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + buff.buf -= buff.len; + buff.len++; + regs[1] = flg? (regs[1] | COM3_H_MIRROR) : (regs[1] & ~COM3_H_MIRROR); + + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + mp_hal_delay_ms(2); + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not inited! call CAM.init() first")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_cam_mirror_obj, camera_mirror); + +STATIC mp_obj_t camera_contrast(mp_obj_t self_in, mp_obj_t cnst) { + machine_cam_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (self->isinited) { + int res = 0; + int val = mp_obj_get_int(cnst); + uint8_t regs[2] = {CCD(CNST), 0x20}; + mp_machine_i2c_buf_t buff = {sizeof(regs), regs}; + mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t *)MP_OBJ_TYPE_GET_SLOT(self->i2c->type, protocol); + + if ((val > 4) || (val < -4)) { + mp_raise_ValueError(MP_ERROR_TEXT("Contrast should be in range [-4 to 4]")); + } else { + res = regs[1]; + res += 0x04 * val; + regs[1] = res; + + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + } + mp_hal_delay_ms(2); + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not inited! call CAM.init() first")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_cam_contrast_obj, camera_contrast); + +STATIC mp_obj_t camera_saturation(mp_obj_t self_in, mp_obj_t sat) { + machine_cam_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (self->isinited) { + int res = 0; + int val = mp_obj_get_int(sat); + uint8_t regs[2] = {CCD(USAT), 0x40}; + mp_machine_i2c_buf_t buff = {sizeof(regs), regs}; + mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t *)MP_OBJ_TYPE_GET_SLOT(self->i2c->type, protocol); + + if ((val > 4) || (val < -4)) { + mp_raise_ValueError(MP_ERROR_TEXT("Saturation should be in range [-4 to 4]")); + } else { + res = regs[1]; + res += 0x04 * val; + regs[1] = res; + + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + + regs[0] = CCD(VSAT); + + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + } + mp_hal_delay_ms(2); + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not inited! call CAM.init() first")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_cam_saturation_obj, camera_saturation); + +STATIC mp_obj_t camera_brightness(mp_obj_t self_in, mp_obj_t bright) { + machine_cam_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (self->isinited) { + int val = mp_obj_get_int(bright); + uint8_t regs[2] = {CCD(SIGN), 0}; + mp_machine_i2c_buf_t buff = {sizeof(regs), regs}; + mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t *)MP_OBJ_TYPE_GET_SLOT(self->i2c->type, protocol); + + buff.len--; + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + buff.buf += buff.len; + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_READ | MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + buff.buf -= buff.len; + buff.len++; + + if ((val > 4) || (val < -4)) { + mp_raise_ValueError(MP_ERROR_TEXT("Saturation should be in range [-4 to 4]")); + } else { + if (val < 0) { + regs[1] |= 0x08; + } else { + regs[1] &= 0xF7; + } + + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + + regs[0] = CCD(BRIGHT); + regs[1] = 0x10 * abs(val); + + if (val < 0) { + regs[1] -= 0x10; + } + + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + } + } + mp_hal_delay_ms(2); + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not inited! call CAM.init() first")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_cam_brightness_obj, camera_brightness); + +STATIC mp_obj_t camera_speffect(mp_obj_t self_in, mp_obj_t what) { + machine_cam_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (self->isinited) { + int val = mp_obj_get_int(what); + uint8_t regs[3][2] = {{CCD(SDE), 0}, {CCD(UFix), 0x80}, {CCD(VFix), 0x80}}; + mp_machine_i2c_buf_t buff = {sizeof(regs[0]), regs[0]}; + mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t *)MP_OBJ_TYPE_GET_SLOT(self->i2c->type, protocol); + + switch (val) + { + case EFFECT_NONE: + regs[0][1] = 0x06; + regs[1][1] = 0x80; + regs[2][1] = 0x80; + break; + + case EFFECT_NEG: + regs[0][1] = 0x46; + regs[1][1] = 0x80; + regs[2][1] = 0x80; + break; + + case EFFECT_BW: + regs[0][1] = 0x26; + regs[1][1] = 0x80; + regs[2][1] = 0x80; + break; + + case EFFECT_RED: + regs[0][1] = 0x1E; + regs[1][1] = 0x80; + regs[2][1] = 0xC0; + break; + + case EFFECT_GREEN: + regs[0][1] = 0x1E; + regs[1][1] = 0x60; + regs[2][1] = 0x60; + break; + + case EFFECT_BLUE: + regs[0][1] = 0x1E; + regs[1][1] = 0xA0; + regs[2][1] = 0x40; + break; + + case EFFECT_RETRO: + regs[0][1] = 0x1E; + regs[1][1] = 0x40; + regs[2][1] = 0xA0; + break; + + default: + mp_raise_ValueError(MP_ERROR_TEXT("Wrong argument!")); + break; + } + + val = MP_ARRAY_SIZE(regs); + do + { + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + break; + } + buff.buf += buff.len; + } while (--val); + mp_hal_delay_ms(2); + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not inited! call CAM.init() first")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_cam_speffect_obj, camera_speffect); + +STATIC mp_obj_t camera_whitebalance(mp_obj_t self_in, mp_obj_t white) { + machine_cam_obj_t *self = MP_OBJ_TO_PTR(self_in); + + if (self->isinited) { + int val = mp_obj_get_int(white); + uint8_t regs[6][2] = {{CCD(COM8), 0}, {CCD(BLUE), 0x80}, {CCD(RED), 0x80}, {CCD(COM5), 0x65}, {CCD(ADVFL), 0}, {CCD(ADVFH), 0}}; + mp_machine_i2c_buf_t buff = {sizeof(regs[0]), regs[0]}; + mp_machine_i2c_p_t *i2c_p = (mp_machine_i2c_p_t *)MP_OBJ_TYPE_GET_SLOT(self->i2c->type, protocol); + + switch (val) + { + case WB_NONE: + regs[0][1] = 0xff; + regs[1][1] = 0x80; + regs[2][1] = 0x80; + break; + + case WB_SUNNY: + regs[0][1] = 0xfd; + regs[1][1] = 0x5a; + regs[2][1] = 0x5c; + break; + + case WB_CLOUDY: + regs[0][1] = 0xfd; + regs[1][1] = 0x58; + regs[2][1] = 0x60; + break; + + case WB_OFFICE: + regs[0][1] = 0xfd; + regs[1][1] = 0x84; + regs[2][1] = 0x4c; + break; + + case WB_HOME: + regs[0][1] = 0xfd; + regs[1][1] = 0x96; + regs[2][1] = 0x40; + break; + + default: + mp_raise_ValueError(MP_ERROR_TEXT("Wrong argument!")); + break; + } + + val = MP_ARRAY_SIZE(regs); + do + { + if (0 > i2c_p->transfer(self->i2c, 0x21, 1, &buff, MP_MACHINE_I2C_FLAG_STOP)) { + mp_raise_ValueError(MP_ERROR_TEXT("I2C transfer error")); + break; + } + buff.buf += buff.len; + } while (--val); + mp_hal_delay_ms(2); + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not inited! call CAM.init() first")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_cam_whitebalance_obj, camera_whitebalance); + + +STATIC const mp_rom_map_elem_t cam_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_cam_init_obj) }, + { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_cam_deinit_obj) }, + { MP_ROM_QSTR(MP_QSTR_jpeg), MP_ROM_PTR(&machine_cam_jpeg_obj) }, + { MP_ROM_QSTR(MP_QSTR_yuyv), MP_ROM_PTR(&machine_cam_yuyv_obj) }, + + { MP_ROM_QSTR(MP_QSTR_show_start), MP_ROM_PTR(&machine_cam_show_start_obj) }, + { MP_ROM_QSTR(MP_QSTR_show_stop), MP_ROM_PTR(&machine_cam_show_stop_obj) }, + // control + { MP_ROM_QSTR(MP_QSTR_flip), MP_ROM_PTR(&machine_cam_flip_obj) }, + { MP_ROM_QSTR(MP_QSTR_mirror), MP_ROM_PTR(&machine_cam_mirror_obj) }, + { MP_ROM_QSTR(MP_QSTR_contrast), MP_ROM_PTR(&machine_cam_contrast_obj) }, + { MP_ROM_QSTR(MP_QSTR_saturation), MP_ROM_PTR(&machine_cam_saturation_obj) }, + { MP_ROM_QSTR(MP_QSTR_brightness), MP_ROM_PTR(&machine_cam_brightness_obj) }, + { MP_ROM_QSTR(MP_QSTR_speffect), MP_ROM_PTR(&machine_cam_speffect_obj) }, + { MP_ROM_QSTR(MP_QSTR_whitebalance), MP_ROM_PTR(&machine_cam_whitebalance_obj) }, + // Constants + { MP_ROM_QSTR(MP_QSTR_WB_NONE), MP_ROM_INT(WB_NONE) }, + { MP_ROM_QSTR(MP_QSTR_WB_SUNNY), MP_ROM_INT(WB_SUNNY) }, + { MP_ROM_QSTR(MP_QSTR_WB_CLOUDY), MP_ROM_INT(WB_CLOUDY) }, + { MP_ROM_QSTR(MP_QSTR_WB_OFFICE), MP_ROM_INT(WB_OFFICE) }, + { MP_ROM_QSTR(MP_QSTR_WB_HOME), MP_ROM_INT(WB_HOME) }, + + { MP_ROM_QSTR(MP_QSTR_EFFECT_NONE), MP_ROM_INT(EFFECT_NONE) }, + { MP_ROM_QSTR(MP_QSTR_EFFECT_NEG), MP_ROM_INT(EFFECT_NEG) }, + { MP_ROM_QSTR(MP_QSTR_EFFECT_BW), MP_ROM_INT(EFFECT_BW) }, + { MP_ROM_QSTR(MP_QSTR_EFFECT_RED), MP_ROM_INT(EFFECT_RED) }, + { MP_ROM_QSTR(MP_QSTR_EFFECT_GREEN), MP_ROM_INT(EFFECT_GREEN) }, + { MP_ROM_QSTR(MP_QSTR_EFFECT_BLUE), MP_ROM_INT(EFFECT_BLUE) }, + { MP_ROM_QSTR(MP_QSTR_EFFECT_RETRO), MP_ROM_INT(EFFECT_RETRO) }, +}; +STATIC MP_DEFINE_CONST_DICT(cam_locals_dict, cam_locals_dict_table); + +MP_DEFINE_CONST_OBJ_TYPE( + machine_cam_type, + MP_QSTR_CAM, + MP_TYPE_FLAG_NONE, + make_new, machine_cam_make_new, + locals_dict, &cam_locals_dict + ); + +#else +volatile uint8_t CAM_rdy = 0; + +void next_img() { +} + +void SnapShot(void *fb) { +} +#endif diff --git a/ports/renesas-ra/machine_lcd.c b/ports/renesas-ra/machine_lcd.c new file mode 100644 index 0000000000000..2ae88f5d8c3e2 --- /dev/null +++ b/ports/renesas-ra/machine_lcd.c @@ -0,0 +1,374 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2023 Vekatech Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/mpconfig.h" +#include "py/runtime.h" +#include "py/mphal.h" +#include "modmachine.h" +#include "hal_data.h" + +void next_img(); +void SnapShot(); +extern volatile uint8_t CAM_rdy; + +#if MODULE_LCD_ENABLED + +#define FT5X06_DOWN 0 +#define FT5X06_UP 1 +#define FT5X06_CONTACT 2 +#define FT5X06_NUM_POINTS 5 +#define FT5X06_REG_TD_STATUS 0x02 + +#define extract_e(t) ((uint8_t)((t).event)) +#define extract_x(t) ((int16_t)(((t).x_msb << 8) | ((t).x_lsb))) +#define extract_y(t) ((int16_t)(((t).y_msb << 8) | ((t).y_lsb))) + +typedef enum +{ + TOUCH_EVENT_NONE, + TOUCH_EVENT_DOWN, + TOUCH_EVENT_HOLD, + TOUCH_EVENT_MOVE, + TOUCH_EVENT_UP +} touch_event_t; + +typedef struct st_touch_coord +{ + uint16_t x; + uint16_t y; + touch_event_t event; +} touch_coord_t; + +typedef struct st_ft5x06_touch +{ + uint8_t x_msb : 4; + uint8_t : 2; + uint8_t event : 2; + uint8_t x_lsb; + + uint8_t y_msb : 4; + uint8_t id : 4; + uint8_t y_lsb : 8; + + uint8_t res1; + uint8_t res2; +} ft5x06_touch_t; + +/* Complete FT5X06 data payload (number of active points + all five touch points) */ + +typedef struct st_touch_data +{ + uint8_t num_stamp_points; + touch_coord_t stamp_point[FT5X06_NUM_POINTS]; +} touch_data_t; + +typedef struct st_ft5x06_payload +{ + uint8_t num_points_active; + ft5x06_touch_t data_raw[FT5X06_NUM_POINTS]; +} ft5x06_payload_t; + +typedef struct _machine_lcd_obj_t { + mp_obj_base_t base; + uint8_t idx; // currently used buffer; + uint8_t isinited; + uint8_t isstarted; + uint8_t ischanged; + mp_hal_pin_obj_t bl; // backlight ctr (ON OFF) + mp_hal_pin_obj_t en; // enable ctr (ON OFF) + mp_hal_pin_obj_t tch; // touch + + uint8_t num_points; + touch_coord_t point[FT5X06_NUM_POINTS]; +} machine_lcd_obj_t; + +static volatile uint8_t I2C_complete = 0; + +touch_data_t locked; + +STATIC machine_lcd_obj_t machine_lcd_obj = {{&machine_lcd_type}, 0, 0, 0, 0, pin_P801, pin_P806, pin_P800, 0}; + +void touch_i2c_callback(i2c_master_callback_args_t *p_args) { + I2C_complete = 1; +} + +void ft5x06_payload_get() { + touch_coord_t new_touch; + ft5x06_payload_t touch_payload; + + /* Clear payload struct */ + memset(&touch_payload, 0, sizeof(ft5x06_payload_t)); + + /* Read the data about the touch point(s) */ + uint8_t reg = FT5X06_REG_TD_STATUS; + + /* Write TD_STATUS address */ + I2C_complete = 0; + R_SCI_I2C_Write(&g_i2c_touch_ctrl, ®, 1, true); + while (!I2C_complete) { + ; // i2c_wait(); + + } + /* Read TD_STATUS through all five TOUCHn_** register sets */ + I2C_complete = 0; + R_SCI_I2C_Read(&g_i2c_touch_ctrl, (uint8_t *)&touch_payload, sizeof(ft5x06_payload_t), false); + while (!I2C_complete) { + ; // i2c_wait(); + + } + if (touch_payload.num_points_active) { + /* Process the raw data for the touch point(s) into useful data */ + for (uint8_t i = 0; i < FT5X06_NUM_POINTS; i++) + { + new_touch.x = (uint16_t)extract_x(touch_payload.data_raw[i]); + new_touch.y = (uint16_t)extract_y(touch_payload.data_raw[i]); + new_touch.event = extract_e(touch_payload.data_raw[i]); + + /* Set event type based on received data */ + switch (new_touch.event) + { + case FT5X06_DOWN: + machine_lcd_obj.point[i].event = TOUCH_EVENT_DOWN; + break; + case FT5X06_UP: + machine_lcd_obj.point[i].event = TOUCH_EVENT_UP; + break; + case FT5X06_CONTACT: + /* Check if the point is moving or not */ + if ((machine_lcd_obj.point[i].x != new_touch.x) || (machine_lcd_obj.point[i].y != new_touch.y)) { + machine_lcd_obj.point[i].event = TOUCH_EVENT_MOVE; + } else { + machine_lcd_obj.point[i].event = TOUCH_EVENT_HOLD; + } + break; + default: + machine_lcd_obj.point[i].event = TOUCH_EVENT_NONE; + break; + } + + /* Set new coordinates */ + machine_lcd_obj.point[i].x = new_touch.x; + machine_lcd_obj.point[i].y = new_touch.y; + } + + /* Pass the number of active touch points through */ + machine_lcd_obj.num_points = touch_payload.num_points_active; + } +} + +void callback_icu(external_irq_callback_args_t *p_args) { // callback_icu + if (g_external_irq11_cfg.channel == p_args->channel) { + ft5x06_payload_get(); + } +} + +void lcd_Vsync_ISR(display_callback_args_t *p_args) { + if (p_args->event == DISPLAY_EVENT_LINE_DETECTION) { + if (CAM_rdy) { + SnapShot(); + next_img(); + } + } +} + +STATIC mp_int_t machine_lcd_set_buffer(mp_obj_t self_in, mp_buffer_info_t *bufinfo, mp_uint_t flags) { + // mp_obj_framebuf_t *self = MP_OBJ_TO_PTR(self_in); + bufinfo->buf = g_display0_cfg.input[0].p_base; + bufinfo->len = g_display0_cfg.input[0].hstride * g_display0_cfg.input[0].vsize * ((g_display0_cfg.input[0].format < DISPLAY_IN_FORMAT_16BITS_RGB565)? 4 : 2); + bufinfo->typecode = 'B'; // view framebuf as bytes + return 0; +} + +STATIC mp_obj_t machine_lcd_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + // check arguments + mp_arg_check_num(n_args, n_kw, 0, 0, false); + + // return self object + return MP_OBJ_FROM_PTR(&machine_lcd_obj); +} + +STATIC mp_obj_t lcd_init(mp_obj_t self_in) { + machine_lcd_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (!self->isinited) { + if (FSP_SUCCESS == R_GLCDC_Open(&g_display0_ctrl, &g_display0_cfg)) { + self->isinited = 1; + ra_gpio_config(self->bl->pin, GPIO_MODE_OUTPUT_PP, GPIO_NOPULL, GPIO_LOW_POWER, 0); + ra_gpio_config(self->en->pin, GPIO_MODE_OUTPUT_PP, GPIO_NOPULL, GPIO_LOW_POWER, 0); + ra_gpio_write(self->bl->pin, 1); + ra_gpio_write(self->en->pin, 1); + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Can't init R_GLCDC")); + } + + ra_gpio_config(self->tch->pin, GPIO_MODE_OUTPUT_PP, GPIO_NOPULL, GPIO_LOW_POWER, 0); + ra_gpio_write(self->tch->pin, 1); + + if (FSP_SUCCESS == R_SCI_I2C_Open(&g_i2c_touch_ctrl, &g_i2c_touch_cfg)) { + /* Enable touch IRQ */ + R_ICU_ExternalIrqOpen(&g_external_irq11_ctrl, &g_external_irq11_cfg); + R_ICU_ExternalIrqEnable(&g_external_irq11_ctrl); + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Can't init R_SCI")); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Olready inited!")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_lcd_init_obj, lcd_init); + +STATIC mp_obj_t lcd_touched(mp_obj_t self_in) { + machine_lcd_obj_t *self = MP_OBJ_TO_PTR(self_in); + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + if (!locked.num_stamp_points) { + if (self->num_points) { + locked.num_stamp_points = (self->num_points > FT5X06_NUM_POINTS)? FT5X06_NUM_POINTS : self->num_points; + + for (uint8_t i = 0; i < locked.num_stamp_points; i++) { + locked.stamp_point[i] = self->point[i]; + } + + self->num_points = 0; + } else { + locked.num_stamp_points = 0; + } + } + + FSP_CRITICAL_SECTION_EXIT; + + return MP_OBJ_NEW_SMALL_INT(locked.num_stamp_points); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_lcd_touched_obj, lcd_touched); + +STATIC mp_obj_t lcd_touches(mp_obj_t self_in) { + // machine_lcd_obj_t *self = MP_OBJ_TO_PTR(self_in); + + const char *ev[] = {"NONE", "DOWN", "HOLD", "MOVE", "UP"}; + + if (!locked.num_stamp_points) { + lcd_touched(self_in); + } + + mp_obj_list_t *list = mp_obj_new_list(locked.num_stamp_points, NULL); + + if (locked.num_stamp_points) { + // Add elements to the list + for (uint8_t i = 0; i < locked.num_stamp_points; i++) { + list->items[i] = mp_obj_new_tuple(3, (mp_obj_t[]) {mp_obj_new_int(locked.stamp_point[i].x), mp_obj_new_int(locked.stamp_point[i].y), mp_obj_new_str(ev[locked.stamp_point[i].event], strlen(ev[locked.stamp_point[i].event]))}); + } + + locked.num_stamp_points = 0; + } + return MP_OBJ_FROM_PTR(list); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_lcd_touches_obj, lcd_touches); + +STATIC mp_obj_t lcd_deinit(mp_obj_t self_in) { + machine_lcd_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (self->isinited) { + if (FSP_SUCCESS == R_GLCDC_Close(&g_display0_ctrl)) { + self->isinited = 0; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Can't close R_GLCDC")); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not inited! call LCD.init() first")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_lcd_deinit_obj, lcd_deinit); + +STATIC mp_obj_t lcd_start(mp_obj_t self_in) { + machine_lcd_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (!self->isstarted) { + if (FSP_SUCCESS == R_GLCDC_Start(&g_display0_ctrl)) { + self->isstarted = 1; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Can't start R_GLCDC")); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Olready started!")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_lcd_start_obj, lcd_start); + +STATIC mp_obj_t lcd_stop(mp_obj_t self_in) { + machine_lcd_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (self->isstarted) { + if (FSP_SUCCESS == R_GLCDC_Stop(&g_display0_ctrl)) { + self->isstarted = 0; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Can't stop R_GLCDC")); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("Not started! call LCD.start() first")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_lcd_stop_obj, lcd_stop); + +/* +STATIC mp_obj_t lcd_changebuf(mp_obj_t self_in, mp_obj_t idx){ + machine_lcd_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_int_t i = mp_obj_get_int(idx); + + self->ischanged = 0; + if(self->isinited && self->isstarted) + if(FSP_SUCCESS == R_GLCDC_BufferChange(&g_display0_ctrl, fb_background[i? 1 : 0], DISPLAY_FRAME_LAYER_1)) + { + self->ischanged = 1; + self->idx = i; + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_lcd_changebuf_obj, lcd_changebuf); +*/ +STATIC const mp_rom_map_elem_t lcd_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_lcd_init_obj) }, + { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_lcd_deinit_obj) }, + { MP_ROM_QSTR(MP_QSTR_start), MP_ROM_PTR(&machine_lcd_start_obj) }, + { MP_ROM_QSTR(MP_QSTR_stop), MP_ROM_PTR(&machine_lcd_stop_obj) }, + { MP_ROM_QSTR(MP_QSTR_touched), MP_ROM_PTR(&machine_lcd_touched_obj) }, + { MP_ROM_QSTR(MP_QSTR_touches), MP_ROM_PTR(&machine_lcd_touches_obj) }, + // control + // { MP_ROM_QSTR(MP_QSTR_changebuf), MP_ROM_PTR(&machine_lcd_changebuf_obj) }, +}; +STATIC MP_DEFINE_CONST_DICT(lcd_locals_dict, lcd_locals_dict_table); + +MP_DEFINE_CONST_OBJ_TYPE( + machine_lcd_type, + MP_QSTR_LCD, + MP_TYPE_FLAG_NONE, + make_new, machine_lcd_make_new, + buffer, machine_lcd_set_buffer, + locals_dict, &lcd_locals_dict + ); + +#endif // MODULE_LCD_ENABLED diff --git a/ports/renesas-ra/main.c b/ports/renesas-ra/main.c index c4cb7cc9df043..c0fce3b06b5ca 100644 --- a/ports/renesas-ra/main.c +++ b/ports/renesas-ra/main.c @@ -44,7 +44,6 @@ #include "extmod/vfs.h" #include "extmod/vfs_fat.h" #include "extmod/vfs_lfs.h" - #include "boardctrl.h" #include "systick.h" #include "pendsv.h" @@ -66,6 +65,7 @@ #if MICROPY_PY_LWIP #include "lwip/init.h" #include "lwip/apps/mdns.h" +#include "lwip/memp.h" #endif #if MICROPY_PY_BLUETOOTH #include "mpbthciport.h" @@ -287,6 +287,9 @@ int main(void) { #if LWIP_MDNS_RESPONDER mdns_resp_init(); #endif + #if MICROPY_HW_ETH_MDC + systick_enable_dispatch(SYSTICK_DISPATCH_LWIP, mod_network_lwip_poll_wrapper); + #endif #endif soft_reset: @@ -340,8 +343,10 @@ int main(void) { #endif #if MICROPY_PY_LWIP + #if MICROPY_PY_NETWORK_ESP_HOSTED mod_network_lwip_init(); #endif + #endif // Initialise the local flash filesystem. // Create it if needed, mount in on /flash, and set it as current dir. diff --git a/ports/renesas-ra/modmachine.c b/ports/renesas-ra/modmachine.c index bc85d9b7f88bb..e6e8ac38c452b 100644 --- a/ports/renesas-ra/modmachine.c +++ b/ports/renesas-ra/modmachine.c @@ -304,6 +304,12 @@ STATIC const mp_rom_map_elem_t machine_module_globals_table[] = { #if MICROPY_HW_HAS_SDHI_CARD { MP_ROM_QSTR(MP_QSTR_SDCard), MP_ROM_PTR(&machine_sdcard_type) }, #endif + #if MODULE_LCD_ENABLED + { MP_ROM_QSTR(MP_QSTR_LCD), MP_ROM_PTR(&machine_lcd_type) }, + #endif + #if MODULE_CAM_ENABLED + { MP_ROM_QSTR(MP_QSTR_CAM), MP_ROM_PTR(&machine_cam_type) }, + #endif { MP_ROM_QSTR(MP_QSTR_PWRON_RESET), MP_ROM_INT(PYB_RESET_POWER_ON) }, { MP_ROM_QSTR(MP_QSTR_HARD_RESET), MP_ROM_INT(PYB_RESET_HARD) }, { MP_ROM_QSTR(MP_QSTR_WDT_RESET), MP_ROM_INT(PYB_RESET_WDT) }, diff --git a/ports/renesas-ra/modmachine.h b/ports/renesas-ra/modmachine.h index 5dbda6bda8ae7..fee32646933b6 100644 --- a/ports/renesas-ra/modmachine.h +++ b/ports/renesas-ra/modmachine.h @@ -42,6 +42,8 @@ extern const mp_obj_type_t machine_i2s_type; extern const mp_obj_type_t machine_uart_type; extern const mp_obj_type_t machine_rtc_type; extern const mp_obj_type_t machine_sdcard_type; +extern const mp_obj_type_t machine_lcd_type; +extern const mp_obj_type_t machine_cam_type; void machine_init(void); diff --git a/ports/renesas-ra/mpconfigboard_common.h b/ports/renesas-ra/mpconfigboard_common.h index f8990f489e3b2..3c35dcddc6116 100644 --- a/ports/renesas-ra/mpconfigboard_common.h +++ b/ports/renesas-ra/mpconfigboard_common.h @@ -49,6 +49,11 @@ #define MICROPY_PY_PYB_LEGACY (1) #endif +// Whether to enable network functions +#ifndef MICROPY_PY_NETWORK +#define MICROPY_PY_NETWORK (0) +#endif + // Whether machine.bootloader() will enter the bootloader via reset, or direct jump. #ifndef MICROPY_HW_ENTER_BOOTLOADER_VIA_RESET #define MICROPY_HW_ENTER_BOOTLOADER_VIA_RESET (1) diff --git a/ports/renesas-ra/mpconfigport.h b/ports/renesas-ra/mpconfigport.h index 255605a57e8c0..6c52b941d1668 100644 --- a/ports/renesas-ra/mpconfigport.h +++ b/ports/renesas-ra/mpconfigport.h @@ -176,16 +176,16 @@ #define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "mpy-ra" #endif #ifndef MICROPY_PY_USOCKET -#define MICROPY_PY_USOCKET (1) +#define MICROPY_PY_USOCKET (MICROPY_PY_LWIP) #endif #ifndef MICROPY_PY_USSL -#define MICROPY_PY_USSL (1) +#define MICROPY_PY_USSL (MICROPY_PY_LWIP) #endif #ifndef MICROPY_PY_UWEBSOCKET -#define MICROPY_PY_UWEBSOCKET (1) +#define MICROPY_PY_UWEBSOCKET (MICROPY_PY_LWIP) #endif #ifndef MICROPY_PY_WEBREPL -#define MICROPY_PY_WEBREPL (1) +#define MICROPY_PY_WEBREPL (MICROPY_PY_LWIP) #endif #endif @@ -204,9 +204,12 @@ #if MICROPY_PY_NETWORK_ESP_HOSTED extern const struct _mp_obj_type_t mod_network_esp_hosted_type; -#define MICROPY_HW_NIC_ESP_HOSTED { MP_ROM_QSTR(MP_QSTR_WLAN), MP_ROM_PTR(&mod_network_esp_hosted_type) }, +#define MICROPY_HW_NIC_IF_HOSTED { MP_ROM_QSTR(MP_QSTR_WLAN), MP_ROM_PTR(&mod_network_esp_hosted_type) }, +#elif MICROPY_HW_ETH_MDC +extern const struct _mp_obj_type_t network_lan_type; +#define MICROPY_HW_NIC_IF_HOSTED { MP_ROM_QSTR(MP_QSTR_LAN), MP_ROM_PTR(&network_lan_type) }, #else -#define MICROPY_HW_NIC_ESP_HOSTED +#define MICROPY_HW_NIC_IF_HOSTED #endif #ifndef MICROPY_BOARD_NETWORK_INTERFACES @@ -214,7 +217,7 @@ extern const struct _mp_obj_type_t mod_network_esp_hosted_type; #endif #define MICROPY_PORT_NETWORK_INTERFACES \ - MICROPY_HW_NIC_ESP_HOSTED \ + MICROPY_HW_NIC_IF_HOSTED \ MICROPY_BOARD_NETWORK_INTERFACES \ // Miscellaneous settings diff --git a/ports/renesas-ra/mpnetworkport.c b/ports/renesas-ra/mpnetworkport.c index 8e16c2b1b4f80..9b17c68b5899c 100644 --- a/ports/renesas-ra/mpnetworkport.c +++ b/ports/renesas-ra/mpnetworkport.c @@ -27,10 +27,20 @@ #include "py/runtime.h" #include "py/mphal.h" #include "shared/runtime/softtimer.h" +#include "shared/netutils/netutils.h" +#include "systick.h" +#include "pendsv.h" +#include "extmod/modnetwork.h" #if MICROPY_PY_LWIP - +#include "lwip/netif.h" #include "lwip/timeouts.h" +#include "lwip/dns.h" +#include "lwip/dhcp.h" +#include "lwip/apps/mdns.h" + +// Poll lwIP every 128ms +#define LWIP_TICK(tick) (((tick) & ~(SYSTICK_DISPATCH_NUM_SLOTS - 1) & 0x7f) == 0) static mp_sched_node_t network_poll_node; static soft_timer_entry_t network_timer; @@ -71,4 +81,17 @@ void mod_network_lwip_init(void) { soft_timer_reinsert(&network_timer, 50); timer_started = true; } + +STATIC void pyb_lwip_poll(void) { + + // Run the lwIP internal updates + sys_check_timeouts(); +} + +void mod_network_lwip_poll_wrapper(uint32_t ticks_ms) { + if (LWIP_TICK(ticks_ms)) { + pendsv_schedule_dispatch(PENDSV_DISPATCH_LWIP, pyb_lwip_poll); + } +} + #endif // MICROPY_PY_LWIP diff --git a/ports/renesas-ra/network_lan.c b/ports/renesas-ra/network_lan.c new file mode 100644 index 0000000000000..9e02a9a7e26bf --- /dev/null +++ b/ports/renesas-ra/network_lan.c @@ -0,0 +1,186 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/runtime.h" +#include "py/mphal.h" +#include "extmod/modnetwork.h" +#include "eth.h" + +#if defined(MICROPY_HW_ETH_MDC) + +#include "lwip/netif.h" + +typedef struct _network_lan_obj_t { + mp_obj_base_t base; + eth_t *eth; +} network_lan_obj_t; + +STATIC const network_lan_obj_t network_lan_eth0 = { { &network_lan_type }, ð_instance }; + +STATIC void network_lan_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + network_lan_obj_t *self = MP_OBJ_TO_PTR(self_in); + struct netif *netif = eth_netif(self->eth); + int status = eth_link_status(self->eth); + mp_printf(print, "", + status, + netif->ip_addr.addr & 0xff, + netif->ip_addr.addr >> 8 & 0xff, + netif->ip_addr.addr >> 16 & 0xff, + netif->ip_addr.addr >> 24 + ); +} + +STATIC mp_obj_t network_lan_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + mp_arg_check_num(n_args, n_kw, 0, 0, false); + const network_lan_obj_t *self = &network_lan_eth0; + eth_init(self->eth, MP_HAL_MAC_ETH0); + return MP_OBJ_FROM_PTR(self); +} + +STATIC mp_obj_t network_lan_active(size_t n_args, const mp_obj_t *args) { + network_lan_obj_t *self = MP_OBJ_TO_PTR(args[0]); + if (n_args == 1) { + return mp_obj_new_bool(eth_link_status(self->eth)); + } else { + int ret; + if (mp_obj_is_true(args[1])) { + ret = eth_start(self->eth); + } else { + ret = eth_stop(self->eth); + } + if (ret < 0) { + mp_raise_OSError(-ret); + } + return mp_const_none; + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(network_lan_active_obj, 1, 2, network_lan_active); + +STATIC mp_obj_t network_lan_isconnected(mp_obj_t self_in) { + network_lan_obj_t *self = MP_OBJ_TO_PTR(self_in); + return mp_obj_new_bool(eth_link_status(self->eth) == 3); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(network_lan_isconnected_obj, network_lan_isconnected); + +STATIC mp_obj_t network_lan_ifconfig(size_t n_args, const mp_obj_t *args) { + network_lan_obj_t *self = MP_OBJ_TO_PTR(args[0]); + return mod_network_nic_ifconfig(eth_netif(self->eth), n_args - 1, args + 1); +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(network_lan_ifconfig_obj, 1, 2, network_lan_ifconfig); + +STATIC mp_obj_t network_lan_status(size_t n_args, const mp_obj_t *args) { + network_lan_obj_t *self = MP_OBJ_TO_PTR(args[0]); + (void)self; + + if (n_args == 1) { + // No arguments: return link status + return MP_OBJ_NEW_SMALL_INT(eth_link_status(self->eth)); + } + + mp_raise_ValueError(MP_ERROR_TEXT("unknown status param")); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(network_lan_status_obj, 1, 2, network_lan_status); + +STATIC mp_obj_t network_lan_config(size_t n_args, const mp_obj_t *args, mp_map_t *kwargs) { + network_lan_obj_t *self = MP_OBJ_TO_PTR(args[0]); + + if (kwargs->used == 0) { + // Get config value + if (n_args != 2) { + mp_raise_TypeError(MP_ERROR_TEXT("must query one param")); + } + + switch (mp_obj_str_get_qstr(args[1])) { + case MP_QSTR_mac: { + return mp_obj_new_bytes(ð_netif(self->eth)->hwaddr[0], 6); + } + default: + mp_raise_ValueError(MP_ERROR_TEXT("unknown config param")); + } + } else { + // Set config value(s) + if (n_args != 1) { + mp_raise_TypeError(MP_ERROR_TEXT("can't specify pos and kw args")); + } + + for (size_t i = 0; i < kwargs->alloc; ++i) { + if (MP_MAP_SLOT_IS_FILLED(kwargs, i)) { + mp_map_elem_t *e = &kwargs->table[i]; + switch (mp_obj_str_get_qstr(e->key)) { + case MP_QSTR_mac: { + mp_buffer_info_t bufinfo; + mp_get_buffer_raise(e->value, &bufinfo, MP_BUFFER_READ); + if (bufinfo.len == 6) { + memcpy(g_ether0_mac_address, bufinfo.buf, bufinfo.len); + memcpy(eth_netif(self->eth)->hwaddr, g_ether0_mac_address, eth_netif(self->eth)->hwaddr_len); + if (eth_link_status(self->eth)) { + eth_stop(self->eth); + mp_hal_delay_ms(500); + eth_start(self->eth); + } + } else { + mp_raise_ValueError(MP_ERROR_TEXT("MAC address must be 6 bytes long")); + } + break; + } + case MP_QSTR_trace: { + eth_set_trace(self->eth, mp_obj_get_int(e->value)); + break; + } + case MP_QSTR_low_power: { + eth_low_power_mode(self->eth, mp_obj_get_int(e->value)); + break; + } + default: + mp_raise_ValueError(MP_ERROR_TEXT("unknown config param")); + } + } + } + + return mp_const_none; + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(network_lan_config_obj, 1, network_lan_config); + +STATIC const mp_rom_map_elem_t network_lan_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_active), MP_ROM_PTR(&network_lan_active_obj) }, + { MP_ROM_QSTR(MP_QSTR_isconnected), MP_ROM_PTR(&network_lan_isconnected_obj) }, + { MP_ROM_QSTR(MP_QSTR_ifconfig), MP_ROM_PTR(&network_lan_ifconfig_obj) }, + { MP_ROM_QSTR(MP_QSTR_status), MP_ROM_PTR(&network_lan_status_obj) }, + { MP_ROM_QSTR(MP_QSTR_config), MP_ROM_PTR(&network_lan_config_obj) }, +}; +STATIC MP_DEFINE_CONST_DICT(network_lan_locals_dict, network_lan_locals_dict_table); + +MP_DEFINE_CONST_OBJ_TYPE( + network_lan_type, + MP_QSTR_LAN, + MP_TYPE_FLAG_NONE, + make_new, network_lan_make_new, + print, network_lan_print, + locals_dict, &network_lan_locals_dict + ); + +#endif // defined(MICROPY_HW_ETH_MDC) diff --git a/ports/renesas-ra/ra/ra_config.h b/ports/renesas-ra/ra/ra_config.h index a2df775c8902b..1bcb4e5cce8dd 100644 --- a/ports/renesas-ra/ra/ra_config.h +++ b/ports/renesas-ra/ra/ra_config.h @@ -33,7 +33,7 @@ #define SCI_TX_BUF_SIZE 128 #define SCI_RX_BUF_SIZE 256 #define PCLK 48000000 -#elif defined(RA6M1) | defined(RA6M2) +#elif defined(RA6M1) | defined(RA6M2) | defined(RA6M3) #define SCI_CH_MAX 10 #define SCI_CH_NUM 4 #define SCI_TX_BUF_SIZE 128 diff --git a/ports/renesas-ra/ra/ra_sci.c b/ports/renesas-ra/ra/ra_sci.c index 81f3ff9675b5e..5297898046e80 100644 --- a/ports/renesas-ra/ra/ra_sci.c +++ b/ports/renesas-ra/ra/ra_sci.c @@ -1388,7 +1388,7 @@ void ra_sci_init_with_flow(uint32_t ch, uint32_t tx_pin, uint32_t rx_pin, uint32 sci_reg->SEMR = (uint8_t)0xc0; ra_sci_set_baud(ch, baud); delay_us(10); - sci_reg->SCR = (uint8_t)0x50; + sci_reg->SCR = (uint8_t)0x70; ra_sci_irq_enable(ch); ra_enable_irq(state); if (!ra_sci_init_flag[idx]) { diff --git a/ports/renesas-ra/rng.c b/ports/renesas-ra/rng.c index 4efee2d21ce8f..c273b4bdb7a30 100644 --- a/ports/renesas-ra/rng.c +++ b/ports/renesas-ra/rng.c @@ -33,7 +33,12 @@ #if MICROPY_HW_ENABLE_RNG #include "rng.h" +#if defined(RA6M3) +#include "hw_sce_private.h" +#include "hw_sce_trng_private.h" +#elif defined(RA6M5) #include "r_sce.h" +#endif uint32_t rng_read(void) { uint32_t random_data[4]; @@ -41,10 +46,15 @@ uint32_t rng_read(void) { if (initialized == false) { initialized = true; + #if defined(RA6M3) + HW_SCE_McuSpecificInit(); + } + HW_SCE_RNG_Read(random_data); + #elif defined(RA6M5) R_SCE_Open(&sce_ctrl, &sce_cfg); } - R_SCE_RandomNumberGenerate(random_data); + #endif return random_data[0]; } diff --git a/ports/renesas-ra/uart.c b/ports/renesas-ra/uart.c index 47c793e7d3b29..915603cfbdd31 100644 --- a/ports/renesas-ra/uart.c +++ b/ports/renesas-ra/uart.c @@ -78,7 +78,9 @@ static void uart_rx_cb(uint32_t ch, int d) { #endif #if MICROPY_HW_ENABLE_UART_REPL - ringbuf_put(&stdin_ringbuf, d); + if (self->attached_to_repl) { + ringbuf_put(&stdin_ringbuf, d); + } #endif // Check the flags to see if the user handler should be called