8000 mimxrt/MSC: Include support for the MIMXRT117x devices. · micropython/micropython@ea2317d · GitHub
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robert-hhrobert-hh
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mimxrt/MSC: Include support for the MIMXRT117x devices.
1 parent e04a9c9 commit ea2317d

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3 files changed

+13
-11
lines changed

3 files changed

+13
-11
lines changed

‎ports/mimxrt/Makefile

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -212,7 +212,6 @@ SHARED_SRC_C += \
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shared/runtime/pyexec.c \
213213
shared/runtime/softtimer.c \
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shared/runtime/stdout_helpers.c \
215-
shared/runtime/tinyusb_helpers.c \
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shared/runtime/sys_stdio_mphal.c \
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shared/timeutils/timeutils.c \
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‎ports/mimxrt/boards/MIMXRT1170_EVK/mpconfigboard.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,8 @@
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#define MICROPY_HW_BOARD_NAME "i.MX RT1170 EVK"
22
#define MICROPY_HW_MCU_NAME "MIMXRT1176DVMAA"
3+
4+
#define MICROPY_HW_USB_MSC (1)
5+
36
#define MICROPY_EVENT_POLL_HOOK \
47
do { \
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extern void mp_handle_pending(bool); \

‎ports/mimxrt/flash.c

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -32,17 +32,17 @@
3232
void flash_init(void) {
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// Upload the custom flash configuration
3434
// This should be performed by the boot ROM but for some reason it is not.
35-
FLEXSPI_UpdateLUT(FLEXSPI, 0,
35+
FLEXSPI_UpdateLUT(BOARD_FLEX_SPI, 0,
3636
qspiflash_config.memConfig.lookupTable,
3737
ARRAY_SIZE(qspiflash_config.memConfig.lookupTable));
3838

3939
// Configure FLEXSPI IP FIFO access.
40-
FLEXSPI->MCR0 &= ~(FLEXSPI_MCR0_ARDFEN_MASK);
41-
FLEXSPI->MCR0 &= ~(FLEXSPI_MCR0_ATDFEN_MASK);
42-
FLEXSPI->MCR0 |= FLEXSPI_MCR0_ARDFEN(0);
43-
FLEXSPI->MCR0 |= FLEXSPI_MCR0_ATDFEN(0);
40+
BOARD_FLEX_SPI->MCR0 &= ~(FLEXSPI_MCR0_ARDFEN_MASK);
41+
BOARD_FLEX_SPI->MCR0 &= ~(FLEXSPI_MCR0_ATDFEN_MASK);
42+
BOARD_FLEX_SPI->MCR0 |= FLEXSPI_MCR0_ARDFEN(0);
43+
BOARD_FLEX_SPI->MCR0 |= FLEXSPI_MCR0_ATDFEN(0);
4444

45-
FLEXSPI_EnableIPParallelMode(FLEXSPI, true);
45+
FLEXSPI_EnableIPParallelMode(BOARD_FLEX_SPI, true);
4646
}
4747

4848
// flash_erase_block(erase_addr)
@@ -54,7 +54,7 @@ status_t flash_erase_block(uint32_t erase_addr) {
5454
SCB_DisableDCache();
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__disable_irq();
5656

57-
status = flexspi_nor_flash_erase_block(FLEXSPI, erase_addr);
57+
status = flexspi_nor_flash_erase_block(BOARD_FLEX_SPI, erase_addr);
5858

5959
__enable_irq();
6060
SCB_EnableDCache();
@@ -71,7 +71,7 @@ status_t flash_erase_sector(uint32_t erase_addr) {
7171
SCB_DisableDCache();
7272
__disable_irq();
7373

74-
status = flexspi_nor_flash_erase_sector(FLEXSPI, erase_addr);
74+
status = flexspi_nor_flash_erase_sector(BOARD_FLEX_SPI, erase_addr);
7575

7676
__enable_irq();
7777
SCB_EnableDCache();
@@ -83,7 +83,7 @@ status_t flash_erase_sector(uint32_t erase_addr) {
8383
// read length_byte data to the source address
8484
// It is just a shim to provide the same structure for read_block and write_block.
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void inline flash_read_block(uint32_t src_addr, uint8_t *dest, uint32_t length) {
86-
memcpy(dest, (uint8_t *)(FlexSPI_AMBA_BASE + src_addr), length);
86+
memcpy(dest, (uint8_t *)(BOARD_FLEX_SPI_ADDR_BASE + src_addr), length);
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}
8888

8989
// flash_write_block(flash_dest_addr_bytes, data_source, length_bytes)
@@ -114,7 +114,7 @@ status_t flash_write_block(uint32_t dest_addr, const uint8_t *src, uint32_t leng
114114

115115
__disable_irq();
116116

117-
status = flexspi_nor_flash_page_program(FLEXSPI, dest_addr, (uint32_t *)src, size);
117+
status = flexspi_nor_flash_page_program(BOARD_FLEX_SPI, dest_addr, (uint32_t *)src, size);
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119119
__enable_irq();
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