10000 mimxrt/flexspi_nor_c: Set the flash CLK frequency on boot. · micropython/micropython@b40abbc · GitHub
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robert-hhrobert-hh
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mimxrt/flexspi_nor_c: Set the flash CLK frequency on boot.
The flash clock frequency may have been set to a different value by a bootloader. Set the frequency according to the configured value. Use a table of pre-calculated dividers for PFD_480 and the flespi PODF to get the closest value for the flash frequency, achieving: 30 -> 30.85 MHz 50 -> 49.65 MHz 60 -> 60 MHz 75 -> 75.13 MHz 80 -> 80 MHz 100 -> 99.31 Mhz 133 -> 132.92 MHz 166 -> 166.15 MHz Signed-off-by: robert-hh <robert@hammelrath.com>
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4 files changed

+63
-6
lines changed

4 files changed

+63
-6
lines changed

‎ports/mimxrt/flash.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,8 @@
2929
void flash_init(void) {
3030
// Upload the custom flash configuration
3131
// And fix the entry for PAGEPROGRAM_QUAD
32-
flexspi_nor_update_lut();
32+
// Update the flash CLK
33+
flexspi_nor_update_lut_clk();
3334

3435
// Configure FLEXSPI IP FIFO access.
3536
BOARD_FLEX_SPI->MCR0 &= ~(FLEXSPI_MCR0_ARDFEN_MASK);

‎ports/mimxrt/hal/flexspi_hyper_flash.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
#include "fsl_clock.h"
1010
#include "flexspi_hyper_flash.h"
1111

12-
void flexspi_nor_update_lut(void) {
12+
void flexspi_nor_update_lut_clk(void) {
1313
}
1414

1515
// Copy of a few (pseudo-)functions from fsl_clock.h, which were nor reliably

‎ports/mimxrt/hal/flexspi_nor_flash.c

Lines changed: 59 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,9 @@
3838
#include "flexspi_nor_flash.h"
3939
#include "flexspi_flash_config.h"
4040

41+
bool flash_busy_status_pol = 0;
42+
bool flash_busy_status_offset = 0;
43+
4144
uint32_t LUT_pageprogram_quad[4] = {
4245
// 10 Page Program - quad mode
4346
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32, RADDR_SDR, FLEXSPI_1PAD, 24),
@@ -54,16 +57,69 @@ uint32_t LUT_write_status[4] = {
5457
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
5558
};
5659

57-
void flexspi_nor_update_lut(void) {
60+
#if !defined(MIMXRT117x_SERIES)
61+
typedef struct _ps_div_t {
62+
uint8_t pfd480_div;
63+
uint8_t podf_div;
64+
} ps_div_t;
65+
66+
static ps_div_t div_table_mhz[] = {
67+
{ 35, 8 }, // Entry 0 is out of range
68+
{ 35, 8 }, // 30 -> 30.85 MHz
69+
{ 29, 6 }, // 50 -> 49.65 MHz
70+
{ 18, 8 }, // 60 -> 60 MHz
71+
{ 23, 5 }, // 75 -> 75.13 MHz
72+
{ 18, 6 }, // 80 -> 80 MHz
73+
{ 29, 3 }, // 100 -> 99.31 Mhz
74+
{ 13, 5 }, // 133 -> 132.92 MHz
75+
{ 26, 2 } // 166 -> 166.15 MHz
76+
};
77+
#endif
78+
79+
__attribute__((section(".ram_functions"))) void flexspi_nor_update_lut_clk(void) {
80+
// Create a local copy of the LookupTable. Modify the entry for WRITESTATUSREG
81+
// Add an entry for PAGEPROGRAM_QUAD.
5882
uint32_t lookuptable_copy[64];
5983
memcpy(lookuptable_copy, (const uint32_t *)&qspiflash_config.memConfig.lookupTable, 64 * sizeof(uint32_t));
60-
// write WRITESTATUSREG code to entry 10
84+
// write local WRITESTATUSREG code to index 4
6185
memcpy(&lookuptable_copy[NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG * 4],
6286
LUT_write_status, 4 * sizeof(uint32_t));
63-
// write PAGEPROGRAM_QUAD code to entry 10
87+
// write local PAGEPROGRAM_QUAD code to index 10
6488
memcpy(&lookuptable_copy[NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD * 4],
6589
LUT_pageprogram_quad, 4 * sizeof(uint32_t));
90+
// Update the LookupTable.
6691
FLEXSPI_UpdateLUT(BOARD_FLEX_SPI, 0, lookuptable_copy, 64);
92+
93+
#if !defined(MIMXRT117x_SERIES)
94+
volatile uint8_t pfd480_div = div_table_mhz[MICROPY_HW_FLASH_CLK].pfd480_div;
95+
volatile uint8_t podf_div = div_table_mhz[MICROPY_HW_FLASH_CLK].podf_div - 1;
96+
97+
__DSB();
98+
__ISB();
99+
__disable_irq();
100+
SCB_DisableDCache();
101+
while (!FLEXSPI_GetBusIdleStatus(BOARD_FLEX_SPI)) {
102+
}
103+
FLEXSPI_Enable(BOARD_FLEX_SPI, false);
104+
105+
// Disable FlexSPI clock
106+
CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK;
107+
// Changing the clock is OK now.
108+
// Change the PFD
109+
CCM_ANALOG->PFD_480 = (CCM_ANALOG->PFD_480 & ~CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) | CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(pfd480_div);
110+
// Change the flexspi divider
111+
CCM->CSCMR1 = (CCM->CSCMR1 & ~CCM_CSCMR1_FLEXSPI_PODF_MASK) | CCM_CSCMR1_FLEXSPI_PODF(podf_div);
112+
// Re-enable FlexSPI
113+
CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
114+
115+
FLEXSPI_Enable(BOARD_FLEX_SPI, true);
116+
FLEXSPI_SoftwareReset(BOARD_FLEX_SPI);
117+
while (!FLEXSPI_GetBusIdleStatus(BOARD_FLEX_SPI)) {
118+
}
119+
120+
SCB_EnableDCache();
121+
__enable_irq();
122+
#endif
67123
}
68124

69125
void flexspi_nor_reset(FLEXSPI_Type *base) __attribute__((section(".ram_functions")));

‎ports/mimxrt/hal/flexspi_nor_flash.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ extern flexspi_nor_config_t qspiflash_config;
4646

4747
status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId);
4848
status_t flexspi_nor_init(void);
49-
void flexspi_nor_update_lut(void);
49+
void flexspi_nor_update_lut_clk(void);
5050
status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base);
5151
status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address);
5252
status_t flexspi_nor_flash_erase_block(FLEXSPI_Type *base, uint32_t address);

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