8000 mimxrt/boards/MIMXRT1176_clock_config: Fix comments about UART clocks. · micropython/micropython@abb4469 · GitHub
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robert-hhdpgeorge
robert-hh
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dpgeorge
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mimxrt/boards/MIMXRT1176_clock_config: Fix comments about UART clocks.
No functional change, and pretty obvious. Signed-off-by: robert-hh <robert@hammelrath.com>
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‎ports/mimxrt/boards/MIMXRT1176_clock_config.c

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -382,62 +382,62 @@ void BOARD_BootClockRUN(void) {
382382
rootCfg.div = 1;
383383
CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
384384

385-
/* Configure LPUART1 using SYS_PLL3_PFD3_CLK */
385+
/* Configure LPUART1 using SYS_PLL2_PFD3_CLK */
386386
rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Pfd3;
387387
rootCfg.div = 4;
388388
CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
389389

390-
/* Configure LPUART2 using SYS_PLL3_PFD3_CLK */
390+
/* Configure LPUART2 using SYS_PLL2_PFD3_CLK */
391391
rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Pfd3;
392392
rootCfg.div = 4;
393393
CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
394394

395-
/* Configure LPUART3 using SYS_PLL3_PFD3_CLK */
395+
/* Configure LPUART3 using SYS_PLL2_PFD3_CLK */
396396
rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxSysPll2Pfd3;
397397
rootCfg.div = 4;
398398
CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
399399

400-
/* Configure LPUART4 using SYS_PLL3_PFD3_CLK */
400+
/* Configure LPUART4 using SYS_PLL2_PFD3_CLK */
401401
rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxSysPll2Pfd3;
402402
rootCfg.div = 4;
403403
CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
404404

405-
/* Configure LPUART5 using SYS_PLL3_PFD3_CLK */
405+
/* Configure LPUART5 using SYS_PLL2_PFD3_CLK */
406406
rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxSysPll2Pfd3;
407407
rootCfg.div = 4;
408408
CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
409409

410-
/* Configure LPUART6 using SYS_PLL3_PFD3_CLK */
410+
/* Configure LPUART6 using SYS_PLL2_PFD3_CLK */
411411
rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxSysPll2Pfd3;
412412
rootCfg.div = 4;
413413
CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
414414

415-
/* Configure LPUART7 using SYS_PLL3_PFD3_CLK */
415+
/* Configure LPUART7 using SYS_PLL2_PFD3_CLK */
416416
rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxSysPll2Pfd3;
417417
rootCfg.div = 4;
418418
CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
419419

420-
/* Configure LPUART8 using SYS_PLL3_PFD3_CLK */
420+
/* Configure LPUART8 using SYS_PLL2_PFD3_CLK */
421421
rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxSysPll2Pfd3;
422422
rootCfg.div = 4;
423423
CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
424424

425-
/* Configure LPUART9 using SYS_PLL3_PFD3_CLK */
425+
/* Configure LPUART9 using SYS_PLL2_PFD3_CLK */
426426
rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxSysPll2Pfd3;
427427
rootCfg.div = 4;
428428
CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
429429

430-
/* Configure LPUART10 using SYS_PLL3_PFD3_CLK */
430+
/* Configure LPUART10 using SYS_PLL2_PFD3_CLK */
431431
rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxSysPll2Pfd3;
432432
rootCfg.div = 4;
433433
CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
434434

435-
/* Configure LPUART11 using SYS_PLL3_PFD3_CLK */
435+
/* Configure LPUART11 using SYS_PLL2_PFD3_CLK */
436436
rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxSysPll2Pfd3;
437437
rootCfg.div = 4;
438438
CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
439439

440-
/* Configure LPUART12 using SYS_PLL3_PFD3_CLK */
440+
/* Configure LPUART12 using SYS_PLL2_PFD3_CLK */
441441
rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxSysPll2Pfd3;
442442
rootCfg.div = 4;
443443
CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);

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