8000 lpc: Add support for Micromint Banbino 230E · micropython/micropython@8ef9200 · GitHub
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lpc: Add support for Micromint Banbino 230E
Signed-off-by: Martin Ribelotta <martinribelotta@gmail.com>
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‎ports/lpc/board.h

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#include <chip.h>
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#define CONSOLE_UART LPC_USART2
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#define BOARD_CIAA_EDU_NXP_4337
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#ifdef __cplusplus
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extern "C" {
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#endif

‎ports/lpc/boards/lpc_board_ciaa_edu_4337/board.mk

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CHIP=lpc43xx
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BOARD_CFLAGS=-D__USE_LPCOPEN
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BOARD_CFLAGS=-D__USE_LPCOPEN -DCONSOLE_UART=LPC_USART2 -DBOARD_CIAA_EDU_NXP_4337

‎ports/lpc/boards/micromint_bambino230_lpc4337/README

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LPCOpen v3.01
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Release Date: 03/24/2017

‎ports/lpc/boards/micromint_bambino230_lpc4337/board.mk

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CHIP=lpc43xx
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BOARD_CFLAGS=-D__USE_LPCOPEN -DCONSOLE_UART=LPC_USART2 -DBOARD_MICROMINT_BAMBINO_210E

‎ports/lpc/boards/micromint_bambino230_lpc4337/inc/mpconfigboard.h

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#define MICROPY_HW_BOARD_NAME "Micromint BAMBINO 210E"
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#define MICROPY_HW_MCU_NAME "LPC4337"

‎ports/lpc/boards/micromint_bambino230_lpc4337/memory.lds

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/* Specify the memory areas */
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x1a000000, LENGTH = 512K
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RAM (xrw) : ORIGIN = 0x10000000, LENGTH = 32k
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FLASHB (rx) : ORIGIN = 0x1b000000, LENGTH = 512K
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RAMB (rwx) : ORIGIN = 0x10080000, LENGTH = 32K
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RAMC (rwx) : ORIGIN = 0x10088000, LENGTH = 8K
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RAMD (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
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}
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_py_heap_start = ORIGIN(RAMD);
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_py_heap_end = ORIGIN(RAMD) + LENGTH(RAMD);

‎ports/lpc/boards/micromint_bambino230_lpc4337/openocd.cfg

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###############################################################################
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#
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# Copyright 2014, Juan Cecconi (UTN-FRBA, Numetron)
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from this
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# software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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###############################################################################
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#interface ftdi
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interface cmsis-dap
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#cmsis_dap_vid_pid 0x1FC9 0x0081
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#ftdi_vid_pid 0x0403 0x6010
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#ftdi_channel 0
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#ftdi_layout_init 0x0708 0xFFFB
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#ftdi_layout_signal nTRST -data 0x0100
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#ftdi_layout_signal nSRST -data 0x0200
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transport select jtag
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adapter_khz 2000
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set _CHIPNAME lpc4337
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set _M4_JTAG_TAPID 0x4ba00477
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set _M0_JTAG_TAPID 0x0ba01477
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jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M4_JTAG_TAPID
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jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M0_JTAG_TAPID
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target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
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target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
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set _WORKAREASIZE 0x8000
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$_CHIPNAME.m4 configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME lpc2000 0x1a000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 96000 calc_checksum
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reset_config none
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cortex_m reset_config vectreset
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targets $_CHIPNAME.m4
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$_CHIPNAME.m4 configure -event gdb-attach {
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echo "Reset Halt, due to gdb attached...!"
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reset halt
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}
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init
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proc lpc_flash { BIN } {
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init
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halt 0
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flash write_image erase unlock $BIN 0x1a000000 bin
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reset run
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shutdown
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}

‎ports/lpc/boards/micromint_bambino230_lpc4337/src/board.c

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#include "board.h"
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#include <stdint.h>
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/* System configuration variables used by chip driver */
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const uint32_t ExtRateIn = 0;
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const uint32_t OscRateIn = 12000000;
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/* Structure for initial base clock states */
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struct CLK_BASE_STATES {
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CHIP_CGU_BASE_CLK_T clk; /* Base clock */
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CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
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bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
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bool powerdn; /* Set to true if the base clock is initially powered down */
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};
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/* Initial base clock states are mostly on */
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STATIC const struct CLK_BASE_STATES InitClkStates[] = {
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{CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
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#if defined(USE_RMII)
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{CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
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#else
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{CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
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#endif
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/* Clocks derived from dividers */
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{CLK_BASE_LCD, CLKIN_IDIVC, true, false},
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{CLK_BASE_USB1, CLKIN_IDIVD, true, true}
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};
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/* SPIFI high speed pin mode setup */
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STATIC const PINMUX_GRP_T spifipinmuxing[] = {
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{0x3, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI CLK */
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{0x3, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D3 */
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{0x3, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D2 */
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{0x3, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D1 */
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{0x3, 7, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D0 */
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{0x3, 8, (SCU_PINIO_FAST | SCU_MODE_FUNC3)} /* SPIFI CS/SSEL */
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};
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STATIC const PINMUX_GRP_T pinmuxing[] = {
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/* RMII pin group */
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{0x1, 15, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
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{0x0, 0, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)},
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{0x1, 16, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},
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{0x0, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)},
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{0x1, 19, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)},
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{0x1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
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{0x1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
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{0x1, 17, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
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{0x2, 0, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},
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/* Board LEDs */
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{0x2, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
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{0x2, 12, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
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/* I2S */
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{0x3, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
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{0x6, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC4)},
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{0x7, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
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{0x6, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
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{0x7, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
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{0x6, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
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};
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void Board_UART_Init(LPC_USART_T *pUART)
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{
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Chip_SCU_PinMuxSet(0x2, 10, (SCU_MODE_PULLDOWN | SCU_MODE_FUNC2)); /* P2.10 : UART2_TXD */
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Chip_SCU_PinMuxSet(0x2, 11, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)); /* P2.11 : UART2_RX */
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}
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/* Initialize debug output via UART for board */
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void Board_Debug_Init(void)
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{
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Board_UART_Init(CONSOLE_UART);
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Chip_UART_Init(CONSOLE_UART);
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Chip_UART_SetBaudFDR(CONSOLE_UART, 115200);
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Chip_UART_ConfigData(CONSOLE_UART, UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS);
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/* Enable UART Transmit */
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Chip_UART_TXEnable(CONSOLE_UART);
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}
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/* Set up and initialize all required blocks and functions related to the
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board hardware */
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void Board_Init(void)
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{
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/* Sets up DEBUG UART */
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Board_Debug_Init();
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/* Initializes GPIO */
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Chip_GPIO_Init(LPC_GPIO_PORT);
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}
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/* Sets up system pin muxing */
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void Board_SetupMuxing(void)
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{
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/* Setup system level pin muxing */
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Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
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/* SPIFI pin setup is done prior to setting up system clocking */
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Chip_SCU_SetPinMuxing(spifipinmuxing, sizeof(spifipinmuxing) / sizeof(PINMUX_GRP_T));
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}
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/* Set up and initialize clocking prior to call to main */
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void Board_SetupClocking(void)
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{
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int i;
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Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
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/* Reset and enable 32Khz oscillator */
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LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
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LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
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/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
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Divide rate is based on CPU speed and speed of SPI FLASH part. */
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#if (MAX_CLOCK_FREQ > 180000000)
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Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
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#else
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Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
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#endif
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Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
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/* Setup system base clocks and initial states. This won't enable and
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disable individual clocks, but sets up the base clock sources for
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each individual peripheral clock. */
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for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
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Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
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InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
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}
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}
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/* Set up and initialize hardware prior to call to main */
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void Board_SystemInit(void)
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{
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/* Setup system clocking and memory. This is done early to allow the
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application and tools to clear memory and use scatter loading to
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external memory. */
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fpuInit();
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Board_SetupMuxing();
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Board_SetupClocking();
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}

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