10000 stm32/boards/NUCLEO_F767ZI: Fix up comments about HCLK computation. · micropython/micropython@75a3544 · GitHub
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stm32/boards/NUCLEO_F767ZI: Fix up comments about HCLK computation.
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‎ports/stm32/boards/NUCLEO_F767ZI/mpconfigboard.h

Lines changed: 2 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -16,20 +16,12 @@
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#define MICROPY_BOARD_EARLY_INIT NUCLEO_F767ZI_board_early_init
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void NUCLEO_F767ZI_board_early_init(void);
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19-
// HSE is 25MHz
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// VCOClock = HSE * PLLN / PLLM = 25 MHz * 432 / 25 = 432 MHz
21-
// SYSCLK = VCOClock / PLLP = 432 MHz / 2 = 216 MHz
22-
// USB/SDMMC/RNG Clock = VCOClock / PLLQ = 432 MHz / 9 = 48 MHz
19+
// HSE is 8MHz
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#define MICROPY_HW_CLK_PLLM (4)
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#define MICROPY_HW_CLK_PLLN (216)
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#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2)
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#define MICROPY_HW_CLK_PLLQ (9)
27-
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// From the reference manual, for 2.7V to 3.6V
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// 151-180 MHz => 5 wait states
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// 181-210 MHz => 6 wait states
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// 211-216 MHz => 7 wait states
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#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_7 // 210-216 MHz needs 7 wait states
24+
#define MICROPY_HW_FLASH_LATENCY (FLASH_LATENCY_7) // 210-216 MHz needs 7 wait states
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// UART config
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#define MICROPY_HW_UART2_TX (pin_D5)

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