8000 mimxrt/flash.c: Invalidate cache after disabling IRQ. · micropython/micropython@7084737 · GitHub
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mimxrt/flash.c: Invalidate cache after disabling IRQ.
It used to happen before disabling IRQ. This change stopped problems with USB IRQ happening during flash writes. Signed-off-by: robert-hh <robert@hammelrath.com>
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ports/mimxrt/flash.c

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -45,14 +45,13 @@ void flash_init(void) {
4545
__attribute__((section(".ram_functions"))) status_t flash_erase_block(uint32_t erase_addr) {
4646
status_t status = kStatus_Fail;
4747

48-
SCB_CleanInvalidateDCache();
49-
SCB_DisableDCache();
5048
__disable_irq();
49+
SCB_DisableDCache();
5150

5251
status = flexspi_nor_flash_erase_block(BOARD_FLEX_SPI, erase_addr);
5352

54-
__enable_irq();
5553
SCB_EnableDCache();
54+
__enable_irq();
5655

5756
return status;
5857
}
@@ -62,14 +61,13 @@ __attribute__((section(".ram_functions"))) status_t flash_erase_block(uint32_t e
6261
__attribute__((section(".ram_functions"))) status_t flash_erase_sector(uint32_t erase_addr) {
6362
status_t status = kStatus_Fail;
6463

65-
SCB_CleanInvalidateDCache();
66-
SCB_DisableDCache();
6764
__disable_irq();
65+
SCB_DisableDCache();
6866

6967
status = flexspi_nor_flash_erase_sector(BOARD_FLEX_SPI, erase_addr);
7068

71-
__enable_irq();
7269
SCB_EnableDCache();
70+
__enable_irq();
7371

7472
return status;
7573
}
@@ -86,8 +84,6 @@ __attribute__((section(".ram_functions"))) status_t flash_write_block(uint32_t d
8684
status = kStatus_Success; // Nothing to do
8785
} else {
8886

89-
SCB_CleanInvalidateDCache();
90-
SCB_DisableDCache();
9187

9288
// write data in chunks not crossing a page boundary
9389
do {
@@ -98,7 +94,11 @@ __attribute__((section(".ram_functions"))) status_t flash_write_block(uint32_t d
9894
}
9995

10096
__disable_irq();
97+
SCB_DisableDCache();
98+
10199
status = flexspi_nor_flash_page_program(BOARD_FLEX_SPI, dest_addr, (uint32_t *)src, write_length);
100+
101+
SCB_EnableDCache();
102102
__enable_irq();
103103

104104
// Update remaining data length
@@ -109,7 +109,6 @@ __attribute__((section(".ram_functions"))) status_t flash_write_block(uint32_t d
109109
dest_addr += write_length;
110110
} while ((length > 0) && (status == kStatus_Success));
111111

112-
SCB_EnableDCache();
113112

114113
}
115114
return status;

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