10000 mimxrt/boards: Re-generate MIMXRT1052 clock config files. · micropython/micropython@5e195b6 · GitHub
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mimxrt/boards: Re-generate MIMXRT1052 clock config files.
These were regenerated by the NXP Config tool for v2.11. The board_init update was needed to ensure CLOCK_SetMode() is run at the appropriate time during startup. Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
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-103
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3 files changed

+132
-103
lines changed

‎ports/mimxrt/board_init.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,9 @@ void board_init(void) {
5252
SCB_EnableICache();
5353
// Init clock
5454
BOARD_BootClockRUN();
55+
#if !defined(MIMXRT117x_SERIES)
56+
CLOCK_SetMode(kCLOCK_ModeRun);
57+
#endif
5558
SystemCoreClockUpdate();
5659

5760
// Enable IOCON clock

‎ports/mimxrt/boards/MIMXRT1052_clock_config.c

Lines changed: 76 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright 2017-2019 NXP
2+
* Copyright 2022 NXP
33
* All rights reserved.
44
*
55
* SPDX-License-Identifier: BSD-3-Clause
@@ -22,11 +22,11 @@
2222

2323
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
2424
!!GlobalInfo
25-
product: Clocks v5.0
25+
product: Clocks v10.0
2626
processor: MIMXRT1052xxxxB
2727
package_id: MIMXRT1052DVL6B
2828
mcu_data: ksdk2_0
29-
processor_version: 0.0.0
29+
processor_version: 0.12.10
3030
board: IMXRT1050-EVKB
3131
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
3232

@@ -40,8 +40,6 @@ board: IMXRT1050-EVKB
4040
/*******************************************************************************
4141
* Variables
4242
******************************************************************************/
43-
/* System clock frequency. */
44-
extern uint32_t SystemCoreClock;
4543

4644
/*******************************************************************************
4745
************************ BOARD_InitBootClocks function ************************
@@ -64,7 +62,6 @@ called_from_default_init: true
6462
- {id: CLK_1M.outFreq, value: 1 MHz}
6563
- {id: CLK_24M.outFreq, value: 24 MHz}
6664
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
67-
- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
6865
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
6966
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
7067
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
@@ -92,7 +89,7 @@ called_from_default_init: true
9289
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
9390
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
9491
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
95-
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
92+
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
9693
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
9794
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
9895
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
@@ -104,7 +101,7 @@ called_from_default_init: true
104101
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
105102
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
106103
- {id: CCM.SEMC_PODF.scale, value: '8'}
107-
- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
104+
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
108105
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
109106
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
110107
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50' 57AE ;, locked: true}
@@ -125,31 +122,45 @@ called_from_default_init: true
125122
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
126123
- {id: CCM_ANALOG.PLL4.div, value: '47'}
127124
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
128-
- {id: CCM_ANALOG.PLL5.div, value: '40'}
125+
- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
129126
- {id: CCM_ANALOG.PLL5.num, value: '0'}
127+
- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
128+
- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
129+
- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
130130
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
131131
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
132+
- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
132133
sources:
133-
- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
134134
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
135135
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
136136

137137
/*******************************************************************************
138138
* Variables for BOARD_BootClockRUN configuration
139139
******************************************************************************/
140-
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
141-
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
142-
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
140+
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
141+
{
142+
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
143+
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
143144
};
144-
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
145-
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
146-
.numerator = 0, /* 30 bit numerator of fractional loop divider */
147-
.denominator = 1, /* 30 bit denominator of fractional loop divider */
148-
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
145+
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
146+
{
147+
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
148+
.numerator = 0, /* 30 bit numerator of fractional loop divider */
149+
.denominator = 1, /* 30 bit denominator of fractional loop divider */
150+
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
149151
};
150-
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
151-
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
152-
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
152+
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
153+
{
154+
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
155+
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
156+
};
157+
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
158+
{
159+
.loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
160+
.postDivider = 8, /* Divider after PLL */
161+
.numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
162+
.denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
163+
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
153164
};
154165
/*******************************************************************************
155166
* Code for BOARD_BootClockRUN configuration
@@ -213,10 +224,9 @@ void BOARD_BootClockRUN(void) {
213224
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
214225
/* Set Usdhc2 clock source. */
215226
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
216-
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
217-
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
218-
* unchanged.
219-
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
227+
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
228+
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
229+
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
220230
#ifndef SKIP_SYSCLK_INIT
221231
/* Disable Semc clock gate. */
222232
CLOCK_DisableClock(kCLOCK_Semc);
@@ -227,10 +237,9 @@ void BOARD_BootClockRUN(void) {
227237
/* Set Semc clock source. */
228238
CLOCK_SetMux(kCLOCK_SemcMux, 0);
229239
#endif
230-
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
231-
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
232-
* unchanged.
233-
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
240+
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
241+
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
242+
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
234243
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
235244
/* Disable Flexspi clock gate. */
236245
CLOCK_DisableClock(kCLOCK_FlexSpi);
@@ -257,9 +266,9 @@ void BOARD_BootClockRUN(void) {
257266 10000
/* Disable TRACE clock gate. */
258267
CLOCK_DisableClock(kCLOCK_Trace);
259268
/* Set TRACE_PODF. */
260-
CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
269+
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
261270
/* Set Trace clock source. */
262-
CLOCK_SetMux(kCLOCK_TraceMux, 2);
271+
CLOCK_SetMux(kCLOCK_TraceMux, 0);
263272
/* Disable SAI1 clock gate. */
264273
CLOCK_DisableClock(kCLOCK_Sai1);
265274
/* Set SAI1_CLK_PRED. */
@@ -351,10 +360,12 @@ void BOARD_BootClockRUN(void) {
351360
/* Init ARM PLL. */
352361
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
353362
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
354-
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
355-
* unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
356-
* well.*/
363+
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
364+
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
357365
#ifndef SKIP_SYSCLK_INIT
366+
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
367+
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
368+
#endif
358369
/* Init System PLL. */
359370
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
360371
/* Init System pfd0. */
@@ -365,13 +376,10 @@ void BOARD_BootClockRUN(void) {
365376
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
366377
/* Init System pfd3. */
367378
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
368-
/* Disable pfd offset. */
369-
CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
370379
#endif
371380
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
372-
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
373-
* unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
374-
* well.*/
381+
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
382+
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
375383
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
376384
/* Init Usb1 PLL. */
377385
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
@@ -395,21 +403,30 @@ void BOARD_BootClockRUN(void) {
395403
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
396404
/* Enable Audio PLL output. */
< E377 /td>
397405
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
398-
/* DeInit Video PLL. */
399-
CLOCK_DeinitVideoPll();
400-
/* Bypass Video PLL. */
401-
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
402-
/* Set divider for Video PLL. */
403-
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
404-
/* Enable Video PLL output. */
405-
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
406+
/* Init Video PLL. */
407+
uint32_t pllVideo;
408+
/* Disable Video PLL output before initial Video PLL. */
409+
CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
410+
/* Bypass PLL first */
411+
CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
412+
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
413+
CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
414+
CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
415+
pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
416+
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
417+
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
418+
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
419+
CCM_ANALOG->PLL_VIDEO = pllVideo;
420+
while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) {
421+
}
422+
/* Disable bypass for Video PLL. */
423+
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
406424
/* DeInit Enet PLL. */
407425
CLOCK_DeinitEnetPll();
408426
/* Bypass Enet PLL. */
409427
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
410428
/* Set Enet output divider. */
411-
CCM_ANALOG->PLL_ENET =
412-
(CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
429+
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
413430
/* Enable Enet output. */
414431
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
415432
/* Enable Enet25M output. */
@@ -429,8 +446,7 @@ void BOARD_BootClockRUN(void) {
429446
/* Set per clock source. */
430447
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
431448
/* Set lvds1 clock source. */
432-
CCM_ANALOG->MISC1 =
433-
(CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
449+
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
434450
/* Set clock out1 divider. */
435451
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
436452
/* Set clock out1 source. */
@@ -457,13 +473,19 @@ void BOARD_BootClockRUN(void) {
457473
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
458474
/* Set MQS configuration. */
459475
IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
460-
/* Set ENET Tx clock source. */
461-
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
476+
/* Set ENET Ref clock source. */
477+
#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
478+
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
479+
#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
480+
/* Backward compatibility for original bitfield name */
481+
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
482+
#else
483+
#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
484+
#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
462485
/* Set GPT1 High frequency reference clock source. */
463486
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
464487
/* Set GPT2 High frequency reference clock source. */
465488
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
466489
/* Set SystemCoreClock variable. */
467490
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
468-
CLOCK_SetMode(kCLOCK_ModeRun);
469491
}

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